285 static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in __read_delay()
301 			if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)  in __read_delay()
327 		rd_interval = dpcd[offset];  in __read_delay()
340 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_read_clock_recovery_delay()
343 	return __read_delay(aux, dpcd, dp_phy, uhbr, true);  in drm_dp_read_clock_recovery_delay()
347 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_read_channel_eq_delay()
350 	return __read_delay(aux, dpcd, dp_phy, uhbr, false);  in drm_dp_read_channel_eq_delay()
375 					    const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_link_train_clock_recovery_delay()
377 	u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &  in drm_dp_link_train_clock_recovery_delay()
381 	if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)  in drm_dp_link_train_clock_recovery_delay()
399 					const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_link_train_channel_eq_delay()
402 					     dpcd[DP_TRAINING_AUX_RD_INTERVAL] &  in drm_dp_link_train_channel_eq_delay()
805 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_is_type()
808 	return drm_dp_is_branch(dpcd) &&  in drm_dp_downstream_is_type()
809 		dpcd[DP_DPCD_REV] >= 0x11 &&  in drm_dp_downstream_is_type()
822 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_is_tmds()
826 	if (dpcd[DP_DPCD_REV] < 0x11) {  in drm_dp_downstream_is_tmds()
827 		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {  in drm_dp_downstream_is_tmds()
909 static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_downstream_port_count()
911 	u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK;  in drm_dp_downstream_port_count()
913 	if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4)  in drm_dp_downstream_port_count()
920 					  u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_read_extended_dpcd_caps()
932 	if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] &  in drm_dp_read_extended_dpcd_caps()
943 	if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {  in drm_dp_read_extended_dpcd_caps()
946 			    aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]);  in drm_dp_read_extended_dpcd_caps()
950 	if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext)))  in drm_dp_read_extended_dpcd_caps()
953 	drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);  in drm_dp_read_extended_dpcd_caps()
955 	memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext));  in drm_dp_read_extended_dpcd_caps()
974 			  u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_read_dpcd_caps()
978 	ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE);  in drm_dp_read_dpcd_caps()
981 	if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0)  in drm_dp_read_dpcd_caps()
984 	ret = drm_dp_read_extended_dpcd_caps(aux, dpcd);  in drm_dp_read_dpcd_caps()
988 	drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);  in drm_dp_read_dpcd_caps()
1008 				const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_read_downstream_info()
1017 	if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10)  in drm_dp_read_downstream_info()
1024 	len = drm_dp_downstream_port_count(dpcd);  in drm_dp_read_downstream_info()
1028 	if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE)  in drm_dp_read_downstream_info()
1051 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_max_dotclock()
1054 	if (!drm_dp_is_branch(dpcd))  in drm_dp_downstream_max_dotclock()
1057 	if (dpcd[DP_DPCD_REV] < 0x11)  in drm_dp_downstream_max_dotclock()
1062 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)  in drm_dp_downstream_max_dotclock()
1080 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_max_tmds_clock()
1084 	if (!drm_dp_is_branch(dpcd))  in drm_dp_downstream_max_tmds_clock()
1087 	if (dpcd[DP_DPCD_REV] < 0x11) {  in drm_dp_downstream_max_tmds_clock()
1088 		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {  in drm_dp_downstream_max_tmds_clock()
1122 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)  in drm_dp_downstream_max_tmds_clock()
1126 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)  in drm_dp_downstream_max_tmds_clock()
1145 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_min_tmds_clock()
1149 	if (!drm_dp_is_branch(dpcd))  in drm_dp_downstream_min_tmds_clock()
1152 	if (dpcd[DP_DPCD_REV] < 0x11) {  in drm_dp_downstream_min_tmds_clock()
1153 		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {  in drm_dp_downstream_min_tmds_clock()
1188 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_max_bpc()
1192 	if (!drm_dp_is_branch(dpcd))  in drm_dp_downstream_max_bpc()
1195 	if (dpcd[DP_DPCD_REV] < 0x11) {  in drm_dp_downstream_max_bpc()
1196 		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {  in drm_dp_downstream_max_bpc()
1214 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)  in drm_dp_downstream_max_bpc()
1244 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_420_passthrough()
1247 	if (!drm_dp_is_branch(dpcd))  in drm_dp_downstream_420_passthrough()
1250 	if (dpcd[DP_DPCD_REV] < 0x13)  in drm_dp_downstream_420_passthrough()
1257 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)  in drm_dp_downstream_420_passthrough()
1275 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_444_to_420_conversion()
1278 	if (!drm_dp_is_branch(dpcd))  in drm_dp_downstream_444_to_420_conversion()
1281 	if (dpcd[DP_DPCD_REV] < 0x13)  in drm_dp_downstream_444_to_420_conversion()
1286 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)  in drm_dp_downstream_444_to_420_conversion()
1306 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_rgb_to_ycbcr_conversion()
1310 	if (!drm_dp_is_branch(dpcd))  in drm_dp_downstream_rgb_to_ycbcr_conversion()
1313 	if (dpcd[DP_DPCD_REV] < 0x13)  in drm_dp_downstream_rgb_to_ycbcr_conversion()
1318 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)  in drm_dp_downstream_rgb_to_ycbcr_conversion()
1340 		       const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_mode()
1346 	if (!drm_dp_is_branch(dpcd))  in drm_dp_downstream_mode()
1349 	if (dpcd[DP_DPCD_REV] < 0x11)  in drm_dp_downstream_mode()
1406 			     const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_debug()
1411 	bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &  in drm_dp_downstream_debug()
1419 	bool branch_device = drm_dp_is_branch(dpcd);  in drm_dp_downstream_debug()
1467 		clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);  in drm_dp_downstream_debug()
1471 		clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, drm_edid);  in drm_dp_downstream_debug()
1475 		clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, drm_edid);  in drm_dp_downstream_debug()
1479 		bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, drm_edid);  in drm_dp_downstream_debug()
1493 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_subconnector_type()
1497 	if (!drm_dp_is_branch(dpcd))  in drm_dp_subconnector_type()
1500 	if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) {  in drm_dp_subconnector_type()
1501 		type = dpcd[DP_DOWNSTREAMPORT_PRESENT] &  in drm_dp_subconnector_type()
1550 				      const u8 *dpcd,  in drm_dp_set_subconnector_property()  argument
1556 		subconnector = drm_dp_subconnector_type(dpcd, port_cap);  in drm_dp_set_subconnector_property()
1576 				const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_read_sink_count_cap()
1581 		dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 &&  in drm_dp_read_sink_count_cap()
1582 		dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&  in drm_dp_read_sink_count_cap()
2583 				  const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,  in drm_dp_read_lttpr_regs()
2591 	int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size;  in drm_dp_read_lttpr_regs()
2619 				  const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_read_lttpr_common_caps()
2622 	return drm_dp_read_lttpr_regs(aux, dpcd,  in drm_dp_read_lttpr_common_caps()
2640 			       const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_read_lttpr_phy_caps()
2644 	return drm_dp_read_lttpr_regs(aux, dpcd,  in drm_dp_read_lttpr_phy_caps()
3019 bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_as_sdp_supported()
3023 	if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13)  in drm_dp_as_sdp_supported()
3044 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_vsc_sdp_supported()
3048 	if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13)  in drm_dp_vsc_sdp_supported()
3142 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_get_pcon_max_frl_bw()