Lines Matching full:dp0
190 #define DP0_VIDMNGEN0 0x0610 /* DP0 Video Force M Value Register */
191 #define DP0_VIDMNGEN1 0x0614 /* DP0 Video Force N Value Register */
192 #define DP0_VMNGENSTATUS 0x0618 /* DP0 Video Current M Value Register */
193 #define DP0_AUDMNGEN0 0x0628 /* DP0 Audio Force M Value Register */
194 #define DP0_AUDMNGEN1 0x062c /* DP0 Audio Force N Value Register */
195 #define DP0_AMNGENSTATUS 0x0630 /* DP0 Audio Current M Value Register */
269 #define DP0_TPATDAT0 0x06e8 /* DP0 Test Pattern bits 29 to 0 */
270 #define DP0_TPATDAT1 0x06ec /* DP0 Test Pattern bits 59 to 30 */
271 #define DP0_TPATDAT2 0x06f0 /* DP0 Test Pattern bits 89 to 60 */
272 #define DP0_TPATDAT3 0x06f4 /* DP0 Test Pattern bits 119 to 90 */
274 #define AUDCFG0 0x0700 /* DP0 Audio Config0 Register */
275 #define AUDCFG1 0x0704 /* DP0 Audio Config1 Register */
276 #define AUDIFDATA0 0x0708 /* DP0 Audio Info Frame Bytes 3 to 0 */
277 #define AUDIFDATA1 0x070c /* DP0 Audio Info Frame Bytes 7 to 4 */
278 #define AUDIFDATA2 0x0710 /* DP0 Audio Info Frame Bytes 11 to 8 */
279 #define AUDIFDATA3 0x0714 /* DP0 Audio Info Frame Bytes 15 to 12 */
280 #define AUDIFDATA4 0x0718 /* DP0 Audio Info Frame Bytes 19 to 16 */
281 #define AUDIFDATA5 0x071c /* DP0 Audio Info Frame Bytes 23 to 20 */
282 #define AUDIFDATA6 0x0720 /* DP0 Audio Info Frame Bytes 27 to 24 */
301 #define DP0_AUX_PHY_CTRL 0x0820 /* DP0 AUX PHY Control Register */
302 #define DP0_MAIN_PHY_DBG 0x0840 /* DP0 Main PHY Test Debug Register */
1106 /* SSCG and BW27 on DP1 must be set to the same as on DP0 */ in tc_main_link_enable()
1235 /* Enable DP0 to start Link Training */ in tc_main_link_enable()