Lines Matching refs:dsi_write
306 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) in dsi_write() function
385 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(16) in dw_mipi_message_config()
393 dsi_write(dsi, DSI_CMD_MODE_CFG, val); in dw_mipi_message_config()
400 dsi_write(dsi, DSI_VID_MODE_CFG, val); in dw_mipi_message_config()
416 dsi_write(dsi, DSI_GEN_HDR, hdr_val); in dw_mipi_dsi_gen_pkt_hdr_write()
442 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word)); in dw_mipi_dsi_write()
446 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word)); in dw_mipi_dsi_write()
624 dsi_write(dsi, DSI_VID_MODE_CFG, val); in dw_mipi_dsi_video_mode_config()
632 dsi_write(dsi, DSI_PWR_UP, RESET); in dw_mipi_dsi_set_mode()
635 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE); in dw_mipi_dsi_set_mode()
638 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); in dw_mipi_dsi_set_mode()
644 dsi_write(dsi, DSI_LPCLK_CTRL, val); in dw_mipi_dsi_set_mode()
646 dsi_write(dsi, DSI_PWR_UP, POWERUP); in dw_mipi_dsi_set_mode()
651 dsi_write(dsi, DSI_PWR_UP, RESET); in dw_mipi_dsi_disable()
652 dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ); in dw_mipi_dsi_disable()
682 dsi_write(dsi, DSI_PWR_UP, RESET); in dw_mipi_dsi_init()
689 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(0) | in dw_mipi_dsi_init()
718 dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel)); in dw_mipi_dsi_dpi_config()
719 dsi_write(dsi, DSI_DPI_COLOR_CODING, color); in dw_mipi_dsi_dpi_config()
720 dsi_write(dsi, DSI_DPI_CFG_POL, val); in dw_mipi_dsi_dpi_config()
730 dsi_write(dsi, DSI_PCKHDL_CFG, val); in dw_mipi_dsi_packet_handler_config()
744 dsi_write(dsi, DSI_VID_PKT_SIZE, in dw_mipi_dsi_video_packet_config()
757 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(0) | LPRX_TO_CNT(0)); in dw_mipi_dsi_command_mode_config()
763 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); in dw_mipi_dsi_command_mode_config()
764 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); in dw_mipi_dsi_command_mode_config()
823 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); in dw_mipi_dsi_line_timer_config()
826 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); in dw_mipi_dsi_line_timer_config()
829 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); in dw_mipi_dsi_line_timer_config()
842 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); in dw_mipi_dsi_vertical_timing_config()
843 dsi_write(dsi, DSI_VID_VSA_LINES, vsa); in dw_mipi_dsi_vertical_timing_config()
844 dsi_write(dsi, DSI_VID_VFP_LINES, vfp); in dw_mipi_dsi_vertical_timing_config()
845 dsi_write(dsi, DSI_VID_VBP_LINES, vbp); in dw_mipi_dsi_vertical_timing_config()
871 dsi_write(dsi, DSI_PHY_TMR_CFG, in dw_mipi_dsi_dphy_timing_config()
874 dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000)); in dw_mipi_dsi_dphy_timing_config()
876 dsi_write(dsi, DSI_PHY_TMR_CFG, in dw_mipi_dsi_dphy_timing_config()
882 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, in dw_mipi_dsi_dphy_timing_config()
894 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) | in dw_mipi_dsi_dphy_interface_config()
901 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK in dw_mipi_dsi_dphy_init()
903 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); in dw_mipi_dsi_dphy_init()
904 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR); in dw_mipi_dsi_dphy_init()
905 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); in dw_mipi_dsi_dphy_init()
913 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK | in dw_mipi_dsi_dphy_enable()
932 dsi_write(dsi, DSI_INT_MSK0, 0); in dw_mipi_dsi_clear_err()
933 dsi_write(dsi, DSI_INT_MSK1, 0); in dw_mipi_dsi_clear_err()
1123 dsi_write(dsi, DSI_VID_MODE_CFG, mode_cfg); in dw_mipi_dsi_debugfs_write()