drm/bridge/sil-sii8620.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
9  * Copyright (C) 2013-2014 Silicon Image, Inc.
33 /* System Control #1, default value: 0x00 */
44 /* System Control DPD, default value: 0x90 */
323 /* I2C Device Address re-assignment */
648 /* E-MSC General Control, default value: 0x80 */
659 /* E-MSC Comma ErrorCNT, default value: 0x03 */
664 /* E-MSC RFIFO ByteCnt, default value: 0x00 */
678 /* E-MSC 1st Interrupt, default value: 0x00 */
689 /* E-MSC Interrupt Mask, default value: 0x00 */
692 /* I2C E-MSC XMIT FIFO Write Port, default value: 0x00 */
695 /* I2C E-MSC RCV FIFO Write Port, default value: 0x00 */
698 /* E-MSC 2nd Interrupt, default value: 0x00 */
702 /* E-MSC Interrupt Mask, default value: 0x00 */
706 /* MHL Top Ctl, default value: 0x00 */
712 /* MHL DataPath 1st Ctl, default value: 0xbc */
718 /* MHL DataPath 2nd Ctl, default value: 0xbb */
723 /* MHL DataPath 3rd Ctl, default value: 0x2f */
730 /* MHL DataPath 4th Ctl, default value: 0x48 */
735 /* MHL DataPath 5th Ctl, default value: 0x48 */
740 /* MHL DataPath 6th Ctl, default value: 0x3f */
748 /* MHL PLL 1st Ctl, default value: 0x05 */
771 /* MHL PLL 3rd Ctl, default value: 0x80 */
778 /* MHL CBUS 1st Ctl, default value: 0x12 */
796 /* MHL CBUS 2nd Ctl, default value: 0x03 */
803 /* MHL CoC 1st Ctl, default value: 0xc3 */
809 /* MHL CoC 2nd Ctl, default value: 0x87 */
814 /* MHL CoC 4th Ctl, default value: 0x00 */
818 /* MHL CoC 5th Ctl, default value: 0x28 */
823 /* MHL CoC 6th Ctl, default value: 0x0d */
826 /* MHL DoC 1st Ctl, default value: 0x18 */
833 /* MHL DataPath 7th Ctl, default value: 0x2a */
842 /* MHL DataPath 8th Ctl, default value: 0x06 */
853 /* MHL3 Tx Zone Ctl, default value: 0x00 */
964 /* HSIC Div Ctl, default value: 0x05 */
1015 /* TPI System Control, default value: 0x00 */
1112 /* CoC 1st Ctl, default value: 0x40 */
1115 /* CoC 2nd Ctl, default value: 0x0a */
1120 /* CoC 3rd Ctl, default value: 0x14 */
1125 /* CoC 4th Ctl, default value: 0x40 */
1130 /* CoC 7th Ctl, default value: 0x00 */
1136 /* CoC 8th Ctl, default value: 0x06 */
1144 /* CoC 10th Ctl, default value: 0x00 */
1147 /* CoC 11th Ctl, default value: 0x00 */
1150 /* CoC 12th Ctl, default value: 0x00 */
1153 /* CoC 13th Ctl, default value: 0x0f */
1156 /* CoC 14th Ctl, default value: 0x0a */
1161 /* CoC 15th Ctl, default value: 0x0a */
1166 /* CoC 16th Ctl, default value: 0x00 */
1171 /* CoC 18th Ctl, default value: 0x32 */
1176 /* CoC 21st Ctl, default value: 0x00 */
1181 /* CoC 22nd Ctl, default value: 0x00 */
1195 /* CoC Misc Ctl, default value: 0x00 */
1199 /* CoC 24th Ctl, default value: 0x00 */
1204 /* CoC 25th Ctl, default value: 0x00 */
1209 /* CoC 26th Ctl, default value: 0x00 */
1214 /* CoC 27th Ctl, default value: 0x00 */
1229 /* DoC 1st Ctl, default value: 0x40 */
1232 /* DoC 7th Ctl, default value: 0x00 */
1239 /* DoC 8th Ctl, default value: 0x00 */
1247 /* DoC 9th Ctl, default value: 0x00 */
1254 /* DoC 10th Ctl, default value: 0x00 */
1257 /* DoC 11th Ctl, default value: 0x00 */
1260 /* DoC 15th Ctl, default value: 0x00 */