Lines Matching +full:e +full:- +full:ddc

1 /* SPDX-License-Identifier: GPL-2.0-only */
9  * Copyright (C) 2013-2014 Silicon Image, Inc.
243 /* LM DDC, default value: 0x80 */
252 /* DDC I2C Manual, default value: 0x03 */
263 /* DDC I2C Target Slave Address, default value: 0x00 */
267 /* DDC I2C Target Segment Address, default value: 0x00 */
270 /* DDC I2C Target Offset Address, default value: 0x00 */
273 /* DDC I2C Data In count #1, default value: 0x00 */
276 /* DDC I2C Data In count #2, default value: 0x00 */
280 /* DDC I2C Status, default value: 0x04 */
290 /* DDC I2C Command, default value: 0x70 */
301 /* DDC I2C FIFO Data In/Out, default value: 0x00 */
304 /* DDC I2C Data Out Counter, default value: 0x00 */
309 /* DDC I2C Delay Count, default value: 0x14 */
323 /* I2C Device Address re-assignment */
623 /* EDID DDC Segment Pointer, default value: 0x00 */
648 /* E-MSC General Control, default value: 0x80 */
659 /* E-MSC Comma ErrorCNT, default value: 0x03 */
664 /* E-MSC RFIFO ByteCnt, default value: 0x00 */
678 /* E-MSC 1st Interrupt, default value: 0x00 */
689 /* E-MSC Interrupt Mask, default value: 0x00 */
692 /* I2C E-MSC XMIT FIFO Write Port, default value: 0x00 */
695 /* I2C E-MSC RCV FIFO Write Port, default value: 0x00 */
698 /* E-MSC 2nd Interrupt, default value: 0x00 */
702 /* E-MSC Interrupt Mask, default value: 0x00 */
1379 /* CBUS DDC Abort Interrupt, default value: 0x00 */
1382 /* CBUS DDC Abort Interrupt Mask, default value: 0x00 */