drm/bridge/sil-sii8620.h

37 #define BIT_SYS_CTRL1_OTPADROPOVR_SET		BIT(5)
48 #define BIT_DPD_PDNRX12				BIT(5)
58 #define BIT_DCTL_CTS_TCK_PHASE			BIT(5)
69 #define BIT_PWD_SRST_CBUS_RST_SW_EN		BIT(5)
90 #define BIT_VID_OVRRD_MINIVSYNC_ON		BIT(5)
124 #define BIT_CTRL1_GPIO_I_8			BIT(5)
151 /* Interrupt Source #5, default value: 0x00 */
163 /* Interrupt #5 Mask, default value: 0x00 */
171 #define BIT_HPD_CTRL_HPD_HIGH			BIT(5)
182 #define BIT_CTRL_GPIO_I_4			BIT(5)
216 #define BIT_BIST_START_SEL			BIT(5)
247 #define BIT_LM_DDC_VIDEO_MUTE_EN		BIT(5)
256 #define BIT_DDC_MANUAL_DSDA			BIT(5)
283 #define BIT_DDC_STATUS_DDC_NO_ACK		BIT(5)
293 #define BIT_DDC_CMD_SDA_DEL_EN			BIT(5)
331 #define BIT_UTSRST_FC_SRST			BIT(5)
368 #define BIT_TTXINTL_TTX_INTR5			BIT(5)
379 #define BIT_TTXINTH_TTX_INTR13			BIT(5)
506 /* MHL Tx Control 6th, default value: 0xa0 */
515 #define BIT_PKT_FILTER_0_DROP_MPEG_PKT		BIT(5)
535 #define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_NEW_CP	BIT(5)
543 #define BIT_RX_HDMI_CTRL0_BYP_DVIFILT_SYNC	BIT(5)
564 #define BIT_RX_HDMI_CLR_BUFFER_USE_AIF4VSI	BIT(5)
583 #define BIT_INTR9_EDID_DONE			BIT(5)
593 #define BIT_TPI_CBUS_START_RCPE_REPLY_START	BIT(5)
604 #define BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP	BIT(5)
629 #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_DONE	BIT(5)
652 #define BIT_GENCTL_SPI_MISO_EDGE		BIT(5)
675 #define BIT_SPIBURSTSTAT_SPI_SRST		BIT(5)
682 #define BIT_EMSCINTR_EMSC_RFIFO_READ_ERR	BIT(5)
730 /* MHL DataPath 4th Ctl, default value: 0x48 */
735 /* MHL DataPath 5th Ctl, default value: 0x48 */
740 /* MHL DataPath 6th Ctl, default value: 0x3f */
814 /* MHL CoC 4th Ctl, default value: 0x00 */
818 /* MHL CoC 5th Ctl, default value: 0x28 */
823 /* MHL CoC 6th Ctl, default value: 0x0d */
833 /* MHL DataPath 7th Ctl, default value: 0x2a */
835 #define BIT_MHL_DP_CTL6_DP_TAP2_SGN		BIT(5)
842 /* MHL DataPath 8th Ctl, default value: 0x06 */
867 #define BIT_HDCP2X_POLL_CS_HDCP2X_RPT_READY_CLR_OPTION BIT(5)
883 #define BIT_HDCP2X_CTRL_0_HDCP2X_POLINT_OVR	BIT(5)
1019 #define BIT_TPI_SC_TPI_OUTPUT_MODE_1		BIT(5)
1042 #define BIT_TPI_COPP_DATA2_INTR_ENCRYPTION	BIT(5)
1056 #define BIT_TPI_INTR_ST0_TPI_COPP_CHNGE_STAT	BIT(5)
1088 #define BIT_TPI_INFO_FSEL_READ_FLAG		BIT(5)
1125 /* CoC 4th Ctl, default value: 0x40 */
1130 /* CoC 7th Ctl, default value: 0x00 */
1136 /* CoC 8th Ctl, default value: 0x06 */
1140 #define BIT_COC_CTL7_COC_CTRL7_5		BIT(5)
1144 /* CoC 10th Ctl, default value: 0x00 */
1147 /* CoC 11th Ctl, default value: 0x00 */
1150 /* CoC 12th Ctl, default value: 0x00 */
1153 /* CoC 13th Ctl, default value: 0x0f */
1156 /* CoC 14th Ctl, default value: 0x0a */
1161 /* CoC 15th Ctl, default value: 0x0a */
1166 /* CoC 16th Ctl, default value: 0x00 */
1171 /* CoC 18th Ctl, default value: 0x32 */
1199 /* CoC 24th Ctl, default value: 0x00 */
1204 /* CoC 25th Ctl, default value: 0x00 */
1209 /* CoC 26th Ctl, default value: 0x00 */
1214 /* CoC 27th Ctl, default value: 0x00 */
1219 /* DoC 9th Status, default value: 0x00 */
1222 /* DoC 10th Status, default value: 0x00 */
1225 /* DoC 5th CFG, default value: 0x00 */
1232 /* DoC 7th Ctl, default value: 0x00 */
1239 /* DoC 8th Ctl, default value: 0x00 */
1243 #define BIT_DOC_CTL7_DOC_CTRL7_5		BIT(5)
1247 /* DoC 9th Ctl, default value: 0x00 */
1254 /* DoC 10th Ctl, default value: 0x00 */
1257 /* DoC 11th Ctl, default value: 0x00 */
1260 /* DoC 15th Ctl, default value: 0x00 */
1276 /* Interrupt Mask 4th, default value: 0x00 */
1302 #define BIT_MDT_XMIT_CTRL_FIXED_BURST_LEN	BIT(5)
1337 #define BIT_MDT_XMIT_TIMEOUT			BIT(5)
1359 #define BIT_CBUS_MSC_MR_WRITE_BURST		BIT(5)
1413 #define BIT_MSC_COMMAND_START_DEBUG		BIT(5)
1445 #define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_DDC_ON_CBUS BIT(5)
1496 #define BIT_DISC_STAT1_PSM_OVRIDE		BIT(5)
1502 #define BIT_DISC_STAT2_CBUS_SATUS		BIT(5)
1520 #define BIT_CBUS_MHL12_DISCON_INT		BIT(5)