drm/bridge/nwl-dsi.h

12 #define NWL_DSI_CFG_NUM_LANES			0x0
13 #define NWL_DSI_CFG_NONCONTINUOUS_CLK		0x4
14 #define NWL_DSI_CFG_T_PRE			0x8
15 #define NWL_DSI_CFG_T_POST			0xc
16 #define NWL_DSI_CFG_TX_GAP			0x10
17 #define NWL_DSI_CFG_AUTOINSERT_EOTP		0x14
18 #define NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP	0x18
19 #define NWL_DSI_CFG_HTX_TO_COUNT		0x1c
20 #define NWL_DSI_CFG_LRX_H_TO_COUNT		0x20
21 #define NWL_DSI_CFG_BTA_H_TO_COUNT		0x24
22 #define NWL_DSI_CFG_TWAKEUP			0x28
23 #define NWL_DSI_CFG_STATUS_OUT			0x2c
24 #define NWL_DSI_RX_ERROR_STATUS			0x30
27 #define NWL_DSI_PIXEL_PAYLOAD_SIZE		0x200
28 #define NWL_DSI_PIXEL_FIFO_SEND_LEVEL		0x204
29 #define NWL_DSI_INTERFACE_COLOR_CODING		0x208
30 #define NWL_DSI_PIXEL_FORMAT			0x20c
31 #define NWL_DSI_VSYNC_POLARITY			0x210
32 #define NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW	0
33 #define NWL_DSI_VSYNC_POLARITY_ACTIVE_HIGH	BIT(0)
35 #define NWL_DSI_HSYNC_POLARITY			0x214
36 #define NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW	0
37 #define NWL_DSI_HSYNC_POLARITY_ACTIVE_HIGH	BIT(0)
39 #define NWL_DSI_VIDEO_MODE			0x218
40 #define NWL_DSI_HFP				0x21c
41 #define NWL_DSI_HBP				0x220
42 #define NWL_DSI_HSA				0x224
43 #define NWL_DSI_ENABLE_MULT_PKTS		0x228
44 #define NWL_DSI_VBP				0x22c
45 #define NWL_DSI_VFP				0x230
46 #define NWL_DSI_BLLP_MODE			0x234
47 #define NWL_DSI_USE_NULL_PKT_BLLP		0x238
48 #define NWL_DSI_VACTIVE				0x23c
49 #define NWL_DSI_VC				0x240
52 #define NWL_DSI_TX_PAYLOAD			0x280
53 #define NWL_DSI_PKT_CONTROL			0x284
54 #define NWL_DSI_SEND_PACKET			0x288
55 #define NWL_DSI_PKT_STATUS			0x28c
56 #define NWL_DSI_PKT_FIFO_WR_LEVEL		0x290
57 #define NWL_DSI_PKT_FIFO_RD_LEVEL		0x294
58 #define NWL_DSI_RX_PAYLOAD			0x298
59 #define NWL_DSI_RX_PKT_HEADER			0x29c
62 #define NWL_DSI_IRQ_STATUS			0x2a0
63 #define NWL_DSI_SM_NOT_IDLE			BIT(0)
76 #define NWL_DSI_IRQ_STATUS2			0x2a4
77 #define NWL_DSI_SINGLE_BIT_ECC_ERR		BIT(0)
81 #define NWL_DSI_IRQ_MASK			0x2a8
82 #define NWL_DSI_SM_NOT_IDLE_MASK		BIT(0)
95 #define NWL_DSI_IRQ_MASK2			0x2ac
96 #define NWL_DSI_SINGLE_BIT_ECC_ERR_MASK		BIT(0)
102  * [15: 0] - word count
105  * [24]	   - LP or HS select (0 - LP, 1 - HS)
109 #define NWL_DSI_WC(x)		FIELD_PREP(GENMASK(15, 0), (x))
118  * [15: 0] - word count
126 #define NWL_DSI_VM_BURST_MODE_WITH_SYNC_PULSES		0
127 #define NWL_DSI_VM_NON_BURST_MODE_WITH_SYNC_EVENTS	BIT(0)
131 #define NWL_DSI_DPI_16_BIT_565_PACKED	0
139 #define NWL_DSI_PIXEL_FORMAT_16  0
140 #define NWL_DSI_PIXEL_FORMAT_18  BIT(0)
142 #define NWL_DSI_PIXEL_FORMAT_24  (BIT(0) | BIT(1))