363 				 u8 *post_divider)  in anx7625_calculate_m_n()  argument
381 	for (*post_divider = 1;  in anx7625_calculate_m_n()
382 		pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));)  in anx7625_calculate_m_n()
383 		*post_divider += 1;  in anx7625_calculate_m_n()
385 	if (*post_divider > POST_DIVIDER_MAX) {  in anx7625_calculate_m_n()
386 		for (*post_divider = 1;  in anx7625_calculate_m_n()
388 			 (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));)  in anx7625_calculate_m_n()
389 			*post_divider += 1;  in anx7625_calculate_m_n()
391 		if (*post_divider > POST_DIVIDER_MAX) {  in anx7625_calculate_m_n()
393 				  *post_divider);  in anx7625_calculate_m_n()
399 	if (*post_divider == 7) {  in anx7625_calculate_m_n()
401 		*post_divider = 8;  in anx7625_calculate_m_n()
402 	} else if (*post_divider == 11) {  in anx7625_calculate_m_n()
404 		*post_divider = 12;  in anx7625_calculate_m_n()
405 	} else if ((*post_divider == 13) || (*post_divider == 14)) {  in anx7625_calculate_m_n()
407 		*post_divider = 15;  in anx7625_calculate_m_n()
410 	if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) {  in anx7625_calculate_m_n()
412 			  pixelclock * (*post_divider),  in anx7625_calculate_m_n()
418 	*n = XTAL_FRQ / (*post_divider);  in anx7625_calculate_m_n()
426 			       u8 post_divider)  in anx7625_odfc_config()  argument
440 				post_divider << 4);  in anx7625_odfc_config()
485 	u8 post_divider = 0;  in anx7625_dsi_video_timing_config()  local
488 				    &m, &n, &post_divider);  in anx7625_dsi_video_timing_config()
496 			     m, n, post_divider);  in anx7625_dsi_video_timing_config()
568 	ret |= anx7625_odfc_config(ctx, post_divider - 1);  in anx7625_dsi_video_timing_config()