108 u32 ast_mindwm(struct ast_device *ast, u32 r)  in ast_mindwm()  function
154 		data = ast_mindwm(ast, 0x1e6e0070) & 0x40;  in mmctestburst2_ast2150()
164 		data = ast_mindwm(ast, 0x1e6e0070) & 0x40;  in mmctestburst2_ast2150()
170 	data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;  in mmctestburst2_ast2150()
184 		data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
190 	data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
431 		data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;  in mmc_test()
451 		data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;  in mmc_test2()
457 	data = ast_mindwm(ast, 0x1e6e0078);  in mmc_test2()
697 	reg_mcr0c  = ast_mindwm(ast, 0x1E6E000C);  in finetuneDQSI()
698 	reg_mcr18  = ast_mindwm(ast, 0x1E6E0018);  in finetuneDQSI()
830 	ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16));  in cbr_dll2()
841 	trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;  in get_ddr3_info()
1118 		data = ast_mindwm(ast, 0x1E6E001C);  in ddr3_init()
1120 	data = ast_mindwm(ast, 0x1E6E001C);  in ddr3_init()
1123 		data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;  in ddr3_init()
1133 		data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;  in ddr3_init()
1138 		ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);  in ddr3_init()
1140 		data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;  in ddr3_init()
1145 			data = ast_mindwm(ast, 0x1E6E001C);  in ddr3_init()
1148 		data = ast_mindwm(ast, 0x1E6E001C);  in ddr3_init()
1151 	ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff);  in ddr3_init()
1152 	data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;  in ddr3_init()
1189 		data = ast_mindwm(ast, 0x1E6E0070);  in ddr3_init()
1206 	trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;  in get_ddr2_info()
1487 		data = ast_mindwm(ast, 0x1E6E001C);  in ddr2_init()
1489 	data = ast_mindwm(ast, 0x1E6E001C);  in ddr2_init()
1492 		data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;  in ddr2_init()
1502 		data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;  in ddr2_init()
1507 		ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);  in ddr2_init()
1509 		data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;  in ddr2_init()
1514 			data = ast_mindwm(ast, 0x1E6E001C);  in ddr2_init()
1517 		data = ast_mindwm(ast, 0x1E6E001C);  in ddr2_init()
1520 	ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff);  in ddr2_init()
1521 	data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;  in ddr2_init()
1563 		data = ast_mindwm(ast, 0x1E6E0070);  in ddr2_init()
1600 		temp = ast_mindwm(ast, 0x1e6e2070);  in ast_post_chip_2300()
1645 		temp = ast_mindwm(ast, 0x1e6e2040);  in ast_post_chip_2300()
1714 			data = ast_mindwm(ast, 0x1E6E0060) & 0x1;  in ddr_phy_init_2500()
1719 			data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;  in ddr_phy_init_2500()
1744 	reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;  in check_dram_size_2500()
1745 	reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;  in check_dram_size_2500()
1753 	if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {  in check_dram_size_2500()
1757 	} else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {  in check_dram_size_2500()
1761 	} else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {  in check_dram_size_2500()
1775 	reg_04 = ast_mindwm(ast, 0x1E6E0004);  in enable_cache_2500()
1779 		data = ast_mindwm(ast, 0x1E6E0004);  in enable_cache_2500()
1798 	data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;  in set_mpll_2500()
1918 				data = ast_mindwm(ast, 0x1E6E03D0);  in ddr4_init_2500()
1988 		data = ast_mindwm(ast, 0x1E6E2070);  in ast_dram_init_2500()
1995 	ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);  in ast_dram_init_2500()
1998 	data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;  in ast_dram_init_2500()
2071 		if (ast_mindwm(ast, 0x1E6E2070) & 0x00800000) {  in ast_post_chip_2500()
2077 		temp = ast_mindwm(ast, 0x1E6E2070);  in ast_post_chip_2500()
2089 		temp = ast_mindwm(ast, 0x1e6e2040);  in ast_post_chip_2500()