693 	u16 pass[32][2][2];  in finetuneDQSI()  local
707 		pass[dqidly][0][0] = 0xff;  in finetuneDQSI()
708 		pass[dqidly][0][1] = 0x0;  in finetuneDQSI()
709 		pass[dqidly][1][0] = 0xff;  in finetuneDQSI()
710 		pass[dqidly][1][1] = 0x0;  in finetuneDQSI()
727 					if (dlli < pass[dqidly][dqsip][0])  in finetuneDQSI()
728 						pass[dqidly][dqsip][0] = (u16) dlli;  in finetuneDQSI()
729 					if (dlli > pass[dqidly][dqsip][1])  in finetuneDQSI()
730 						pass[dqidly][dqsip][1] = (u16) dlli;  in finetuneDQSI()
734 					pass[dqidly][dqsip][0] = 0xff;  in finetuneDQSI()
735 					pass[dqidly][dqsip][1] = 0x0;  in finetuneDQSI()
747 			if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1])  in finetuneDQSI()
749 			diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0];  in finetuneDQSI()
753 			for (dlli = pass[dqidly][dqsip][0]; dlli > 0  && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++);  in finetuneDQSI()
754 			for (dlli = pass[dqidly][dqsip][1]; dlli < 76 && tag[dqsip][dlli] != 0; dlli++, passcnt[1]++);  in finetuneDQSI()
1708 	u32 data, pass, timecnt;  in ddr_phy_init_2500()  local
1710 	pass = 0;  in ddr_phy_init_2500()
1712 	while (!pass) {  in ddr_phy_init_2500()
1721 				pass = 1;  in ddr_phy_init_2500()
1723 		if (!pass) {  in ddr_phy_init_2500()
1868 	u32 data, data2, pass, retrycnt;  in ddr4_init_2500()  local
1903 	pass = 0;  in ddr4_init_2500()
1905 	for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {  in ddr4_init_2500()
1907 		pass = 0;  in ddr4_init_2500()
1917 				pass++;  in ddr4_init_2500()
1927 			} else if (pass > 0)  in ddr4_init_2500()
1934 	pass = 0;  in ddr4_init_2500()
1936 	for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {  in ddr4_init_2500()
1939 		pass = 0;  in ddr4_init_2500()
1948 				pass++;  in ddr4_init_2500()
1953 			} else if (pass != 0)  in ddr4_init_2500()