Lines Matching +full:0 +full:x0210

15 #define HDLCD_REG_VERSION		0x0000	/* ro */
16 #define HDLCD_REG_INT_RAWSTAT		0x0010	/* rw */
17 #define HDLCD_REG_INT_CLEAR		0x0014	/* wo */
18 #define HDLCD_REG_INT_MASK		0x0018	/* rw */
19 #define HDLCD_REG_INT_STATUS		0x001c	/* ro */
20 #define HDLCD_REG_FB_BASE		0x0100	/* rw */
21 #define HDLCD_REG_FB_LINE_LENGTH	0x0104	/* rw */
22 #define HDLCD_REG_FB_LINE_COUNT		0x0108	/* rw */
23 #define HDLCD_REG_FB_LINE_PITCH		0x010c	/* rw */
24 #define HDLCD_REG_BUS_OPTIONS		0x0110	/* rw */
25 #define HDLCD_REG_V_SYNC		0x0200	/* rw */
26 #define HDLCD_REG_V_BACK_PORCH		0x0204	/* rw */
27 #define HDLCD_REG_V_DATA		0x0208	/* rw */
28 #define HDLCD_REG_V_FRONT_PORCH		0x020c	/* rw */
29 #define HDLCD_REG_H_SYNC		0x0210	/* rw */
30 #define HDLCD_REG_H_BACK_PORCH		0x0214	/* rw */
31 #define HDLCD_REG_H_DATA		0x0218	/* rw */
32 #define HDLCD_REG_H_FRONT_PORCH		0x021c	/* rw */
33 #define HDLCD_REG_POLARITIES		0x0220	/* rw */
34 #define HDLCD_REG_COMMAND		0x0230	/* rw */
35 #define HDLCD_REG_PIXEL_FORMAT		0x0240	/* rw */
36 #define HDLCD_REG_RED_SELECT		0x0244	/* rw */
37 #define HDLCD_REG_GREEN_SELECT		0x0248	/* rw */
38 #define HDLCD_REG_BLUE_SELECT		0x024c	/* rw */
41 #define HDLCD_PRODUCT_ID		0x1CDC0000
42 #define HDLCD_PRODUCT_MASK		0xFFFF0000
43 #define HDLCD_VERSION_MAJOR_MASK	0x0000FF00
44 #define HDLCD_VERSION_MINOR_MASK	0x000000FF
47 #define HDLCD_INTERRUPT_DMA_END		(1 << 0)
56 #define HDLCD_POLARITY_VSYNC		(1 << 0)
63 #define HDLCD_COMMAND_DISABLE		(0 << 0)
64 #define HDLCD_COMMAND_ENABLE		(1 << 0)
67 #define HDLCD_PIXEL_FMT_LITTLE_ENDIAN	(0 << 31)
72 #define HDLCD_BUS_BURST_MASK		0x01f
73 #define HDLCD_BUS_MAX_OUTSTAND		0xf00
74 #define HDLCD_BUS_BURST_NONE		(0 << 0)
75 #define HDLCD_BUS_BURST_1		(1 << 0)