Lines Matching +full:0 +full:x114
11 #define BLK_BLOCK_INFO 0x000
12 #define BLK_PIPELINE_INFO 0x004
13 #define BLK_MAX_LINE_SIZE 0x008
14 #define BLK_VALID_INPUT_ID0 0x020
15 #define BLK_OUTPUT_ID0 0x060
16 #define BLK_INPUT_ID0 0x080
17 #define BLK_IRQ_RAW_STATUS 0x0A0
18 #define BLK_IRQ_CLEAR 0x0A4
19 #define BLK_IRQ_MASK 0x0A8
20 #define BLK_IRQ_STATUS 0x0AC
21 #define BLK_STATUS 0x0B0
22 #define BLK_INFO 0x0C0
23 #define BLK_CONTROL 0x0D0
24 #define BLK_SIZE 0x0D4
25 #define BLK_IN_SIZE 0x0E0
27 #define BLK_P0_PTR_LOW 0x100
28 #define BLK_P0_PTR_HIGH 0x104
29 #define BLK_P0_STRIDE 0x108
30 #define BLK_P1_PTR_LOW 0x110
31 #define BLK_P1_PTR_HIGH 0x114
32 #define BLK_P1_STRIDE 0x118
33 #define BLK_P2_PTR_LOW 0x120
34 #define BLK_P2_PTR_HIGH 0x124
36 #define BLOCK_INFO_N_SUBBLKS(x) ((x) & 0x000F)
37 #define BLOCK_INFO_BLK_ID(x) (((x) & 0x00F0) >> 4)
38 #define BLOCK_INFO_BLK_TYPE(x) (((x) & 0xFF00) >> 8)
39 #define BLOCK_INFO_INPUT_ID(x) ((x) & 0xFFF0)
40 #define BLOCK_INFO_TYPE_ID(x) (((x) & 0x0FF0) >> 4)
42 #define PIPELINE_INFO_N_OUTPUTS(x) ((x) & 0x000F)
43 #define PIPELINE_INFO_N_VALID_INPUTS(x) (((x) & 0x0F00) >> 8)
46 #define BLK_CTRL_EN BIT(0)
48 #define HV_SIZE(h, v) (((h) & 0x1FFF) + (((v) & 0x1FFF) << 16))
49 #define HV_OFFSET(h, v) (((h) & 0xFFF) + (((v) & 0xFFF) << 16))
50 #define HV_CROP(h, v) (((h) & 0xFFF) + (((v) & 0xFFF) << 16))
53 #define AD_CONTROL 0x160
56 #define AD_AEN BIT(0)
63 #define GLB_ARCH_ID 0x000
64 #define GLB_CORE_ID 0x004
65 #define GLB_CORE_INFO 0x008
66 #define GLB_IRQ_STATUS 0x010
68 #define GCU_CONFIG_VALID0 0x0D4
69 #define GCU_CONFIG_VALID1 0x0D8
72 #define GCU_CONTROL_MODE(x) ((x) & 0x7)
76 #define GCU_CONFIGURATION_ID0 0x100
77 #define GCU_CONFIGURATION_ID1 0x104
80 #define GCU_MAX_LINE_SIZE(x) ((x) & 0xFFFF)
82 #define GCU_NUM_RICH_LAYERS(x) ((x) & 0x7)
83 #define GCU_NUM_PIPELINES(x) (((x) >> 3) & 0x7)
84 #define GCU_NUM_SCALERS(x) (((x) >> 6) & 0x7)
85 #define GCU_DISPLAY_SPLIT_EN(x) (((x) >> 16) & 0x1)
86 #define GCU_DISPLAY_TBU_EN(x) (((x) >> 17) & 0x1)
89 #define INACTIVE_MODE 0
97 #define GLB_IRQ_STATUS_GCU BIT(0)
127 #define GCU_IRQ_CVAL0 BIT(0)
133 #define GCU_STATUS_MODE(x) ((x) & 0x7)
140 #define GCU_CONFIG_CVAL BIT(0)
143 #define PERIPH_MAX_LINE_SIZE BIT(0)
148 #define PERIPH_CONFIGURATION_ID 0x1D4
151 #define LPU_TBU_STATUS 0x0B4
152 #define LPU_RAXI_CONTROL 0x0D0
153 #define LPU_WAXI_CONTROL 0x0D4
154 #define LPU_TBU_CONTROL 0x0D8
165 #define RAXI_AOUTSTDCAPB_MASK 0x7F
166 #define RAXI_BOUTSTDCAPB_MASK 0x7F00
168 #define xAXI_BURSTLEN_MASK 0x3F0000
169 #define xAXI_AxQOS_MASK 0xF000000
171 #define WAXI_OUTSTDCAPB_MASK 0x3F
175 #define TBU_DOUTSTDCAPB_MASK 0x3F
185 #define LPU_STATUS_AXIED(x) ((x) & 0xF)
197 #define AXIEID_MASK 0xF
218 #define CBU_INPUT_CTRL_EN BIT(0)
223 #define CU_BG_COLOR 0x0DC
224 #define CU_INPUT0_SIZE 0x0E0
225 #define CU_INPUT0_OFFSET 0x0E4
226 #define CU_INPUT0_CONTROL 0x0E8
227 #define CU_INPUT1_SIZE 0x0F0
228 #define CU_INPUT1_OFFSET 0x0F4
229 #define CU_INPUT1_CONTROL 0x0F8
230 #define CU_INPUT2_SIZE 0x100
231 #define CU_INPUT2_OFFSET 0x104
232 #define CU_INPUT2_CONTROL 0x108
233 #define CU_INPUT3_SIZE 0x110
234 #define CU_INPUT3_OFFSET 0x114
235 #define CU_INPUT3_CONTROL 0x118
236 #define CU_INPUT4_SIZE 0x120
237 #define CU_INPUT4_OFFSET 0x124
238 #define CU_INPUT4_CONTROL 0x128
246 #define CU_CTRL_COPROC BIT(0)
253 #define CU_STATUS_CPE BIT(0)
259 #define CU_INPUT_CTRL_EN BIT(0)
262 #define CU_INPUT_CTRL_ALPHA(x) (((x) & 0xFF) << 8)
273 #define DOU_STATUS_DRIFTTO BIT(0)
280 #define LAYER_INFO 0x0C0
281 #define LAYER_R_CONTROL 0x0D4
282 #define LAYER_FMT 0x0D8
283 #define LAYER_LT_COEFFTAB 0x0DC
284 #define LAYER_PALPHA 0x0E4
286 #define LAYER_YUV_RGB_COEFF0 0x130
288 #define LAYER_AD_H_CROP 0x164
289 #define LAYER_AD_V_CROP 0x168
291 #define LAYER_RGB_RGB_COEFF0 0x170
294 #define L_EN BIT(0)
302 #define L_A_RCACHE(x) (((x) & 0xF) << 28)
303 #define L_ROT_R0 0
309 #define LR_CHI422_BILINEAR 0
311 #define LR_CHI420_JPEG (0 << 2)
314 #define L_ITSEL(x) ((x) & 0xFFF)
315 #define L_FTSEL(x) (((x) & 0xFFF) << 16)
320 #define LAYER_WR_PROG_LINE 0x0D4
321 #define LAYER_WR_FORMAT 0x0D8
325 #define LW_LALPHA(x) (((x) & 0xFF) << 8)
326 #define LW_A_WCACHE(x) (((x) & 0xF) << 28)
329 #define AxCACHE_MASK 0xF0000000
332 #define AxCACHE_B BIT(0) /* Bufferable */
338 #define L_INFO_RF BIT(0)
340 #define L_INFO_ABUF_SIZE(x) (((x) >> 4) & 0x7)
341 #define L_INFO_YUV_MAX_LINESZ(x) (((x) >> 16) & 0xFFFF)
344 #define SC_COEFFTAB 0x0DC
345 #define SC_OUT_SIZE 0x0E4
346 #define SC_H_CROP 0x0E8
347 #define SC_V_CROP 0x0EC
348 #define SC_H_INIT_PH 0x0F0
349 #define SC_H_DELTA_PH 0x0F4
350 #define SC_V_INIT_PH 0x0F8
351 #define SC_V_DELTA_PH 0x0FC
352 #define SC_ENH_LIMITS 0x130
353 #define SC_ENH_COEFF0 0x134
358 #define SC_CTRL_SCL BIT(0)
379 #define SP_OVERLAP_SIZE 0xD8
382 #define BS_INFO 0x0C0
383 #define BS_PROG_LINE 0x0D4
384 #define BS_PREFETCH_LINE 0x0D8
385 #define BS_BG_COLOR 0x0DC
386 #define BS_ACTIVESIZE 0x0E0
387 #define BS_HINTERVALS 0x0E4
388 #define BS_VINTERVALS 0x0E8
389 #define BS_SYNC 0x0EC
390 #define BS_DRIFT_TO 0x100
391 #define BS_FRAME_TO 0x104
392 #define BS_TE_TO 0x108
393 #define BS_T0_INTERVAL 0x110
394 #define BS_T1_INTERVAL 0x114
395 #define BS_T2_INTERVAL 0x118
396 #define BS_CRC0_LOW 0x120
397 #define BS_CRC0_HIGH 0x124
398 #define BS_CRC1_LOW 0x128
399 #define BS_CRC1_HIGH 0x12C
400 #define BS_USER 0x130
403 #define BS_CTRL_EN BIT(0)
417 #define BS_H_INTVALS(hfp, hbp) (((hfp) & 0xFFF) + (((hbp) & 0x3FF) << 16))
418 #define BS_V_INTVALS(vfp, vbp) (((vfp) & 0x3FFF) + (((vbp) & 0xFF) << 16))
421 #define BS_SYNC_HSW(x) ((x) & 0x3FF)
423 #define BS_SYNC_VSW(x) (((x) & 0xFF) << 16)
426 #define BS_NUM_INPUT_IDS 0
427 #define BS_NUM_OUTPUT_IDS 0
430 #define IPS_DEPTH 0x0D8
431 #define IPS_RGB_RGB_COEFF0 0x130
432 #define IPS_RGB_YUV_COEFF0 0x170
434 #define IPS_DEPTH_MARK 0xF
437 #define IPS_CTRL_RGB BIT(0)
454 #define FT_COEFF0 0x80
455 #define GLB_IT_COEFF 0x80
458 #define GLB_SC_COEFF_ADDR 0x0080
459 #define GLB_SC_COEFF_DATA 0x0084
460 #define GLB_LT_COEFF_DATA 0x0080
469 #define SC_COEFF_DATA(x, y) (((y) & 0xFFFF) | (((x) & 0xFFFF) << 16))
472 D71_BLK_TYPE_GCU = 0x00,
473 D71_BLK_TYPE_LPU = 0x01,
474 D71_BLK_TYPE_CU = 0x02,
475 D71_BLK_TYPE_DOU = 0x03,
476 D71_BLK_TYPE_AEU = 0x04,
477 D71_BLK_TYPE_GLB_LT_COEFF = 0x05,
478 D71_BLK_TYPE_GLB_SCL_COEFF = 0x06, /* SH/SV scaler coeff */
479 D71_BLK_TYPE_GLB_SC_COEFF = 0x07,
480 D71_BLK_TYPE_PERIPH = 0x08,
481 D71_BLK_TYPE_LPU_TRUSTED = 0x09,
482 D71_BLK_TYPE_AEU_TRUSTED = 0x0A,
483 D71_BLK_TYPE_LPU_LAYER = 0x10,
484 D71_BLK_TYPE_LPU_WB_LAYER = 0x11,
485 D71_BLK_TYPE_CU_SPLITTER = 0x20,
486 D71_BLK_TYPE_CU_SCALER = 0x21,
487 D71_BLK_TYPE_CU_MERGER = 0x22,
488 D71_BLK_TYPE_DOU_IPS = 0x30,
489 D71_BLK_TYPE_DOU_BS = 0x31,
490 D71_BLK_TYPE_DOU_FT_COEFF = 0x32,
491 D71_BLK_TYPE_AEU_DS = 0x40,
492 D71_BLK_TYPE_AEU_AES = 0x41,
493 D71_BLK_TYPE_RESERVED = 0xFF
509 #define D71_BLOCK_OFFSET_PERIPH 0xFE00
510 #define D71_BLOCK_SIZE 0x0200
524 #define D71_PALPHA_DEF_MAP 0xFFAA5500
525 #define D71_LAYER_CONTROL_DEFAULT 0x30000000
526 #define D71_WB_LAYER_CONTROL_DEFAULT 0x3000FF00
527 #define D71_BS_CONTROL_DEFAULT 0x00000002