181 	struct d71_dev *d71 = mdev->chip_data;  in d71_irq_handler()  local
184 	gcu_status = malidp_read32(d71->gcu_addr, GLB_IRQ_STATUS);  in d71_irq_handler()
187 		raw_status = malidp_read32(d71->gcu_addr, BLK_IRQ_RAW_STATUS);  in d71_irq_handler()
193 			status = malidp_read32(d71->gcu_addr, BLK_STATUS);  in d71_irq_handler()
196 				malidp_write32_mask(d71->gcu_addr, BLK_STATUS,  in d71_irq_handler()
201 		malidp_write32(d71->gcu_addr, BLK_IRQ_CLEAR, raw_status);  in d71_irq_handler()
205 		evts->pipes[0] |= get_pipeline_event(d71->pipes[0], gcu_status);  in d71_irq_handler()
208 		evts->pipes[1] |= get_pipeline_event(d71->pipes[1], gcu_status);  in d71_irq_handler()
221 	struct d71_dev *d71 = mdev->chip_data;  in d71_enable_irq()  local
225 	malidp_write32_mask(d71->gcu_addr, BLK_IRQ_MASK,  in d71_enable_irq()
227 	for (i = 0; i < d71->num_pipelines; i++) {  in d71_enable_irq()
228 		pipe = d71->pipes[i];  in d71_enable_irq()
241 	struct d71_dev *d71 = mdev->chip_data;  in d71_disable_irq()  local
245 	malidp_write32_mask(d71->gcu_addr, BLK_IRQ_MASK, ENABLED_GCU_IRQS, 0);  in d71_disable_irq()
246 	for (i = 0; i < d71->num_pipelines; i++) {  in d71_disable_irq()
247 		pipe = d71->pipes[i];  in d71_disable_irq()
260 	struct d71_dev *d71 = mdev->chip_data;  in d71_on_off_vblank()  local
261 	struct d71_pipeline *pipe = d71->pipes[master_pipe];  in d71_on_off_vblank()
286 	struct d71_dev *d71 = mdev->chip_data;  in d71_change_opmode()  local
290 	malidp_write32_mask(d71->gcu_addr, BLK_CONTROL, 0x7, opmode);  in d71_change_opmode()
292 	ret = dp_wait_cond(((malidp_read32(d71->gcu_addr, BLK_CONTROL) & 0x7) == opmode),  in d71_change_opmode()
301 	struct d71_dev *d71 = mdev->chip_data;  in d71_flush()  local
305 	malidp_write32(d71->gcu_addr, reg_offset, GCU_CONFIG_CVAL);  in d71_flush()
308 static int d71_reset(struct d71_dev *d71)  in d71_reset()  argument
310 	u32 __iomem *gcu = d71->gcu_addr;  in d71_reset()
340 	struct d71_dev *d71 = mdev->chip_data;  in d71_cleanup()  local
342 	if (!d71)  in d71_cleanup()
345 	devm_kfree(mdev->dev, d71);  in d71_cleanup()
351 	struct d71_dev *d71;  in d71_enum_resources()  local
358 	d71 = devm_kzalloc(mdev->dev, sizeof(*d71), GFP_KERNEL);  in d71_enum_resources()
359 	if (!d71)  in d71_enum_resources()
362 	mdev->chip_data = d71;  in d71_enum_resources()
363 	d71->mdev = mdev;  in d71_enum_resources()
364 	d71->gcu_addr = mdev->reg_base;  in d71_enum_resources()
365 	d71->periph_addr = mdev->reg_base + (D71_BLOCK_OFFSET_PERIPH >> 2);  in d71_enum_resources()
367 	err = d71_reset(d71);  in d71_enum_resources()
374 	value = malidp_read32(d71->gcu_addr, GLB_CORE_INFO);  in d71_enum_resources()
375 	d71->num_blocks = value & 0xFF;  in d71_enum_resources()
376 	d71->num_pipelines = (value >> 8) & 0x7;  in d71_enum_resources()
378 	if (d71->num_pipelines > D71_MAX_PIPELINE) {  in d71_enum_resources()
380 			  D71_MAX_PIPELINE, d71->num_pipelines);  in d71_enum_resources()
388 	value = malidp_read32(d71->periph_addr, BLK_BLOCK_INFO);  in d71_enum_resources()
390 		d71->periph_addr = NULL;  in d71_enum_resources()
392 	if (d71->periph_addr) {  in d71_enum_resources()
394 		value = malidp_read32(d71->periph_addr, PERIPH_CONFIGURATION_ID);  in d71_enum_resources()
396 		d71->max_line_size	= value & PERIPH_MAX_LINE_SIZE ? 4096 : 2048;  in d71_enum_resources()
397 		d71->max_vsize		= 4096;  in d71_enum_resources()
398 		d71->num_rich_layers	= value & PERIPH_NUM_RICH_LAYERS ? 2 : 1;  in d71_enum_resources()
399 		d71->supports_dual_link	= !!(value & PERIPH_SPLIT_EN);  in d71_enum_resources()
400 		d71->integrates_tbu	= !!(value & PERIPH_TBU_EN);  in d71_enum_resources()
402 		value = malidp_read32(d71->gcu_addr, GCU_CONFIGURATION_ID0);  in d71_enum_resources()
403 		d71->max_line_size	= GCU_MAX_LINE_SIZE(value);  in d71_enum_resources()
404 		d71->max_vsize		= GCU_MAX_NUM_LINES(value);  in d71_enum_resources()
406 		value = malidp_read32(d71->gcu_addr, GCU_CONFIGURATION_ID1);  in d71_enum_resources()
407 		d71->num_rich_layers	= GCU_NUM_RICH_LAYERS(value);  in d71_enum_resources()
408 		d71->supports_dual_link	= GCU_DISPLAY_SPLIT_EN(value);  in d71_enum_resources()
409 		d71->integrates_tbu	= GCU_DISPLAY_TBU_EN(value);  in d71_enum_resources()
412 	for (i = 0; i < d71->num_pipelines; i++) {  in d71_enum_resources()
435 		d71->pipes[i] = to_d71_pipeline(pipe);  in d71_enum_resources()
444 	while (i < d71->num_blocks) {  in d71_enum_resources()
449 			err = d71_probe_block(d71, &blk, blk_base);  in d71_enum_resources()
459 		  i, d71->num_blocks);  in d71_enum_resources()
558 	struct d71_dev *d71 = mdev->chip_data;  in d71_connect_iommu()  local
559 	u32 __iomem *reg = d71->gcu_addr;  in d71_connect_iommu()
560 	u32 check_bits = (d71->num_pipelines == 2) ?  in d71_connect_iommu()
564 	if (!d71->integrates_tbu)  in d71_connect_iommu()
577 	for (i = 0; i < d71->num_pipelines; i++)  in d71_connect_iommu()
578 		malidp_write32_mask(d71->pipes[i]->lpu_addr, LPU_TBU_CONTROL,  in d71_connect_iommu()
585 	struct d71_dev *d71 = mdev->chip_data;  in d71_disconnect_iommu()  local
586 	u32 __iomem *reg = d71->gcu_addr;  in d71_disconnect_iommu()
587 	u32 check_bits = (d71->num_pipelines == 2) ?  in d71_disconnect_iommu()