Lines Matching +full:0 +full:x255
55 #define MC_CG_ARB_FREQ_F1 0x0b
60 #define PPSMC_MSG_ApplyAvfsCksOffVoltage ((uint16_t) 0x415)
61 #define PPSMC_MSG_EnableModeSwitchRLCNotification ((uint16_t) 0x305)
67 { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
68 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
69 …{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5…
97 return 0; in vegam_smu_init()
102 int result = 0; in vegam_start_smu_in_protection_mode()
105 /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */ in vegam_start_smu_in_protection_mode()
112 if (result != 0) in vegam_start_smu_in_protection_mode()
116 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0); in vegam_start_smu_in_protection_mode()
119 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); in vegam_start_smu_in_protection_mode()
123 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in vegam_start_smu_in_protection_mode()
129 /* Call Test SMU message with 0x20000 offset to trigger SMU start */ in vegam_start_smu_in_protection_mode()
135 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0); in vegam_start_smu_in_protection_mode()
141 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0); in vegam_start_smu_in_protection_mode()
147 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in vegam_start_smu_in_protection_mode()
157 int result = 0; in vegam_start_smu_in_non_protection_mode()
160 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0); in vegam_start_smu_in_non_protection_mode()
165 ixFIRMWARE_FLAGS, 0); in vegam_start_smu_in_non_protection_mode()
172 if (result != 0) in vegam_start_smu_in_non_protection_mode()
175 /* Set smc instruct start point at 0x0 */ in vegam_start_smu_in_non_protection_mode()
179 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); in vegam_start_smu_in_non_protection_mode()
182 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in vegam_start_smu_in_non_protection_mode()
194 int result = 0; in vegam_start_smu()
205 if (smu_data->protected_mode == 0) in vegam_start_smu()
210 if (result != 0) in vegam_start_smu()
211 PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result); in vegam_start_smu()
218 0x40000); in vegam_start_smu()
238 if (0 == result) in vegam_process_firmware_header()
241 error |= (0 != result); in vegam_process_firmware_header()
253 error |= (0 != result); in vegam_process_firmware_header()
271 error |= (0 != result); in vegam_process_firmware_header()
281 error |= (0 != result); in vegam_process_firmware_header()
291 error |= (0 != result); in vegam_process_firmware_header()
293 return error ? -1 : 0; in vegam_process_firmware_header()
327 return 0; in vegam_get_mac_definition()
337 smu_data->smc_state_table.UvdBootLevel = 0; in vegam_update_uvd_smc_table()
338 if (table_info->mm_dep_table->count > 0) in vegam_update_uvd_smc_table()
347 mm_boot_level_value &= 0x00FFFFFF; in vegam_update_uvd_smc_table()
360 return 0; in vegam_update_uvd_smc_table()
375 smu_data->smc_state_table.VceBootLevel = 0; in vegam_update_vce_smc_table()
383 mm_boot_level_value &= 0xFF00FFFF; in vegam_update_vce_smc_table()
393 return 0; in vegam_update_vce_smc_table()
408 for (i = 0; i < max_entry; i++) in vegam_update_bif_smc_table()
410 return 0; in vegam_update_bif_smc_table()
428 return 0; in vegam_update_smc_table()
444 smu_data->power_tune_defaults = &vegam_power_tune_data_set_array[0]; in vegam_initialize_power_tune_defaults()
458 for (level = 0; level < count; level++) { in vegam_populate_smc_mvdd_table()
472 return 0; in vegam_populate_smc_mvdd_table()
486 for (level = 0; level < count; ++level) { in vegam_populate_smc_vddci_table()
497 return 0; in vegam_populate_smc_vddci_table()
515 for (count = 0; count < lookup_table->count; count++) { in vegam_populate_cac_table()
526 return 0; in vegam_populate_cac_table()
536 return 0; in vegam_populate_smc_voltage_tables()
546 state->CcPwrDynRm = 0; in vegam_populate_ulv_level()
547 state->CcPwrDynRm1 = 0; in vegam_populate_ulv_level()
553 state->VddcPhase = data->vddc_phase_shed_control ^ 0x3; in vegam_populate_ulv_level()
559 return 0; in vegam_populate_ulv_level()
579 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in vegam_populate_smc_link_level()
585 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff); in vegam_populate_smc_link_level()
597 return 0; in vegam_populate_smc_link_level()
608 *voltage = *mvdd = 0; in vegam_get_dependency_volt_by_clk()
611 if (dep_table->count == 0) in vegam_get_dependency_volt_by_clk()
614 for (i = 0; i < dep_table->count; i++) { in vegam_get_dependency_volt_by_clk()
640 return 0; in vegam_get_dependency_volt_by_clk()
666 return 0; in vegam_get_dependency_volt_by_clk()
675 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } }; in vegam_get_sclk_range_table()
679 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) { in vegam_get_sclk_range_table()
680 for (i = 0; i < NUM_SCLK_RANGE; i++) { in vegam_get_sclk_range_table()
700 for (i = 0; i < NUM_SCLK_RANGE; i++) { in vegam_get_sclk_range_table()
734 if (result == 0) { in vegam_calculate_sclk_params()
739 sclk_setting->Sclk_slew_rate = 0x400; in vegam_calculate_sclk_params()
741 sclk_setting->Pcc_down_slew_rate = 0xffff; in vegam_calculate_sclk_params()
751 for (i = 0; i < NUM_SCLK_RANGE; i++) { in vegam_calculate_sclk_params()
763 temp <<= 0x10; in vegam_calculate_sclk_params()
765 sclk_setting->Fcw_frac = temp & 0xffff; in vegam_calculate_sclk_params()
774 sclk_setting->SSc_En = 0; in vegam_calculate_sclk_params()
782 temp <<= 0x10; in vegam_calculate_sclk_params()
784 sclk_setting->Fcw1_frac = temp & 0xffff; in vegam_calculate_sclk_params()
787 return 0; in vegam_calculate_sclk_params()
799 return 0); in vegam_get_sleep_divider_id_from_clock()
803 if (temp >= min || i == 0) in vegam_get_sleep_divider_id_from_clock()
818 SMU_SclkSetting curr_sclk_setting = { 0 }; in vegam_populate_single_graphic_level()
827 PP_ASSERT_WITH_CODE((0 == result), in vegam_populate_single_graphic_level()
833 level->CcPwrDynRm = 0; in vegam_populate_single_graphic_level()
834 level->CcPwrDynRm1 = 0; in vegam_populate_single_graphic_level()
835 level->EnabledForActivity = 0; in vegam_populate_single_graphic_level()
837 level->VoltageDownHyst = 0; in vegam_populate_single_graphic_level()
838 level->PowerThrottle = 0; in vegam_populate_single_graphic_level()
861 return 0; in vegam_populate_single_graphic_level()
873 int result = 0; in vegam_populate_all_graphic_levels()
881 uint8_t hightest_pcie_level_enabled = 0, in vegam_populate_all_graphic_levels()
882 lowest_pcie_level_enabled = 0, in vegam_populate_all_graphic_levels()
883 mid_pcie_level_enabled = 0, in vegam_populate_all_graphic_levels()
884 count = 0; in vegam_populate_all_graphic_levels()
888 for (i = 0; i < dpm_table->sclk_table.count; i++) { in vegam_populate_all_graphic_levels()
900 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */ in vegam_populate_all_graphic_levels()
902 levels[i].DeepSleepDivId = 0; in vegam_populate_all_graphic_levels()
906 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0; in vegam_populate_all_graphic_levels()
913 for (i = 0; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
915 (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask >> i) & 0x1; in vegam_populate_all_graphic_levels()
922 for (i = 0; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
928 (1 << (hightest_pcie_level_enabled + 1))) != 0)) in vegam_populate_all_graphic_levels()
933 (1 << lowest_pcie_level_enabled)) == 0)) in vegam_populate_all_graphic_levels()
938 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0)) in vegam_populate_all_graphic_levels()
951 levels[0].pcieDpmLevel = lowest_pcie_level_enabled; in vegam_populate_all_graphic_levels()
978 return 0; in vegam_calculate_mclk_params()
987 int result = 0; in vegam_populate_single_memory_level()
1006 mem_level->EnabledForActivity = 0; in vegam_populate_single_memory_level()
1007 mem_level->VoltageDownHyst = 0; in vegam_populate_single_memory_level()
1019 STUTTER_ENABLE) & 0x1)) in vegam_populate_single_memory_level()
1049 for (i = 0; i < dpm_table->mclk_table.count; i++) { in vegam_populate_all_memory_levels()
1050 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in vegam_populate_all_memory_levels()
1071 for (i = 0; i < dpm_table->mclk_table.count; i++) in vegam_populate_all_memory_levels()
1073 (hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask >> i) & 0x1; in vegam_populate_all_memory_levels()
1091 uint32_t i = 0; in vegam_populate_mvdd_value()
1095 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) { in vegam_populate_mvdd_value()
1107 return 0; in vegam_populate_mvdd_value()
1113 int result = 0; in vegam_populate_smc_acpi_level()
1141 table->ACPILevel.DeepSleepDivId = 0; in vegam_populate_smc_acpi_level()
1142 table->ACPILevel.CcPwrDynRm = 0; in vegam_populate_smc_acpi_level()
1143 table->ACPILevel.CcPwrDynRm1 = 0; in vegam_populate_smc_acpi_level()
1168 PP_ASSERT_WITH_CODE((0 == result), in vegam_populate_smc_acpi_level()
1173 if (!vegam_populate_mvdd_value(hwmgr, 0, &vol_level)) in vegam_populate_smc_acpi_level()
1176 table->MemoryACPILevel.MinMvdd = 0; in vegam_populate_smc_acpi_level()
1180 table->MemoryACPILevel.EnabledForThrottle = 0; in vegam_populate_smc_acpi_level()
1181 table->MemoryACPILevel.EnabledForActivity = 0; in vegam_populate_smc_acpi_level()
1182 table->MemoryACPILevel.UpHyst = 0; in vegam_populate_smc_acpi_level()
1184 table->MemoryACPILevel.VoltageDownHyst = 0; in vegam_populate_smc_acpi_level()
1208 table->VceBootLevel = 0; in vegam_populate_smc_vce_level()
1210 for (count = 0; count < table->VceLevelCount; count++) { in vegam_populate_smc_vce_level()
1212 table->VceLevel[count].MinVoltage = 0; in vegam_populate_smc_vce_level()
1232 PP_ASSERT_WITH_CODE((0 == result), in vegam_populate_smc_vce_level()
1258 PP_ASSERT_WITH_CODE(result == 0, in vegam_populate_memory_timing_parameters()
1274 return 0; in vegam_populate_memory_timing_parameters()
1283 int result = 0; in vegam_program_memory_timing_parameters()
1285 memset(&arb_regs, 0, sizeof(SMU75_Discrete_MCArbDramTimingTable)); in vegam_program_memory_timing_parameters()
1287 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { in vegam_program_memory_timing_parameters()
1288 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { in vegam_program_memory_timing_parameters()
1321 table->UvdBootLevel = 0; in vegam_populate_smc_uvd_level()
1323 for (count = 0; count < table->UvdLevelCount; count++) { in vegam_populate_smc_uvd_level()
1324 table->UvdLevel[count].MinVoltage = 0; in vegam_populate_smc_uvd_level()
1344 PP_ASSERT_WITH_CODE((0 == result), in vegam_populate_smc_uvd_level()
1351 PP_ASSERT_WITH_CODE((0 == result), in vegam_populate_smc_uvd_level()
1367 int result = 0; in vegam_populate_smc_boot_level()
1370 table->GraphicsBootLevel = 0; in vegam_populate_smc_boot_level()
1371 table->MemoryBootLevel = 0; in vegam_populate_smc_boot_level()
1398 return 0; in vegam_populate_smc_boot_level()
1411 for (level = 0; level < count; level++) { in vegam_populate_smc_initial_state()
1420 for (level = 0; level < count; level++) { in vegam_populate_smc_initial_state()
1428 return 0; in vegam_populate_smc_initial_state()
1472 for (i = 0; i < SMU75_DTE_ITERATIONS; i++) { in vegam_populate_bapm_parameters_in_dpm_table()
1473 for (j = 0; j < SMU75_DTE_SOURCES; j++) { in vegam_populate_bapm_parameters_in_dpm_table()
1474 for (k = 0; k < SMU75_DTE_SINKS; k++) { in vegam_populate_bapm_parameters_in_dpm_table()
1483 return 0; in vegam_populate_bapm_parameters_in_dpm_table()
1492 uint8_t i, stretch_amount, volt_offset = 0; in vegam_populate_clock_stretcher_data_table()
1509 for (i = 0; i < sclk_table->count; i++) { in vegam_populate_clock_stretcher_data_table()
1527 (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? in vegam_populate_clock_stretcher_data_table()
1541 value &= 0xFFFFFFFE; in vegam_populate_clock_stretcher_data_table()
1544 return 0; in vegam_populate_clock_stretcher_data_table()
1553 efuse &= 0x00000001; in vegam_is_hw_avfs_present()
1567 int result = 0; in vegam_populate_avfs_parameters()
1568 struct pp_atom_ctrl__avfs_parameters avfs_params = {0}; in vegam_populate_avfs_parameters()
1569 AVFS_meanNsigma_t AVFS_meanNsigma = { {0} }; in vegam_populate_avfs_parameters()
1570 AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} }; in vegam_populate_avfs_parameters()
1579 return 0; in vegam_populate_avfs_parameters()
1583 if (0 == result) { in vegam_populate_avfs_parameters()
1584 table->BTCGB_VDROOP_TABLE[0].a0 = in vegam_populate_avfs_parameters()
1586 table->BTCGB_VDROOP_TABLE[0].a1 = in vegam_populate_avfs_parameters()
1588 table->BTCGB_VDROOP_TABLE[0].a2 = in vegam_populate_avfs_parameters()
1596 table->AVFSGB_FUSE_TABLE[0].m1 = in vegam_populate_avfs_parameters()
1598 table->AVFSGB_FUSE_TABLE[0].m2 = in vegam_populate_avfs_parameters()
1600 table->AVFSGB_FUSE_TABLE[0].b = in vegam_populate_avfs_parameters()
1602 table->AVFSGB_FUSE_TABLE[0].m1_shift = 24; in vegam_populate_avfs_parameters()
1603 table->AVFSGB_FUSE_TABLE[0].m2_shift = 12; in vegam_populate_avfs_parameters()
1613 AVFS_meanNsigma.Aconstant[0] = in vegam_populate_avfs_parameters()
1628 for (i = 0; i < sclk_table->count; i++) { in vegam_populate_avfs_parameters()
1707 0x1); in vegam_populate_vr_config()
1721 0x1); in vegam_populate_vr_config()
1727 return 0; in vegam_populate_vr_config()
1738 smu_data->power_tune_table.SviLoadLineOffsetVddC = 0; in vegam_populate_svi_load_line()
1740 return 0; in vegam_populate_svi_load_line()
1758 return 0; in vegam_populate_tdc_limit()
1777 (uint8_t)((temp >> 16) & 0xff); in vegam_populate_dw8()
1779 (uint8_t)((temp >> 8) & 0xff); in vegam_populate_dw8()
1780 smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff); in vegam_populate_dw8()
1782 return 0; in vegam_populate_dw8()
1791 for (i = 0; i < 16; i++) in vegam_populate_temperature_scaler()
1792 smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0; in vegam_populate_temperature_scaler()
1794 return 0; in vegam_populate_temperature_scaler()
1803 || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity) in vegam_populate_fuzzy_fan()
1809 return 0; in vegam_populate_fuzzy_fan()
1818 for (i = 0; i < 16; i++) in vegam_populate_gnb_lpml()
1819 smu_data->power_tune_table.GnbLPML[i] = 0; in vegam_populate_gnb_lpml()
1821 return 0; in vegam_populate_gnb_lpml()
1841 return 0; in vegam_populate_bapm_vddc_base_leakage_sidd()
1874 if (0 != vegam_populate_temperature_scaler(hwmgr)) in vegam_populate_pm_fuses()
1902 return 0; in vegam_populate_pm_fuses()
1914 return 0; in vegam_enable_reconfig_cus()
1940 table->SystemFlags = 0; in vegam_init_smc_table()
2016 table->CurrSclkPllRange = 0xff; in vegam_init_smc_table()
2030 table->VoltageResponseTime = 0; in vegam_init_smc_table()
2031 table->PhaseResponseTime = 0; in vegam_init_smc_table()
2040 table->VRConfig = 0; in vegam_init_smc_table()
2047 table->SclkStepSize = 0x4000; in vegam_init_smc_table()
2086 (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) & in vegam_init_smc_table()
2087 (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0; in vegam_init_smc_table()
2103 for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) { in vegam_init_smc_table()
2110 if (i == 0) in vegam_init_smc_table()
2118 for (i = 0; i < SMU75_MAX_ENTRIES_SMIO; i++) in vegam_init_smc_table()
2150 return 0; in vegam_init_smc_table()
2196 return 0; in vegam_get_offsetof()
2209 return 0; in vegam_program_mem_timing_parameters()
2217 int result = 0; in vegam_update_sclk_threshold()
2218 uint32_t low_sclk_interrupt_threshold = 0; in vegam_update_sclk_threshold()
2222 && (data->low_sclk_interrupt_threshold != 0)) { in vegam_update_sclk_threshold()
2237 PP_ASSERT_WITH_CODE((result == 0), in vegam_update_sclk_threshold()
2241 PP_ASSERT_WITH_CODE((result == 0), in vegam_update_sclk_threshold()
2254 return 0; in vegam_thermal_avfs_enable()
2274 return 0; in vegam_thermal_setup_fan_table()