Lines Matching +full:0 +full:x25a
60 #define MC_CG_ARB_FREQ_F1 0x0b
68 {1, 0xF, 0xFD, 0x19,
69 5, 45, 0, 0xB0000,
70 {0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8,
71 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
72 {0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203,
73 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4}
79 {600, 1050, 3, 0},
87 { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
91 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] */
93 {0, 1, 3, 2, 4, 5},
94 {0, 2, 4, 5, 6, 5}
111 ixSMU_STATUS, 0); in tonga_start_in_protection_mode()
115 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); in tonga_start_in_protection_mode()
119 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in tonga_start_in_protection_mode()
127 ixFIRMWARE_FLAGS, 0); in tonga_start_in_protection_mode()
133 * Call Test SMU message with 0x20000 offset to trigger SMU start in tonga_start_in_protection_mode()
139 SMU_STATUS, SMU_DONE, 0); in tonga_start_in_protection_mode()
152 return 0; in tonga_start_in_protection_mode()
157 int result = 0; in tonga_start_in_non_protection_mode()
161 RCU_UC_EVENTS, boot_seq_done, 0); in tonga_start_in_non_protection_mode()
165 ixFIRMWARE_FLAGS, 0); in tonga_start_in_non_protection_mode()
173 if (result != 0) in tonga_start_in_non_protection_mode()
176 /* Set smc instruct start point at 0x0 */ in tonga_start_in_non_protection_mode()
181 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); in tonga_start_in_non_protection_mode()
185 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in tonga_start_in_non_protection_mode()
202 if (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_smu()
220 &(priv->smu7_data.soft_regs_start), 0x40000); in tonga_start_smu()
242 return 0; in tonga_smu_init()
250 uint32_t i = 0; in tonga_get_dependency_volt_by_clk()
256 if (allowed_clock_voltage_table->count == 0) in tonga_get_dependency_volt_by_clk()
259 for (i = 0; i < allowed_clock_voltage_table->count; i++) { in tonga_get_dependency_volt_by_clk()
282 return 0; in tonga_get_dependency_volt_by_clk()
299 return 0; in tonga_get_dependency_volt_by_clk()
310 for (count = 0; count < table->VddcLevelCount; count++) { in tonga_populate_smc_vddc_table()
316 return 0; in tonga_populate_smc_vddc_table()
327 for (count = 0; count < data->vddgfx_voltage_table.count; count++) { in tonga_populate_smc_vdd_gfx_table()
333 return 0; in tonga_populate_smc_vdd_gfx_table()
343 for (count = 0; count < table->VddciLevelCount; count++) { in tonga_populate_smc_vdd_ci_table()
363 return 0; in tonga_populate_smc_vdd_ci_table()
374 for (count = 0; count < table->MvddLevelCount; count++) { in tonga_populate_smc_mvdd_table()
388 return 0; in tonga_populate_smc_mvdd_table()
395 uint8_t index = 0; in tonga_populate_cac_tables()
410 for (count = 0; count < vddc_level_count; count++) { in tonga_populate_cac_tables()
424 for (count = 0; count < vddgfx_level_count; count++) { in tonga_populate_cac_tables()
431 for (count = 0; count < vddc_level_count; count++) { in tonga_populate_cac_tables()
443 return 0; in tonga_populate_cac_tables()
476 return 0; in tonga_populate_smc_voltage_tables()
485 state->CcPwrDynRm = 0; in tonga_populate_ulv_level()
486 state->CcPwrDynRm1 = 0; in tonga_populate_ulv_level()
498 return 0; in tonga_populate_ulv_level()
515 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in tonga_populate_smc_link_level()
523 (uint8_t)(data->pcie_spc_cap & 0xff); in tonga_populate_smc_link_level()
535 return 0; in tonga_populate_smc_link_level()
556 PP_ASSERT_WITH_CODE(result == 0, in tonga_calculate_sclk_params()
565 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in tonga_calculate_sclk_params()
586 if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) { in tonga_calculate_sclk_params()
613 return 0; in tonga_calculate_sclk_params()
647 graphic_level->CcPwrDynRm = 0; in tonga_populate_single_graphic_level()
648 graphic_level->CcPwrDynRm1 = 0; in tonga_populate_single_graphic_level()
650 graphic_level->EnabledForActivity = 0; in tonga_populate_single_graphic_level()
655 graphic_level->VoltageDownHyst = 0; in tonga_populate_single_graphic_level()
656 graphic_level->PowerThrottle = 0; in tonga_populate_single_graphic_level()
703 uint8_t highest_pcie_level_enabled = 0; in tonga_populate_all_graphic_levels()
704 uint8_t lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0; in tonga_populate_all_graphic_levels()
705 uint8_t count = 0; in tonga_populate_all_graphic_levels()
706 int result = 0; in tonga_populate_all_graphic_levels()
708 memset(levels, 0x00, level_array_size); in tonga_populate_all_graphic_levels()
710 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
714 if (result != 0) in tonga_populate_all_graphic_levels()
717 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */ in tonga_populate_all_graphic_levels()
719 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in tonga_populate_all_graphic_levels()
722 /* Only enable level 0 for now. */ in tonga_populate_all_graphic_levels()
723 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in tonga_populate_all_graphic_levels()
740 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
745 if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask) in tonga_populate_all_graphic_levels()
746 pr_err("Pcie Dpm Enablemask is 0 !"); in tonga_populate_all_graphic_levels()
750 (1<<(highest_pcie_level_enabled+1))) != 0)) { in tonga_populate_all_graphic_levels()
756 (1<<lowest_pcie_level_enabled)) == 0)) { in tonga_populate_all_graphic_levels()
762 (1<<(lowest_pcie_level_enabled+1+count))) == 0)) { in tonga_populate_all_graphic_levels()
774 smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled; in tonga_populate_all_graphic_levels()
859 CLKS = NS - 1 = ISS_STEP_NUM[11:0] in tonga_calculate_mclk_params()
861 CLKV = 65536 * NV = ISS_STEP_SIZE[25:0] in tonga_calculate_mclk_params()
879 if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) { in tonga_calculate_mclk_params()
917 return 0; in tonga_calculate_mclk_params()
927 mc_para_index = 0x00; in tonga_get_mclk_frequency_ratio()
929 mc_para_index = 0x0f; in tonga_get_mclk_frequency_ratio()
934 mc_para_index = 0x00; in tonga_get_mclk_frequency_ratio()
936 mc_para_index = 0x0f; in tonga_get_mclk_frequency_ratio()
949 mc_para_index = 0; in tonga_get_ddr3_mclk_frequency_ratio()
951 mc_para_index = 0x0f; in tonga_get_ddr3_mclk_frequency_ratio()
973 int result = 0; in tonga_populate_single_memory_level()
975 uint32_t mvdd = 0; in tonga_populate_single_memory_level()
1000 memory_level->EnabledForActivity = 0; in tonga_populate_single_memory_level()
1003 memory_level->VoltageDownHyst = 0; in tonga_populate_single_memory_level()
1007 memory_level->StutterEnable = 0; in tonga_populate_single_memory_level()
1008 memory_level->StrobeEnable = 0; in tonga_populate_single_memory_level()
1009 memory_level->EdcReadEnable = 0; in tonga_populate_single_memory_level()
1010 memory_level->EdcWriteEnable = 0; in tonga_populate_single_memory_level()
1011 memory_level->RttEnable = 0; in tonga_populate_single_memory_level()
1019 if ((mclk_stutter_mode_threshold != 0) && in tonga_populate_single_memory_level()
1022 && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1) in tonga_populate_single_memory_level()
1024 && (data->display_timing.num_existing_displays != 0)) in tonga_populate_single_memory_level()
1028 memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) && in tonga_populate_single_memory_level()
1036 if ((mclk_edc_enable_threshold != 0) && in tonga_populate_single_memory_level()
1041 if ((mclk_edc_wr_enable_threshold != 0) && in tonga_populate_single_memory_level()
1048 ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) { in tonga_populate_single_memory_level()
1049 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; in tonga_populate_single_memory_level()
1051 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0; in tonga_populate_single_memory_level()
1060 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; in tonga_populate_single_memory_level()
1105 memset(levels, 0x00, level_array_size); in tonga_populate_all_memory_levels()
1107 for (i = 0; i < dpm_table->mclk_table.count; i++) { in tonga_populate_all_memory_levels()
1108 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in tonga_populate_all_memory_levels()
1119 /* Only enable level 0 for now.*/ in tonga_populate_all_memory_levels()
1120 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in tonga_populate_all_memory_levels()
1127 smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; in tonga_populate_all_memory_levels()
1128 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel); in tonga_populate_all_memory_levels()
1149 uint32_t i = 0; in tonga_populate_mvdd_value()
1153 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) { in tonga_populate_mvdd_value()
1169 return 0; in tonga_populate_mvdd_value()
1176 int result = 0; in tonga_populate_smc_acpi_level()
1192 smu_data->smc_state_table.GraphicsLevel[0].MinVoltage; in tonga_populate_smc_acpi_level()
1201 PP_ASSERT_WITH_CODE(result == 0, in tonga_populate_smc_acpi_level()
1208 table->ACPILevel.DeepSleepDivId = 0; in tonga_populate_smc_acpi_level()
1211 SPLL_PWRON, 0); in tonga_populate_smc_acpi_level()
1223 table->ACPILevel.CcPwrDynRm = 0; in tonga_populate_smc_acpi_level()
1224 table->ACPILevel.CcPwrDynRm1 = 0; in tonga_populate_smc_acpi_level()
1242 smu_data->smc_state_table.MemoryLevel[0].MinVoltage; in tonga_populate_smc_acpi_level()
1246 if (0 == tonga_populate_mvdd_value(hwmgr, 0, &voltage_level)) in tonga_populate_smc_acpi_level()
1250 table->MemoryACPILevel.MinMvdd = 0; in tonga_populate_smc_acpi_level()
1254 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1); in tonga_populate_smc_acpi_level()
1256 MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1); in tonga_populate_smc_acpi_level()
1260 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0); in tonga_populate_smc_acpi_level()
1262 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0); in tonga_populate_smc_acpi_level()
1266 DLL_CNTL, MRDCK0_BYPASS, 0); in tonga_populate_smc_acpi_level()
1268 DLL_CNTL, MRDCK1_BYPASS, 0); in tonga_populate_smc_acpi_level()
1289 table->MemoryACPILevel.EnabledForThrottle = 0; in tonga_populate_smc_acpi_level()
1290 table->MemoryACPILevel.EnabledForActivity = 0; in tonga_populate_smc_acpi_level()
1291 table->MemoryACPILevel.UpHyst = 0; in tonga_populate_smc_acpi_level()
1293 table->MemoryACPILevel.VoltageDownHyst = 0; in tonga_populate_smc_acpi_level()
1298 table->MemoryACPILevel.StutterEnable = 0; in tonga_populate_smc_acpi_level()
1299 table->MemoryACPILevel.StrobeEnable = 0; in tonga_populate_smc_acpi_level()
1300 table->MemoryACPILevel.EdcReadEnable = 0; in tonga_populate_smc_acpi_level()
1301 table->MemoryACPILevel.EdcWriteEnable = 0; in tonga_populate_smc_acpi_level()
1302 table->MemoryACPILevel.RttEnable = 0; in tonga_populate_smc_acpi_level()
1310 int result = 0; in tonga_populate_smc_uvd_level()
1321 table->UvdBootLevel = 0; in tonga_populate_smc_uvd_level()
1323 for (count = 0; count < table->UvdLevelCount; count++) { in tonga_populate_smc_uvd_level()
1332 mm_table->entries[count].vddgfx) : 0; in tonga_populate_smc_uvd_level()
1370 int result = 0; in tonga_populate_smc_vce_level()
1381 table->VceBootLevel = 0; in tonga_populate_smc_vce_level()
1383 for (count = 0; count < table->VceLevelCount; count++) { in tonga_populate_smc_vce_level()
1392 mm_table->entries[count].vddgfx) : 0; in tonga_populate_smc_vce_level()
1416 int result = 0; in tonga_populate_smc_acp_level()
1426 table->AcpBootLevel = 0; in tonga_populate_smc_acp_level()
1428 for (count = 0; count < table->AcpLevelCount; count++) { in tonga_populate_smc_acp_level()
1437 mm_table->entries[count].vddgfx) : 0; in tonga_populate_smc_acp_level()
1472 PP_ASSERT_WITH_CODE(result == 0, in tonga_populate_memory_timing_parameters()
1483 return 0; in tonga_populate_memory_timing_parameters()
1491 int result = 0; in tonga_program_memory_timing_parameters()
1495 memset(&arb_regs, 0x00, sizeof(SMU72_Discrete_MCArbDramTimingTable)); in tonga_program_memory_timing_parameters()
1497 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in tonga_program_memory_timing_parameters()
1498 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in tonga_program_memory_timing_parameters()
1525 int result = 0; in tonga_populate_smc_boot_level()
1529 table->GraphicsBootLevel = 0; in tonga_populate_smc_boot_level()
1530 table->MemoryBootLevel = 0; in tonga_populate_smc_boot_level()
1537 if (result != 0) { in tonga_populate_smc_boot_level()
1538 smu_data->smc_state_table.GraphicsBootLevel = 0; in tonga_populate_smc_boot_level()
1541 "Using Graphics DPM level 0 !"); in tonga_populate_smc_boot_level()
1542 result = 0; in tonga_populate_smc_boot_level()
1549 if (result != 0) { in tonga_populate_smc_boot_level()
1550 smu_data->smc_state_table.MemoryBootLevel = 0; in tonga_populate_smc_boot_level()
1553 "Using Memory DPM level 0 !"); in tonga_populate_smc_boot_level()
1554 result = 0; in tonga_populate_smc_boot_level()
1581 volt_offset = 0; in tonga_populate_clock_stretcher_data_table()
1601 efuse &= 0xFF000000; in tonga_populate_clock_stretcher_data_table()
1603 efuse2 &= 0xF; in tonga_populate_clock_stretcher_data_table()
1611 type = 0; in tonga_populate_clock_stretcher_data_table()
1620 for (i = 0; i < sclk_table->count; i++) { in tonga_populate_clock_stretcher_data_table()
1645 STRETCH_ENABLE, 0x0); in tonga_populate_clock_stretcher_data_table()
1647 masterReset, 0x1); in tonga_populate_clock_stretcher_data_table()
1649 staticEnable, 0x1); in tonga_populate_clock_stretcher_data_table()
1651 masterReset, 0x0); in tonga_populate_clock_stretcher_data_table()
1655 stretch_amount2 = 0; in tonga_populate_clock_stretcher_data_table()
1668 value &= 0xFFC2FF87; in tonga_populate_clock_stretcher_data_table()
1669 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq = in tonga_populate_clock_stretcher_data_table()
1670 tonga_clock_stretcher_lookup_table[stretch_amount2][0]; in tonga_populate_clock_stretcher_data_table()
1671 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq = in tonga_populate_clock_stretcher_data_table()
1676 if (tonga_clock_stretcher_lookup_table[stretch_amount2][0] < in tonga_populate_clock_stretcher_data_table()
1690 CKS_LOOKUPTableEntry[0].minFreq); in tonga_populate_clock_stretcher_data_table()
1692 CKS_LOOKUPTableEntry[0].maxFreq); in tonga_populate_clock_stretcher_data_table()
1693 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting = in tonga_populate_clock_stretcher_data_table()
1694 tonga_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F; in tonga_populate_clock_stretcher_data_table()
1695 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |= in tonga_populate_clock_stretcher_data_table()
1702 for (i = 0; i < 4; i++) { in tonga_populate_clock_stretcher_data_table()
1715 for (j = 0; j < smu_data->smc_state_table.GraphicsDpmLevelCount; j++) { in tonga_populate_clock_stretcher_data_table()
1716 cks_setting = 0; in tonga_populate_clock_stretcher_data_table()
1724 if (clock_freq >= tonga_clock_stretcher_ddt_table[type][i][0] * 100) { in tonga_populate_clock_stretcher_data_table()
1725 cks_setting |= 0x2; in tonga_populate_clock_stretcher_data_table()
1727 cks_setting |= 0x1; in tonga_populate_clock_stretcher_data_table()
1739 value &= 0xFFFFFFFE; in tonga_populate_clock_stretcher_data_table()
1743 return 0; in tonga_populate_clock_stretcher_data_table()
1794 return 0; in tonga_populate_vr_config()
1815 if (result != 0) in tonga_init_arb_table_index()
1818 tmp &= 0x00FFFFFF; in tonga_init_arb_table_index()
1857 for (i = 0; i < SMU72_DTE_ITERATIONS; i++) { in tonga_populate_bapm_parameters_in_dpm_table()
1858 for (j = 0; j < SMU72_DTE_SOURCES; j++) { in tonga_populate_bapm_parameters_in_dpm_table()
1859 for (k = 0; k < SMU72_DTE_SINKS; k++) { in tonga_populate_bapm_parameters_in_dpm_table()
1870 return 0; in tonga_populate_bapm_parameters_in_dpm_table()
1882 smu_data->power_tune_table.SviLoadLineOffsetVddC = 0; in tonga_populate_svi_load_line()
1884 return 0; in tonga_populate_svi_load_line()
1906 return 0; in tonga_populate_tdc_limit()
1927 return 0; in tonga_populate_dw8()
1937 for (i = 0; i < 16; i++) in tonga_populate_temperature_scaler()
1938 smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0; in tonga_populate_temperature_scaler()
1940 return 0; in tonga_populate_temperature_scaler()
1949 (hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity == 0)) in tonga_populate_fuzzy_fan()
1957 return 0; in tonga_populate_fuzzy_fan()
1967 for (i = 0; i < 16; i++) in tonga_populate_gnb_lpml()
1968 smu_data->power_tune_table.GnbLPML[i] = 0; in tonga_populate_gnb_lpml()
1970 return 0; in tonga_populate_gnb_lpml()
1991 return 0; in tonga_populate_bapm_vddc_base_leakage_sidd()
2027 if (tonga_populate_temperature_scaler(hwmgr) != 0) in tonga_populate_pm_fuses()
2060 return 0; in tonga_populate_pm_fuses()
2070 for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) { in tonga_populate_mc_reg_address()
2087 return 0; in tonga_populate_mc_reg_address()
2098 for (i = 0, j = 0; j < num_entries; j++) { in tonga_convert_mc_registers()
2113 uint32_t i = 0; in tonga_convert_mc_reg_table_entry_to_smc()
2115 for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) { in tonga_convert_mc_reg_table_entry_to_smc()
2122 if ((i == smu_data->mc_reg_table.num_entries) && (i > 0)) in tonga_convert_mc_reg_table_entry_to_smc()
2129 return 0; in tonga_convert_mc_reg_table_entry_to_smc()
2135 int result = 0; in tonga_convert_mc_reg_table_to_smc()
2140 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { in tonga_convert_mc_reg_table_to_smc()
2147 if (0 != res) in tonga_convert_mc_reg_table_to_smc()
2161 if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in tonga_update_and_upload_mc_reg_table()
2162 return 0; in tonga_update_and_upload_mc_reg_table()
2165 memset(&smu_data->mc_regs, 0, sizeof(SMU72_Discrete_MCRegisters)); in tonga_update_and_upload_mc_reg_table()
2169 if (result != 0) in tonga_update_and_upload_mc_reg_table()
2174 (uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]); in tonga_update_and_upload_mc_reg_table()
2178 (uint8_t *)&smu_data->mc_regs.data[0], in tonga_update_and_upload_mc_reg_table()
2189 memset(&smu_data->mc_regs, 0x00, sizeof(SMU72_Discrete_MCRegisters)); in tonga_populate_initial_mc_reg_table()
2217 smu_data->power_tune_defaults = &tonga_power_tune_data_set_array[0]; in tonga_initialize_power_tune_defaults()
2234 memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table)); in tonga_init_smc_table()
2255 if (i == 1 || i == 0) in tonga_init_smc_table()
2256 table->SystemFlags |= 0x40; in tonga_init_smc_table()
2265 ixCG_ULV_PARAMETER, 0x40035); in tonga_init_smc_table()
2333 table->VoltageResponseTime = 0; in tonga_init_smc_table()
2334 table->PhaseResponseTime = 0; in tonga_init_smc_table()
2359 table->SclkStepSize = 0x4000; in tonga_init_smc_table()
2386 if (0) { in tonga_init_smc_table()
2401 (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) & in tonga_init_smc_table()
2402 (1 << gpio_pin_assignment.uc_gpio_pin_bit_shift))) ? 1 : 0; in tonga_init_smc_table()
2422 for (i = 0; i < SMU72_MAX_ENTRIES_SMIO; i++) in tonga_init_smc_table()
2457 return 0; in tonga_init_smc_table()
2474 return 0; in tonga_thermal_setup_fan_table()
2479 return 0; in tonga_thermal_setup_fan_table()
2482 if (0 == smu_data->smu7_data.fan_table_start) { in tonga_thermal_setup_fan_table()
2485 return 0; in tonga_thermal_setup_fan_table()
2492 if (0 == duty100) { in tonga_thermal_setup_fan_table()
2495 return 0; in tonga_thermal_setup_fan_table()
2560 return 0; in tonga_program_mem_timing_parameters()
2569 int result = 0; in tonga_update_sclk_threshold()
2570 uint32_t low_sclk_interrupt_threshold = 0; in tonga_update_sclk_threshold()
2574 && (data->low_sclk_interrupt_threshold != 0)) { in tonga_update_sclk_threshold()
2597 PP_ASSERT_WITH_CODE((result == 0), in tonga_update_sclk_threshold()
2647 return 0; in tonga_get_offsetof()
2672 return 0; in tonga_get_mac_definition()
2683 smu_data->smc_state_table.UvdBootLevel = 0; in tonga_update_uvd_smc_table()
2684 if (table_info->mm_dep_table->count > 0) in tonga_update_uvd_smc_table()
2693 mm_boot_level_value &= 0x00FFFFFF; in tonga_update_uvd_smc_table()
2707 return 0; in tonga_update_uvd_smc_table()
2728 mm_boot_level_value &= 0xFF00FFFF; in tonga_update_vce_smc_table()
2739 return 0; in tonga_update_vce_smc_table()
2754 return 0; in tonga_update_smc_table()
2774 error |= (result != 0); in tonga_process_firmware_header()
2786 error |= (result != 0); in tonga_process_firmware_header()
2805 error |= (result != 0); in tonga_process_firmware_header()
2815 error |= (result != 0); in tonga_process_firmware_header()
2825 error |= (result != 0); in tonga_process_firmware_header()
2827 return error ? 1 : 0; in tonga_process_firmware_header()
2834 return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16)); in tonga_get_memory_modile_index()
2935 for (i = 0; i < table->last; i++) { in tonga_set_s0_mc_reg_index()
2942 return 0; in tonga_set_s0_mc_reg_index()
2955 for (i = 0; i < table->last; i++) in tonga_copy_vbios_smc_reg_table()
2960 for (i = 0; i < table->num_entries; i++) { in tonga_copy_vbios_smc_reg_table()
2963 for (j = 0; j < table->last; j++) { in tonga_copy_vbios_smc_reg_table()
2971 return 0; in tonga_copy_vbios_smc_reg_table()
2981 for (i = 0, j = table->last; i < table->last; i++) { in tonga_set_mc_special_registers()
2992 for (k = 0; k < table->num_entries; k++) { in tonga_set_mc_special_registers()
2994 ((temp_reg & 0xffff0000)) | in tonga_set_mc_special_registers()
2995 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); in tonga_set_mc_special_registers()
3004 for (k = 0; k < table->num_entries; k++) { in tonga_set_mc_special_registers()
3006 (temp_reg & 0xffff0000) | in tonga_set_mc_special_registers()
3007 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in tonga_set_mc_special_registers()
3010 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; in tonga_set_mc_special_registers()
3019 for (k = 0; k < table->num_entries; k++) in tonga_set_mc_special_registers()
3021 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; in tonga_set_mc_special_registers()
3031 for (k = 0; k < table->num_entries; k++) { in tonga_set_mc_special_registers()
3033 (temp_reg & 0xffff0000) | in tonga_set_mc_special_registers()
3034 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in tonga_set_mc_special_registers()
3047 return 0; in tonga_set_mc_special_registers()
3054 for (i = 0; i < table->last; i++) { in tonga_set_valid_flag()
3064 return 0; in tonga_set_valid_flag()
3174 for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) { in tonga_update_dpm_settings()
3181 offset = clk_activity_offset & ~0x3; in tonga_update_dpm_settings()
3195 offset = up_hyst_offset & ~0x3; in tonga_update_dpm_settings()
3209 for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) { in tonga_update_dpm_settings()
3216 offset = clk_activity_offset & ~0x3; in tonga_update_dpm_settings()
3230 offset = up_hyst_offset & ~0x3; in tonga_update_dpm_settings()
3240 return 0; in tonga_update_dpm_settings()