38 static int smu7_set_smc_sram_address(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t limit)  in smu7_set_smc_sram_address()  argument
43 	cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, smc_addr);  in smu7_set_smc_sram_address()
44 …PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND_A…  in smu7_set_smc_sram_address()
49 int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, uint32_t *dest, ui…  in smu7_copy_bytes_from_smc()  argument
63 		smu7_read_smc_sram_dword(hwmgr, addr, &data, limit);  in smu7_copy_bytes_from_smc()
73 		smu7_read_smc_sram_dword(hwmgr, addr, &data, limit);  in smu7_copy_bytes_from_smc()
85 int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,  in smu7_copy_bytes_to_smc()  argument
103 		result = smu7_set_smc_sram_address(hwmgr, addr, limit);  in smu7_copy_bytes_to_smc()
108 		cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data);  in smu7_copy_bytes_to_smc()
119 		result = smu7_set_smc_sram_address(hwmgr, addr, limit);  in smu7_copy_bytes_to_smc()
125 		original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11);  in smu7_copy_bytes_to_smc()
139 		result = smu7_set_smc_sram_address(hwmgr, addr, limit);  in smu7_copy_bytes_to_smc()
144 		cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data);  in smu7_copy_bytes_to_smc()
151 int smu7_program_jump_on_start(struct pp_hwmgr *hwmgr)  in smu7_program_jump_on_start()  argument
155 	smu7_copy_bytes_to_smc(hwmgr, 0x0, data, 4, sizeof(data)+1);  in smu7_program_jump_on_start()
160 bool smu7_is_smc_ram_running(struct pp_hwmgr *hwmgr)  in smu7_is_smc_ram_running()  argument
162 …return ((0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_…  in smu7_is_smc_ram_running()
163 	&& (0x20100 <= cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMC_PC_C)));  in smu7_is_smc_ram_running()
166 int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)  in smu7_send_msg_to_smc()  argument
168 	struct amdgpu_device *adev = hwmgr->adev;  in smu7_send_msg_to_smc()
171 	PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);  in smu7_send_msg_to_smc()
173 	ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);  in smu7_send_msg_to_smc()
181 	cgs_write_register(hwmgr->device, mmSMC_RESP_0, 0);  in smu7_send_msg_to_smc()
182 	cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);  in smu7_send_msg_to_smc()
184 	PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);  in smu7_send_msg_to_smc()
186 	ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);  in smu7_send_msg_to_smc()
197 int smu7_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter)  in smu7_send_msg_to_smc_with_parameter()  argument
199 	PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);  in smu7_send_msg_to_smc_with_parameter()
201 	cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);  in smu7_send_msg_to_smc_with_parameter()
203 	return smu7_send_msg_to_smc(hwmgr, msg);  in smu7_send_msg_to_smc_with_parameter()
206 uint32_t smu7_get_argument(struct pp_hwmgr *hwmgr)  in smu7_get_argument()  argument
208 	return cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);  in smu7_get_argument()
211 int smu7_send_msg_to_smc_offset(struct pp_hwmgr *hwmgr)  in smu7_send_msg_to_smc_offset()  argument
213 	return smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_Test, 0x20000, NULL);  in smu7_send_msg_to_smc_offset()
265 int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t *value, uint32_t l…  in smu7_read_smc_sram_dword()  argument
269 	result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit);  in smu7_read_smc_sram_dword()
271 	*value = result ? 0 : cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11);  in smu7_read_smc_sram_dword()
276 int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t value, uint32_t l…  in smu7_write_smc_sram_dword()  argument
280 	result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit);  in smu7_write_smc_sram_dword()
285 	cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, value);  in smu7_write_smc_sram_dword()
290 static int smu7_populate_single_firmware_entry(struct pp_hwmgr *hwmgr,  in smu7_populate_single_firmware_entry()  argument
297 	result = cgs_get_firmware_info(hwmgr->device,  in smu7_populate_single_firmware_entry()
310 		if (!hwmgr->not_vf)  in smu7_populate_single_firmware_entry()
325 int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)  in smu7_request_smu_load_fw()  argument
327 	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);  in smu7_request_smu_load_fw()
331 	amdgpu_ucode_init_bo(hwmgr->adev);  in smu7_request_smu_load_fw()
334 		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,  in smu7_request_smu_load_fw()
335 					smu_data->soft_regs_start + smum_get_offsetof(hwmgr,  in smu7_request_smu_load_fw()
339 	if (hwmgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */  in smu7_request_smu_load_fw()
340 		if (hwmgr->not_vf) {  in smu7_request_smu_load_fw()
341 			smum_send_msg_to_smc_with_parameter(hwmgr,  in smu7_request_smu_load_fw()
345 			smum_send_msg_to_smc_with_parameter(hwmgr,  in smu7_request_smu_load_fw()
379 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,  in smu7_request_smu_load_fw()
382 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,  in smu7_request_smu_load_fw()
385 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,  in smu7_request_smu_load_fw()
388 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,  in smu7_request_smu_load_fw()
391 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,  in smu7_request_smu_load_fw()
394 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,  in smu7_request_smu_load_fw()
397 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,  in smu7_request_smu_load_fw()
400 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,  in smu7_request_smu_load_fw()
403 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,  in smu7_request_smu_load_fw()
406 		if (!hwmgr->not_vf)  in smu7_request_smu_load_fw()
407 			PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,  in smu7_request_smu_load_fw()
413 	smum_send_msg_to_smc_with_parameter(hwmgr,  in smu7_request_smu_load_fw()
417 	smum_send_msg_to_smc_with_parameter(hwmgr,  in smu7_request_smu_load_fw()
422 	smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_LoadUcodes, fw_to_load, NULL);  in smu7_request_smu_load_fw()
424 	r = smu7_check_fw_load_finish(hwmgr, fw_to_load);  in smu7_request_smu_load_fw()
437 int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type)  in smu7_check_fw_load_finish()  argument
439 	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);  in smu7_check_fw_load_finish()
442 	ret = phm_wait_on_indirect_register(hwmgr, mmSMC_IND_INDEX_11,  in smu7_check_fw_load_finish()
443 					smu_data->soft_regs_start + smum_get_offsetof(hwmgr,  in smu7_check_fw_load_finish()
449 int smu7_reload_firmware(struct pp_hwmgr *hwmgr)  in smu7_reload_firmware()  argument
451 	return hwmgr->smumgr_funcs->start_smu(hwmgr);  in smu7_reload_firmware()
454 static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, uint32_t length, uint32_t *src, ui…  in smu7_upload_smc_firmware_data()  argument
460 	cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, 0x20000);  in smu7_upload_smc_firmware_data()
461 	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1);  in smu7_upload_smc_firmware_data()
464 		cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, *src++);  in smu7_upload_smc_firmware_data()
466 	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);  in smu7_upload_smc_firmware_data()
474 int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr)  in smu7_upload_smu_firmware_image()  argument
477 	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);  in smu7_upload_smu_firmware_image()
482 		cgs_get_firmware_info(hwmgr->device,  in smu7_upload_smu_firmware_image()
485 		cgs_get_firmware_info(hwmgr->device,  in smu7_upload_smu_firmware_image()
488 	hwmgr->is_kicker = info.is_kicker;  in smu7_upload_smu_firmware_image()
489 	hwmgr->smu_version = info.version;  in smu7_upload_smu_firmware_image()
490 …result = smu7_upload_smc_firmware_data(hwmgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZ…  in smu7_upload_smu_firmware_image()
495 static void execute_pwr_table(struct pp_hwmgr *hwmgr, const PWR_Command_Table *pvirus, int size)  in execute_pwr_table()  argument
504 			cgs_write_register(hwmgr->device, reg, data);  in execute_pwr_table()
511 static void execute_pwr_dfy_table(struct pp_hwmgr *hwmgr, const PWR_DFY_Section *section)  in execute_pwr_dfy_table()  argument
515 	cgs_write_register(hwmgr->device, mmCP_DFY_CNTL, section->dfy_cntl);  in execute_pwr_dfy_table()
516 	cgs_write_register(hwmgr->device, mmCP_DFY_ADDR_HI, section->dfy_addr_hi);  in execute_pwr_dfy_table()
517 	cgs_write_register(hwmgr->device, mmCP_DFY_ADDR_LO, section->dfy_addr_lo);  in execute_pwr_dfy_table()
519 		cgs_write_register(hwmgr->device, mmCP_DFY_DATA_0, section->dfy_data[i]);  in execute_pwr_dfy_table()
522 int smu7_setup_pwr_virus(struct pp_hwmgr *hwmgr)  in smu7_setup_pwr_virus()  argument
524 	execute_pwr_table(hwmgr, pwr_virus_table_pre, ARRAY_SIZE(pwr_virus_table_pre));  in smu7_setup_pwr_virus()
525 	execute_pwr_dfy_table(hwmgr, &pwr_virus_section1);  in smu7_setup_pwr_virus()
526 	execute_pwr_dfy_table(hwmgr, &pwr_virus_section2);  in smu7_setup_pwr_virus()
527 	execute_pwr_dfy_table(hwmgr, &pwr_virus_section3);  in smu7_setup_pwr_virus()
528 	execute_pwr_dfy_table(hwmgr, &pwr_virus_section4);  in smu7_setup_pwr_virus()
529 	execute_pwr_dfy_table(hwmgr, &pwr_virus_section5);  in smu7_setup_pwr_virus()
530 	execute_pwr_dfy_table(hwmgr, &pwr_virus_section6);  in smu7_setup_pwr_virus()
531 	execute_pwr_table(hwmgr, pwr_virus_table_post, ARRAY_SIZE(pwr_virus_table_post));  in smu7_setup_pwr_virus()
536 int smu7_init(struct pp_hwmgr *hwmgr)  in smu7_init()  argument
541 	smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);  in smu7_init()
547 	r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,  in smu7_init()
558 	if (!hwmgr->not_vf)  in smu7_init()
562 	r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,  in smu7_init()
577 	if (smum_is_hw_avfs_present(hwmgr) &&  in smu7_init()
578 	    (hwmgr->feature_mask & PP_AVFS_MASK))  in smu7_init()
579 		hwmgr->avfs_supported = true;  in smu7_init()
585 int smu7_smu_fini(struct pp_hwmgr *hwmgr)  in smu7_smu_fini()  argument
587 	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);  in smu7_smu_fini()
593 	if (hwmgr->not_vf)  in smu7_smu_fini()
601 	kfree(hwmgr->smu_backend);  in smu7_smu_fini()
602 	hwmgr->smu_backend = NULL;  in smu7_smu_fini()