Lines Matching +full:0 +full:x30750000
55 #define POLARIS10_SMC_SIZE 0x20000
58 #define MC_CG_ARB_FREQ_F1 0x0b
63 { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
64 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
65 …{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5…
83 …0x100ea446, 0x00, 0x03, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x30750000…
84 …0x400ea446, 0x01, 0x04, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x409c0000…
85 …0x740ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x50c30000…
86 …0xa40ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x60ea0000…
87 …0xd80ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x70110100…
88 …0x3c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x80380100…
89 …0x6c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x905f0100…
90 …0xa00fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0xa0860100…
94 0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};
98 int result = 0; in polaris10_perform_btc()
101 if (0 != smu_data->avfs_btc_param) { in polaris10_perform_btc()
102 …if (0 != smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs_btc_param, in polaris10_perform_btc()
111 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000); in polaris10_perform_btc()
113 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff); in polaris10_perform_btc()
114 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0); in polaris10_perform_btc()
131 PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr, in polaris10_setup_graphics_level_structure()
133 &dpm_table_start, 0x40000), in polaris10_setup_graphics_level_structure()
138 vr_config = 0x01000500; /* Real value:0x50001 */ in polaris10_setup_graphics_level_structure()
142 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address, in polaris10_setup_graphics_level_structure()
143 (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000), in polaris10_setup_graphics_level_structure()
149 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address, in polaris10_setup_graphics_level_structure()
151 graphics_level_size, 0x40000), in polaris10_setup_graphics_level_structure()
157 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address, in polaris10_setup_graphics_level_structure()
158 (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000), in polaris10_setup_graphics_level_structure()
166 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address, in polaris10_setup_graphics_level_structure()
167 (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000), in polaris10_setup_graphics_level_structure()
171 return 0; in polaris10_setup_graphics_level_structure()
180 return 0; in polaris10_avfs_event_mgr()
182 PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr), in polaris10_avfs_event_mgr()
188 PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr), in polaris10_avfs_event_mgr()
193 PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr), in polaris10_avfs_event_mgr()
197 return 0; in polaris10_avfs_event_mgr()
202 int result = 0; in polaris10_start_smu_in_protection_mode()
205 /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */ in polaris10_start_smu_in_protection_mode()
212 if (result != 0) in polaris10_start_smu_in_protection_mode()
216 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0); in polaris10_start_smu_in_protection_mode()
219 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); in polaris10_start_smu_in_protection_mode()
223 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in polaris10_start_smu_in_protection_mode()
229 /* Call Test SMU message with 0x20000 offset to trigger SMU start */ in polaris10_start_smu_in_protection_mode()
235 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0); in polaris10_start_smu_in_protection_mode()
241 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0); in polaris10_start_smu_in_protection_mode()
247 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in polaris10_start_smu_in_protection_mode()
257 int result = 0; in polaris10_start_smu_in_non_protection_mode()
260 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0); in polaris10_start_smu_in_non_protection_mode()
265 ixFIRMWARE_FLAGS, 0); in polaris10_start_smu_in_non_protection_mode()
272 if (result != 0) in polaris10_start_smu_in_non_protection_mode()
275 /* Set smc instruct start point at 0x0 */ in polaris10_start_smu_in_non_protection_mode()
279 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); in polaris10_start_smu_in_non_protection_mode()
282 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in polaris10_start_smu_in_non_protection_mode()
294 int result = 0; in polaris10_start_smu()
303 if (smu_data->protected_mode == 0) in polaris10_start_smu()
308 if (result != 0) in polaris10_start_smu()
309 PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result); in polaris10_start_smu()
316 &(smu_data->smu7_data.soft_regs_start), 0x40000); in polaris10_start_smu()
328 efuse &= 0x00000001; in polaris10_is_hw_avfs_present()
350 return 0; in polaris10_smu_init()
361 *voltage = *mvdd = 0; in polaris10_get_dependency_volt_by_clk()
364 if (dep_table->count == 0) in polaris10_get_dependency_volt_by_clk()
367 for (i = 0; i < dep_table->count; i++) { in polaris10_get_dependency_volt_by_clk()
393 return 0; in polaris10_get_dependency_volt_by_clk()
417 return 0; in polaris10_get_dependency_volt_by_clk()
461 for (i = 0; i < SMU74_DTE_ITERATIONS; i++) { in polaris10_populate_bapm_parameters_in_dpm_table()
462 for (j = 0; j < SMU74_DTE_SOURCES; j++) { in polaris10_populate_bapm_parameters_in_dpm_table()
463 for (k = 0; k < SMU74_DTE_SINKS; k++) { in polaris10_populate_bapm_parameters_in_dpm_table()
472 return 0; in polaris10_populate_bapm_parameters_in_dpm_table()
498 smu_data->power_tune_table.SviLoadLineOffsetVddC = 0; in polaris10_populate_svi_load_line()
500 return 0; in polaris10_populate_svi_load_line()
518 return 0; in polaris10_populate_tdc_limit()
537 (uint8_t)((temp >> 16) & 0xff); in polaris10_populate_dw8()
539 (uint8_t)((temp >> 8) & 0xff); in polaris10_populate_dw8()
540 smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff); in polaris10_populate_dw8()
542 return 0; in polaris10_populate_dw8()
551 for (i = 0; i < 16; i++) in polaris10_populate_temperature_scaler()
552 smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0; in polaris10_populate_temperature_scaler()
554 return 0; in polaris10_populate_temperature_scaler()
563 || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity) in polaris10_populate_fuzzy_fan()
569 return 0; in polaris10_populate_fuzzy_fan()
578 for (i = 0; i < 16; i++) in polaris10_populate_gnb_lpml()
579 smu_data->power_tune_table.GnbLPML[i] = 0; in polaris10_populate_gnb_lpml()
581 return 0; in polaris10_populate_gnb_lpml()
601 return 0; in polaris10_populate_bapm_vddc_base_leakage_sidd()
634 if (0 != polaris10_populate_temperature_scaler(hwmgr)) in polaris10_populate_pm_fuses()
661 return 0; in polaris10_populate_pm_fuses()
674 for (level = 0; level < count; level++) { in polaris10_populate_smc_mvdd_table()
688 return 0; in polaris10_populate_smc_mvdd_table()
702 for (level = 0; level < count; ++level) { in polaris10_populate_smc_vddc_table()
713 return 0; in polaris10_populate_smc_vddc_table()
727 for (level = 0; level < count; ++level) { in polaris10_populate_smc_vddci_table()
738 return 0; in polaris10_populate_smc_vddci_table()
756 for (count = 0; count < lookup_table->count; count++) { in polaris10_populate_cac_table()
764 return 0; in polaris10_populate_cac_table()
775 return 0; in polaris10_populate_smc_voltage_tables()
786 state->CcPwrDynRm = 0; in polaris10_populate_ulv_level()
787 state->CcPwrDynRm1 = 0; in polaris10_populate_ulv_level()
798 state->VddcPhase = data->vddc_phase_shed_control ^ 0x3; in polaris10_populate_ulv_level()
800 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1; in polaris10_populate_ulv_level()
806 return 0; in polaris10_populate_ulv_level()
825 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in polaris10_populate_smc_link_level()
831 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff); in polaris10_populate_smc_link_level()
843 return 0; in polaris10_populate_smc_link_level()
853 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } }; in polaris10_get_sclk_range_table()
857 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) { in polaris10_get_sclk_range_table()
858 for (i = 0; i < NUM_SCLK_RANGE; i++) { in polaris10_get_sclk_range_table()
873 for (i = 0; i < NUM_SCLK_RANGE; i++) { in polaris10_get_sclk_range_table()
905 if (result == 0) { in polaris10_calculate_sclk_params()
910 sclk_setting->Sclk_slew_rate = 0x400; in polaris10_calculate_sclk_params()
912 sclk_setting->Pcc_down_slew_rate = 0xffff; in polaris10_calculate_sclk_params()
922 for (i = 0; i < NUM_SCLK_RANGE; i++) { in polaris10_calculate_sclk_params()
932 temp <<= 0x10; in polaris10_calculate_sclk_params()
934 sclk_setting->Fcw_frac = temp & 0xffff; in polaris10_calculate_sclk_params()
941 sclk_setting->SSc_En = 0; in polaris10_calculate_sclk_params()
947 temp <<= 0x10; in polaris10_calculate_sclk_params()
949 sclk_setting->Fcw1_frac = temp & 0xffff; in polaris10_calculate_sclk_params()
952 return 0; in polaris10_calculate_sclk_params()
964 SMU_SclkSetting curr_sclk_setting = { 0 }; in polaris10_populate_single_graphic_level()
979 PP_ASSERT_WITH_CODE((0 == result), in polaris10_populate_single_graphic_level()
985 level->CcPwrDynRm = 0; in polaris10_populate_single_graphic_level()
986 level->CcPwrDynRm1 = 0; in polaris10_populate_single_graphic_level()
987 level->EnabledForActivity = 0; in polaris10_populate_single_graphic_level()
991 level->VoltageDownHyst = 0; in polaris10_populate_single_graphic_level()
992 level->PowerThrottle = 0; in polaris10_populate_single_graphic_level()
1023 return 0; in polaris10_populate_single_graphic_level()
1045 int result = 0; in polaris10_populate_all_graphic_levels()
1053 uint8_t hightest_pcie_level_enabled = 0, in polaris10_populate_all_graphic_levels()
1054 lowest_pcie_level_enabled = 0, in polaris10_populate_all_graphic_levels()
1055 mid_pcie_level_enabled = 0, in polaris10_populate_all_graphic_levels()
1056 count = 0; in polaris10_populate_all_graphic_levels()
1059 uint32_t dpm0_sclkfrequency = levels[0].SclkSetting.SclkFrequency; in polaris10_populate_all_graphic_levels()
1067 for (i = 0; i < dpm_table->sclk_table.count; i++) { in polaris10_populate_all_graphic_levels()
1075 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */ in polaris10_populate_all_graphic_levels()
1077 levels[i].DeepSleepDivId = 0; in polaris10_populate_all_graphic_levels()
1081 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0; in polaris10_populate_all_graphic_levels()
1082 if (dpm0_sclkfrequency != levels[0].SclkSetting.SclkFrequency) { in polaris10_populate_all_graphic_levels()
1084 dpm_table->sclk_table.dpm_levels[0].value, in polaris10_populate_all_graphic_levels()
1086 PP_ASSERT_WITH_CODE((0 == result), in polaris10_populate_all_graphic_levels()
1091 dividers.real_clock < dpm_table->sclk_table.dpm_levels[0].value ? in polaris10_populate_all_graphic_levels()
1102 for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) in polaris10_populate_all_graphic_levels()
1111 for (i = 0; i < dpm_table->sclk_table.count; i++) in polaris10_populate_all_graphic_levels()
1117 (1 << (hightest_pcie_level_enabled + 1))) != 0)) in polaris10_populate_all_graphic_levels()
1122 (1 << lowest_pcie_level_enabled)) == 0)) in polaris10_populate_all_graphic_levels()
1127 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0)) in polaris10_populate_all_graphic_levels()
1140 levels[0].pcieDpmLevel = lowest_pcie_level_enabled; in polaris10_populate_all_graphic_levels()
1159 int result = 0; in polaris10_populate_single_memory_level()
1173 PP_ASSERT_WITH_CODE((0 == result), in polaris10_populate_single_memory_level()
1180 mem_level->EnabledForActivity = 0; in polaris10_populate_single_memory_level()
1183 mem_level->VoltageDownHyst = 0; in polaris10_populate_single_memory_level()
1194 STUTTER_ENABLE) & 0x1) && in polaris10_populate_single_memory_level()
1223 for (i = 0; i < dpm_table->mclk_table.count; i++) { in polaris10_populate_all_memory_levels()
1224 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in polaris10_populate_all_memory_levels()
1241 for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) in polaris10_populate_all_memory_levels()
1258 uint32_t i = 0; in polaris10_populate_mvdd_value()
1262 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) { in polaris10_populate_mvdd_value()
1274 return 0; in polaris10_populate_mvdd_value()
1280 int result = 0; in polaris10_populate_smc_acpi_level()
1297 PP_ASSERT_WITH_CODE((0 == result), in polaris10_populate_smc_acpi_level()
1303 …PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return resu… in polaris10_populate_smc_acpi_level()
1305 table->ACPILevel.DeepSleepDivId = 0; in polaris10_populate_smc_acpi_level()
1306 table->ACPILevel.CcPwrDynRm = 0; in polaris10_populate_smc_acpi_level()
1307 table->ACPILevel.CcPwrDynRm1 = 0; in polaris10_populate_smc_acpi_level()
1332 PP_ASSERT_WITH_CODE((0 == result), in polaris10_populate_smc_acpi_level()
1340 data->dpm_table.mclk_table.dpm_levels[0].value, in polaris10_populate_smc_acpi_level()
1343 if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level)) in polaris10_populate_smc_acpi_level()
1346 table->MemoryACPILevel.MinMvdd = 0; in polaris10_populate_smc_acpi_level()
1350 table->MemoryACPILevel.EnabledForThrottle = 0; in polaris10_populate_smc_acpi_level()
1351 table->MemoryACPILevel.EnabledForActivity = 0; in polaris10_populate_smc_acpi_level()
1352 table->MemoryACPILevel.UpHyst = 0; in polaris10_populate_smc_acpi_level()
1354 table->MemoryACPILevel.VoltageDownHyst = 0; in polaris10_populate_smc_acpi_level()
1379 table->VceBootLevel = 0; in polaris10_populate_smc_vce_level()
1381 for (count = 0; count < table->VceLevelCount; count++) { in polaris10_populate_smc_vce_level()
1383 table->VceLevel[count].MinVoltage = 0; in polaris10_populate_smc_vce_level()
1403 PP_ASSERT_WITH_CODE((0 == result), in polaris10_populate_smc_vce_level()
1429 table->SamuBootLevel = 0; in polaris10_populate_smc_samu_level()
1431 for (count = 0; count < table->SamuLevelCount; count++) { in polaris10_populate_smc_samu_level()
1452 PP_ASSERT_WITH_CODE((0 == result), in polaris10_populate_smc_samu_level()
1475 PP_ASSERT_WITH_CODE(result == 0, in polaris10_populate_memory_timing_parameters()
1487 return 0; in polaris10_populate_memory_timing_parameters()
1496 int result = 0; in polaris10_program_memory_timing_parameters()
1498 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { in polaris10_program_memory_timing_parameters()
1499 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { in polaris10_program_memory_timing_parameters()
1504 if (result == 0 && i == 0) in polaris10_program_memory_timing_parameters()
1506 if (result != 0) in polaris10_program_memory_timing_parameters()
1534 table->UvdBootLevel = 0; in polaris10_populate_smc_uvd_level()
1536 for (count = 0; count < table->UvdLevelCount; count++) { in polaris10_populate_smc_uvd_level()
1537 table->UvdLevel[count].MinVoltage = 0; in polaris10_populate_smc_uvd_level()
1557 PP_ASSERT_WITH_CODE((0 == result), in polaris10_populate_smc_uvd_level()
1564 PP_ASSERT_WITH_CODE((0 == result), in polaris10_populate_smc_uvd_level()
1580 int result = 0; in polaris10_populate_smc_boot_level()
1583 table->GraphicsBootLevel = 0; in polaris10_populate_smc_boot_level()
1584 table->MemoryBootLevel = 0; in polaris10_populate_smc_boot_level()
1591 table->GraphicsBootLevel = 0; in polaris10_populate_smc_boot_level()
1592 result = 0; in polaris10_populate_smc_boot_level()
1599 table->MemoryBootLevel = 0; in polaris10_populate_smc_boot_level()
1600 result = 0; in polaris10_populate_smc_boot_level()
1614 return 0; in polaris10_populate_smc_boot_level()
1627 for (level = 0; level < count; level++) { in polaris10_populate_smc_initailial_state()
1636 for (level = 0; level < count; level++) { in polaris10_populate_smc_initailial_state()
1644 return 0; in polaris10_populate_smc_initailial_state()
1659 uint8_t i, stretch_amount, volt_offset = 0; in polaris10_populate_clock_stretcher_data_table()
1671 for (i = 0; i < sclk_table->count; i++) { in polaris10_populate_clock_stretcher_data_table()
1693 …smu_data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_i… in polaris10_populate_clock_stretcher_data_table()
1696 if (stretch_amount == 0 || stretch_amount > 5) { in polaris10_populate_clock_stretcher_data_table()
1705 value &= 0xFFFFFFFE; in polaris10_populate_clock_stretcher_data_table()
1708 return 0; in polaris10_populate_clock_stretcher_data_table()
1750 offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1); in polaris10_populate_vr_config()
1759 offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1); in polaris10_populate_vr_config()
1765 return 0; in polaris10_populate_vr_config()
1776 int result = 0; in polaris10_populate_avfs_parameters()
1777 struct pp_atom_ctrl__avfs_parameters avfs_params = {0}; in polaris10_populate_avfs_parameters()
1778 AVFS_meanNsigma_t AVFS_meanNsigma = { {0} }; in polaris10_populate_avfs_parameters()
1779 AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} }; in polaris10_populate_avfs_parameters()
1789 return 0; in polaris10_populate_avfs_parameters()
1793 hwmgr->avfs_supported = 0; in polaris10_populate_avfs_parameters()
1794 return 0; in polaris10_populate_avfs_parameters()
1799 if (0 == result) { in polaris10_populate_avfs_parameters()
1804 if ((adev->pdev->device == 0x67ef && adev->pdev->revision == 0xe5) || in polaris10_populate_avfs_parameters()
1805 (adev->pdev->device == 0x67ff && adev->pdev->revision == 0xef)) { in polaris10_populate_avfs_parameters()
1806 if ((avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 == 0xEA522DD3) && in polaris10_populate_avfs_parameters()
1807 (avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 == 0x5645A) && in polaris10_populate_avfs_parameters()
1808 (avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 == 0x33F9E) && in polaris10_populate_avfs_parameters()
1809 (avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 == 0xFFFFC5CC) && in polaris10_populate_avfs_parameters()
1810 (avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 == 0x1B1A) && in polaris10_populate_avfs_parameters()
1811 (avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b == 0xFFFFFCED)) { in polaris10_populate_avfs_parameters()
1812 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 = 0xF718F1D4; in polaris10_populate_avfs_parameters()
1813 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 = 0x323FD; in polaris10_populate_avfs_parameters()
1814 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 = 0x1E455; in polaris10_populate_avfs_parameters()
1815 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0; in polaris10_populate_avfs_parameters()
1816 avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0; in polaris10_populate_avfs_parameters()
1817 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b = 0x23; in polaris10_populate_avfs_parameters()
1820 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 = 0xF6B024DD; in polaris10_populate_avfs_parameters()
1821 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 = 0x3005E; in polaris10_populate_avfs_parameters()
1822 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 = 0x18A5F; in polaris10_populate_avfs_parameters()
1823 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0x315; in polaris10_populate_avfs_parameters()
1824 avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0xFED1; in polaris10_populate_avfs_parameters()
1825 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b = 0x3B; in polaris10_populate_avfs_parameters()
1827 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 = 0xF843B66B; in polaris10_populate_avfs_parameters()
1828 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 = 0x59CB5; in polaris10_populate_avfs_parameters()
1829 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 = 0xFFFF287F; in polaris10_populate_avfs_parameters()
1830 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0; in polaris10_populate_avfs_parameters()
1831 avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0xFF23; in polaris10_populate_avfs_parameters()
1832 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b = 0x58; in polaris10_populate_avfs_parameters()
1837 if (0 == result) { in polaris10_populate_avfs_parameters()
1838 table->BTCGB_VDROOP_TABLE[0].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0); in polaris10_populate_avfs_parameters()
1839 table->BTCGB_VDROOP_TABLE[0].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1); in polaris10_populate_avfs_parameters()
1840 table->BTCGB_VDROOP_TABLE[0].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2); in polaris10_populate_avfs_parameters()
1844 table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1); in polaris10_populate_avfs_parameters()
1845 table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2); in polaris10_populate_avfs_parameters()
1846 table->AVFSGB_VDROOP_TABLE[0].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b); in polaris10_populate_avfs_parameters()
1847 table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24; in polaris10_populate_avfs_parameters()
1848 table->AVFSGB_VDROOP_TABLE[0].m2_shift = 12; in polaris10_populate_avfs_parameters()
1855 AVFS_meanNsigma.Aconstant[0] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0); in polaris10_populate_avfs_parameters()
1863 for (i = 0; i < NUM_VFT_COLUMNS; i++) { in polaris10_populate_avfs_parameters()
1909 smu_data->power_tune_defaults = &polaris10_power_tune_data_set_array[0]; in polaris10_initialize_power_tune_defaults()
1932 table->SystemFlags = 0; in polaris10_init_smc_table()
1946 PP_ASSERT_WITH_CODE(0 == result, in polaris10_init_smc_table()
1953 PP_ASSERT_WITH_CODE(0 == result, in polaris10_init_smc_table()
1957 PP_ASSERT_WITH_CODE(0 == result, in polaris10_init_smc_table()
1961 PP_ASSERT_WITH_CODE(0 == result, in polaris10_init_smc_table()
1965 PP_ASSERT_WITH_CODE(0 == result, in polaris10_init_smc_table()
1969 PP_ASSERT_WITH_CODE(0 == result, in polaris10_init_smc_table()
1973 PP_ASSERT_WITH_CODE(0 == result, in polaris10_init_smc_table()
1981 PP_ASSERT_WITH_CODE(0 == result, in polaris10_init_smc_table()
1985 PP_ASSERT_WITH_CODE(0 == result, in polaris10_init_smc_table()
1989 PP_ASSERT_WITH_CODE(0 == result, in polaris10_init_smc_table()
1993 PP_ASSERT_WITH_CODE(0 == result, in polaris10_init_smc_table()
1997 PP_ASSERT_WITH_CODE(0 == result, in polaris10_init_smc_table()
2005 PP_ASSERT_WITH_CODE(0 == result, in polaris10_init_smc_table()
2011 PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;); in polaris10_init_smc_table()
2013 table->CurrSclkPllRange = 0xff; in polaris10_init_smc_table()
2027 table->VoltageResponseTime = 0; in polaris10_init_smc_table()
2028 table->PhaseResponseTime = 0; in polaris10_init_smc_table()
2032 table->VRConfig = 0; in polaris10_init_smc_table()
2035 PP_ASSERT_WITH_CODE(0 == result, in polaris10_init_smc_table()
2039 table->SclkStepSize = 0x4000; in polaris10_init_smc_table()
2078 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) in polaris10_init_smc_table()
2079 & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0; in polaris10_init_smc_table()
2093 for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) { in polaris10_init_smc_table()
2095 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result); in polaris10_init_smc_table()
2097 if (i == 0) in polaris10_init_smc_table()
2103 for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++) in polaris10_init_smc_table()
2124 PP_ASSERT_WITH_CODE(0 == result, in polaris10_init_smc_table()
2128 PP_ASSERT_WITH_CODE(0 == result, in polaris10_init_smc_table()
2131 return 0; in polaris10_init_smc_table()
2142 return 0; in polaris10_program_mem_timing_parameters()
2150 return 0; in polaris10_thermal_avfs_enable()
2164 return 0; in polaris10_thermal_avfs_enable()
2181 return 0; in polaris10_thermal_setup_fan_table()
2184 if (smu_data->smu7_data.fan_table_start == 0) { in polaris10_thermal_setup_fan_table()
2187 return 0; in polaris10_thermal_setup_fan_table()
2193 if (duty100 == 0) { in polaris10_thermal_setup_fan_table()
2196 return 0; in polaris10_thermal_setup_fan_table()
2201 return 0; in polaris10_thermal_setup_fan_table()
2278 return 0; in polaris10_thermal_setup_fan_table()
2288 smu_data->smc_state_table.UvdBootLevel = 0; in polaris10_update_uvd_smc_table()
2289 if (table_info->mm_dep_table->count > 0) in polaris10_update_uvd_smc_table()
2298 mm_boot_level_value &= 0x00FFFFFF; in polaris10_update_uvd_smc_table()
2311 return 0; in polaris10_update_uvd_smc_table()
2326 smu_data->smc_state_table.VceBootLevel = 0; in polaris10_update_vce_smc_table()
2334 mm_boot_level_value &= 0xFF00FFFF; in polaris10_update_vce_smc_table()
2344 return 0; in polaris10_update_vce_smc_table()
2359 for (i = 0; i < max_entry; i++) in polaris10_update_bif_smc_table()
2361 return 0; in polaris10_update_bif_smc_table()
2379 return 0; in polaris10_update_smc_table()
2387 int result = 0; in polaris10_update_sclk_threshold()
2388 uint32_t low_sclk_interrupt_threshold = 0; in polaris10_update_sclk_threshold()
2392 && (data->low_sclk_interrupt_threshold != 0)) { in polaris10_update_sclk_threshold()
2407 PP_ASSERT_WITH_CODE((result == 0), in polaris10_update_sclk_threshold()
2411 PP_ASSERT_WITH_CODE((result == 0), in polaris10_update_sclk_threshold()
2461 return 0; in polaris10_get_offsetof()
2489 return 0; in polaris10_get_mac_definition()
2505 if (0 == result) in polaris10_process_firmware_header()
2508 error |= (0 != result); in polaris10_process_firmware_header()
2520 error |= (0 != result); in polaris10_process_firmware_header()
2538 error |= (0 != result); in polaris10_process_firmware_header()
2548 error |= (0 != result); in polaris10_process_firmware_header()
2558 error |= (0 != result); in polaris10_process_firmware_header()
2560 return error ? -1 : 0; in polaris10_process_firmware_header()
2565 return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16)); in polaris10_get_memory_modile_index()
2574 memset(mc_reg_table, 0, sizeof(pp_atomctrl_mc_reg_table)); in polaris10_initialize_mc_reg_table()
2613 for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) { in polaris10_update_dpm_settings()
2620 offset = clk_activity_offset & ~0x3; in polaris10_update_dpm_settings()
2634 offset = up_hyst_offset & ~0x3; in polaris10_update_dpm_settings()
2648 for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) { in polaris10_update_dpm_settings()
2655 offset = clk_activity_offset & ~0x3; in polaris10_update_dpm_settings()
2669 offset = up_hyst_offset & ~0x3; in polaris10_update_dpm_settings()
2679 return 0; in polaris10_update_dpm_settings()