Lines Matching +full:0 +full:x255
62 #define ICELAND_SMC_SIZE 0x20000
65 #define MC_CG_ARB_FREQ_F1 0x0b
68 #define DEVICE_ID_VI_ICELAND_M_6900 0x6900
69 #define DEVICE_ID_VI_ICELAND_M_6901 0x6901
70 #define DEVICE_ID_VI_ICELAND_M_6902 0x6902
71 #define DEVICE_ID_VI_ICELAND_M_6903 0x6903
78 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
79 …{ 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D,…
80 …{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5…
91 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x0,
92 { 0xA7, 0x0, 0x0, 0xB5, 0x0, 0x0, 0x9F, 0x0, 0x0, 0xD6, 0x0, 0x0, 0xD7, 0x0, 0x0},
93 { 0x1EA, 0x0, 0x0, 0x224, 0x0, 0x0, 0x25E, 0x0, 0x0, 0x28E, 0x0, 0x0, 0x2AB, 0x0, 0x0}
104 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x0,
105 { 0xB7, 0x0, 0x0, 0xC3, 0x0, 0x0, 0xB5, 0x0, 0x0, 0xEA, 0x0, 0x0, 0xE6, 0x0, 0x0},
106 { 0x1EA, 0x0, 0x0, 0x224, 0x0, 0x0, 0x25E, 0x0, 0x0, 0x28E, 0x0, 0x0, 0x2AB, 0x0, 0x0}
112 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in iceland_start_smc()
114 return 0; in iceland_start_smc()
136 ck_disable, 0); in iceland_start_smc_clock()
141 /* set smc instruct start point at 0x0 */ in iceland_smu_start_smc()
153 return 0; in iceland_smu_start_smc()
170 data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3]; in iceland_upload_smc_firmware_data()
176 PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); in iceland_upload_smc_firmware_data()
178 PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be divisible by 4.", return -EINVAL); in iceland_upload_smc_firmware_data()
180 return 0; in iceland_upload_smc_firmware_data()
187 struct cgs_firmware_info info = {0}; in iceland_smu_upload_firmware_image()
208 RCU_UC_EVENTS, boot_seq_done, 0); in iceland_smu_upload_firmware_image()
225 return 0; in iceland_smu_upload_firmware_image()
231 return 0; in iceland_request_smu_load_specific_fw()
253 &(priv->smu7_data.soft_regs_start), 0x40000); in iceland_start_smu()
276 return 0; in iceland_smu_init()
314 smu_data->power_tune_table.SviLoadLineOffsetVddC = 0; in iceland_populate_svi_load_line()
316 return 0; in iceland_populate_svi_load_line()
332 return 0; in iceland_populate_tdc_limit()
351 return 0; in iceland_populate_dw8()
356 return 0; in iceland_populate_temperature_scaler()
365 for (i = 0; i < 8; i++) in iceland_populate_gnb_lpml()
366 smu_data->power_tune_table.GnbLPML[i] = 0; in iceland_populate_gnb_lpml()
368 return 0; in iceland_populate_gnb_lpml()
386 return 0; in iceland_populate_bapm_vddc_base_leakage_sidd()
404 for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) { in iceland_populate_bapm_vddc_vid_sidd()
412 return 0; in iceland_populate_bapm_vddc_vid_sidd()
426 for (i = 0; i < (int)data->vddc_voltage_table.count; i++) { in iceland_populate_vddc_vid()
430 return 0; in iceland_populate_vddc_vid()
479 if (0 != iceland_populate_temperature_scaler(hwmgr)) in iceland_populate_pm_fuses()
503 return 0; in iceland_populate_pm_fuses()
510 uint32_t i = 0; in iceland_get_dependency_volt_by_clk()
513 if (allowed_clock_voltage_table->count == 0) in iceland_get_dependency_volt_by_clk()
516 for (i = 0; i < allowed_clock_voltage_table->count; i++) { in iceland_get_dependency_volt_by_clk()
520 return 0; in iceland_get_dependency_volt_by_clk()
527 return 0; in iceland_get_dependency_volt_by_clk()
546 return 0; in iceland_get_std_voltage_value_sidd()
554 for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in iceland_get_std_voltage_value_sidd()
574 …for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in iceland_get_std_voltage_value_sidd()
593 return 0; in iceland_get_std_voltage_value_sidd()
605 if (0 != result) { in iceland_populate_smc_voltage_table()
614 return 0; in iceland_populate_smc_voltage_table()
625 for (count = 0; count < table->VddcLevelCount; count++) { in iceland_populate_smc_vddc_table()
629 PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL); in iceland_populate_smc_vddc_table()
635 table->VddcLevel[count].Smio = 0; in iceland_populate_smc_vddc_table()
640 return 0; in iceland_populate_smc_vddc_table()
652 for (count = 0; count < table->VddciLevelCount; count++) { in iceland_populate_smc_vdd_ci_table()
656 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL); in iceland_populate_smc_vdd_ci_table()
660 table->VddciLevel[count].Smio |= 0; in iceland_populate_smc_vdd_ci_table()
665 return 0; in iceland_populate_smc_vdd_ci_table()
677 for (count = 0; count < table->VddciLevelCount; count++) { in iceland_populate_smc_mvdd_table()
681 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL); in iceland_populate_smc_mvdd_table()
685 table->MvddLevel[count].Smio |= 0; in iceland_populate_smc_mvdd_table()
690 return 0; in iceland_populate_smc_mvdd_table()
700 PP_ASSERT_WITH_CODE(0 == result, in iceland_populate_smc_voltage_tables()
704 PP_ASSERT_WITH_CODE(0 == result, in iceland_populate_smc_voltage_tables()
708 PP_ASSERT_WITH_CODE(0 == result, in iceland_populate_smc_voltage_tables()
711 return 0; in iceland_populate_smc_voltage_tables()
721 state->CcPwrDynRm = 0; in iceland_populate_ulv_level()
722 state->CcPwrDynRm1 = 0; in iceland_populate_ulv_level()
725 PP_ASSERT_WITH_CODE((0 == result), "can not get ULV voltage value", return result;); in iceland_populate_ulv_level()
727 if (ulv_voltage == 0) { in iceland_populate_ulv_level()
729 return 0; in iceland_populate_ulv_level()
734 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in iceland_populate_ulv_level()
735 state->VddcOffset = 0; in iceland_populate_ulv_level()
738 …state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltag… in iceland_populate_ulv_level()
741 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in iceland_populate_ulv_level()
742 state->VddcOffsetVid = 0; in iceland_populate_ulv_level()
745 (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage) in iceland_populate_ulv_level()
755 return 0; in iceland_populate_ulv_level()
772 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in iceland_populate_smc_link_level()
780 (uint8_t)(data->pcie_spc_cap & 0xff); in iceland_populate_smc_link_level()
792 return 0; in iceland_populate_smc_link_level()
813 PP_ASSERT_WITH_CODE(result == 0, in iceland_calculate_sclk_params()
822 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in iceland_calculate_sclk_params()
843 if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) { in iceland_calculate_sclk_params()
870 return 0; in iceland_calculate_sclk_params()
882 for (i = 0; i < pl->count; i++) { in iceland_populate_phase_value_based_on_sclk()
888 return 0; in iceland_populate_phase_value_based_on_sclk()
904 PP_ASSERT_WITH_CODE((0 == result), in iceland_populate_single_graphic_level()
920 graphic_level->CcPwrDynRm = 0; in iceland_populate_single_graphic_level()
921 graphic_level->CcPwrDynRm1 = 0; in iceland_populate_single_graphic_level()
923 graphic_level->EnabledForActivity = 0; in iceland_populate_single_graphic_level()
928 graphic_level->VoltageDownHyst = 0; in iceland_populate_single_graphic_level()
929 graphic_level->PowerThrottle = 0; in iceland_populate_single_graphic_level()
943 if (0 == result) { in iceland_populate_single_graphic_level()
973 uint8_t highest_pcie_level_enabled = 0; in iceland_populate_all_graphic_levels()
974 uint8_t lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0; in iceland_populate_all_graphic_levels()
975 uint8_t count = 0; in iceland_populate_all_graphic_levels()
976 int result = 0; in iceland_populate_all_graphic_levels()
978 memset(levels, 0x00, level_array_size); in iceland_populate_all_graphic_levels()
980 for (i = 0; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
984 if (result != 0) in iceland_populate_all_graphic_levels()
987 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */ in iceland_populate_all_graphic_levels()
989 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in iceland_populate_all_graphic_levels()
992 /* Only enable level 0 for now. */ in iceland_populate_all_graphic_levels()
993 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in iceland_populate_all_graphic_levels()
1006 (1 << (highest_pcie_level_enabled + 1))) != 0) { in iceland_populate_all_graphic_levels()
1011 (1 << lowest_pcie_level_enabled)) == 0) { in iceland_populate_all_graphic_levels()
1017 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0)) { in iceland_populate_all_graphic_levels()
1031 smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled; in iceland_populate_all_graphic_levels()
1069 PP_ASSERT_WITH_CODE(0 == result, in iceland_calculate_mclk_params()
1107 CLKS = NS - 1 = ISS_STEP_NUM[11:0] in iceland_calculate_mclk_params()
1109 CLKV = 65536 * NV = ISS_STEP_SIZE[25:0] in iceland_calculate_mclk_params()
1127 if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) { in iceland_calculate_mclk_params()
1166 return 0; in iceland_calculate_mclk_params()
1176 mc_para_index = 0x00; in iceland_get_mclk_frequency_ratio()
1178 mc_para_index = 0x0f; in iceland_get_mclk_frequency_ratio()
1184 mc_para_index = 0x00; in iceland_get_mclk_frequency_ratio()
1186 mc_para_index = 0x0f; in iceland_get_mclk_frequency_ratio()
1200 mc_para_index = 0; in iceland_get_ddr3_mclk_frequency_ratio()
1202 mc_para_index = 0x0f; in iceland_get_ddr3_mclk_frequency_ratio()
1217 for (i = 0; i < pl->count; i++) { in iceland_populate_phase_value_based_on_mclk()
1224 return 0; in iceland_populate_phase_value_based_on_mclk()
1234 int result = 0; in iceland_populate_single_memory_level()
1243 PP_ASSERT_WITH_CODE((0 == result), in iceland_populate_single_memory_level()
1254 PP_ASSERT_WITH_CODE((0 == result), in iceland_populate_single_memory_level()
1266 memory_level->EnabledForActivity = 0; in iceland_populate_single_memory_level()
1269 memory_level->VoltageDownHyst = 0; in iceland_populate_single_memory_level()
1273 memory_level->StutterEnable = 0; in iceland_populate_single_memory_level()
1274 memory_level->StrobeEnable = 0; in iceland_populate_single_memory_level()
1275 memory_level->EdcReadEnable = 0; in iceland_populate_single_memory_level()
1276 memory_level->EdcWriteEnable = 0; in iceland_populate_single_memory_level()
1277 memory_level->RttEnable = 0; in iceland_populate_single_memory_level()
1288 memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) && in iceland_populate_single_memory_level()
1296 if ((mclk_edc_enable_threshold != 0) && in iceland_populate_single_memory_level()
1301 if ((mclk_edc_wr_enable_threshold != 0) && in iceland_populate_single_memory_level()
1308 ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) in iceland_populate_single_memory_level()
1309 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; in iceland_populate_single_memory_level()
1311 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0; in iceland_populate_single_memory_level()
1317 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; in iceland_populate_single_memory_level()
1323 if (0 == result) { in iceland_populate_single_memory_level()
1359 memset(levels, 0x00, level_array_size); in iceland_populate_all_memory_levels()
1361 for (i = 0; i < dpm_table->mclk_table.count; i++) { in iceland_populate_all_memory_levels()
1362 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in iceland_populate_all_memory_levels()
1366 if (0 != result) { in iceland_populate_all_memory_levels()
1371 /* Only enable level 0 for now.*/ in iceland_populate_all_memory_levels()
1372 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in iceland_populate_all_memory_levels()
1379 smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; in iceland_populate_all_memory_levels()
1380 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel); in iceland_populate_all_memory_levels()
1400 uint32_t i = 0; in iceland_populate_mvdd_value()
1404 for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) { in iceland_populate_mvdd_value()
1419 return 0; in iceland_populate_mvdd_value()
1425 int result = 0; in iceland_populate_smc_acpi_level()
1428 uint32_t vddc_phase_shed_control = 0; in iceland_populate_smc_acpi_level()
1445 table->ACPILevel.MinVddcPhases = vddc_phase_shed_control ? 0 : 1; in iceland_populate_smc_acpi_level()
1453 PP_ASSERT_WITH_CODE(result == 0, in iceland_populate_smc_acpi_level()
1459 table->ACPILevel.DeepSleepDivId = 0; in iceland_populate_smc_acpi_level()
1462 CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0); in iceland_populate_smc_acpi_level()
1474 table->ACPILevel.CcPwrDynRm = 0; in iceland_populate_smc_acpi_level()
1475 table->ACPILevel.CcPwrDynRm1 = 0; in iceland_populate_smc_acpi_level()
1498 if (data->acpi_vddci != 0) in iceland_populate_smc_acpi_level()
1504 if (0 == iceland_populate_mvdd_value(hwmgr, 0, &voltage_level)) in iceland_populate_smc_acpi_level()
1508 table->MemoryACPILevel.MinMvdd = 0; in iceland_populate_smc_acpi_level()
1512 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1); in iceland_populate_smc_acpi_level()
1514 MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1); in iceland_populate_smc_acpi_level()
1518 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0); in iceland_populate_smc_acpi_level()
1520 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0); in iceland_populate_smc_acpi_level()
1524 DLL_CNTL, MRDCK0_BYPASS, 0); in iceland_populate_smc_acpi_level()
1526 DLL_CNTL, MRDCK1_BYPASS, 0); in iceland_populate_smc_acpi_level()
1547 table->MemoryACPILevel.EnabledForThrottle = 0; in iceland_populate_smc_acpi_level()
1548 table->MemoryACPILevel.EnabledForActivity = 0; in iceland_populate_smc_acpi_level()
1549 table->MemoryACPILevel.UpHyst = 0; in iceland_populate_smc_acpi_level()
1551 table->MemoryACPILevel.VoltageDownHyst = 0; in iceland_populate_smc_acpi_level()
1555 table->MemoryACPILevel.StutterEnable = 0; in iceland_populate_smc_acpi_level()
1556 table->MemoryACPILevel.StrobeEnable = 0; in iceland_populate_smc_acpi_level()
1557 table->MemoryACPILevel.EdcReadEnable = 0; in iceland_populate_smc_acpi_level()
1558 table->MemoryACPILevel.EdcWriteEnable = 0; in iceland_populate_smc_acpi_level()
1559 table->MemoryACPILevel.RttEnable = 0; in iceland_populate_smc_acpi_level()
1567 return 0; in iceland_populate_smc_uvd_level()
1573 return 0; in iceland_populate_smc_vce_level()
1579 return 0; in iceland_populate_smc_acp_level()
1597 PP_ASSERT_WITH_CODE(result == 0, in iceland_populate_memory_timing_parameters()
1608 return 0; in iceland_populate_memory_timing_parameters()
1615 int result = 0; in iceland_program_memory_timing_parameters()
1619 memset(&arb_regs, 0x00, sizeof(SMU71_Discrete_MCArbDramTimingTable)); in iceland_program_memory_timing_parameters()
1621 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in iceland_program_memory_timing_parameters()
1622 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in iceland_program_memory_timing_parameters()
1628 if (0 != result) { in iceland_program_memory_timing_parameters()
1634 if (0 == result) { in iceland_program_memory_timing_parameters()
1650 int result = 0; in iceland_populate_smc_boot_level()
1653 table->GraphicsBootLevel = 0; in iceland_populate_smc_boot_level()
1654 table->MemoryBootLevel = 0; in iceland_populate_smc_boot_level()
1661 if (0 != result) { in iceland_populate_smc_boot_level()
1662 smu_data->smc_state_table.GraphicsBootLevel = 0; in iceland_populate_smc_boot_level()
1663 …r("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0!\n"); in iceland_populate_smc_boot_level()
1664 result = 0; in iceland_populate_smc_boot_level()
1671 if (0 != result) { in iceland_populate_smc_boot_level()
1672 smu_data->smc_state_table.MemoryBootLevel = 0; in iceland_populate_smc_boot_level()
1673 …pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\… in iceland_populate_smc_boot_level()
1674 result = 0; in iceland_populate_smc_boot_level()
1695 for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) { in iceland_populate_mc_reg_address()
1709 return 0; in iceland_populate_mc_reg_address()
1720 for (i = 0, j = 0; j < num_entries; j++) { in iceland_convert_mc_registers()
1734 uint32_t i = 0; in iceland_convert_mc_reg_table_entry_to_smc()
1736 for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) { in iceland_convert_mc_reg_table_entry_to_smc()
1743 if ((i == smu_data->mc_reg_table.num_entries) && (i > 0)) in iceland_convert_mc_reg_table_entry_to_smc()
1750 return 0; in iceland_convert_mc_reg_table_entry_to_smc()
1756 int result = 0; in iceland_convert_mc_reg_table_to_smc()
1761 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { in iceland_convert_mc_reg_table_to_smc()
1768 if (0 != res) in iceland_convert_mc_reg_table_to_smc()
1782 if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in iceland_update_and_upload_mc_reg_table()
1783 return 0; in iceland_update_and_upload_mc_reg_table()
1786 memset(&smu_data->mc_regs, 0, sizeof(SMU71_Discrete_MCRegisters)); in iceland_update_and_upload_mc_reg_table()
1790 if (result != 0) in iceland_update_and_upload_mc_reg_table()
1794 …= smu_data->smu7_data.mc_reg_table_start + (uint32_t)offsetof(SMU71_Discrete_MCRegisters, data[0]); in iceland_update_and_upload_mc_reg_table()
1797 (uint8_t *)&smu_data->mc_regs.data[0], in iceland_update_and_upload_mc_reg_table()
1807 memset(&smu_data->mc_regs, 0x00, sizeof(SMU71_Discrete_MCRegisters)); in iceland_populate_initial_mc_reg_table()
1809 PP_ASSERT_WITH_CODE(0 == result, in iceland_populate_initial_mc_reg_table()
1813 PP_ASSERT_WITH_CODE(0 == result, in iceland_populate_initial_mc_reg_table()
1828 for (level = 0; level < count; level++) { in iceland_populate_smc_initial_state()
1838 for (level = 0; level < count; level++) { in iceland_populate_smc_initial_state()
1846 return 0; in iceland_populate_smc_initial_state()
1870 dpm_table->DTETjOffset = 0; in iceland_populate_bapm_parameters_in_dpm_table()
1882 dpm_table->PPM_PkgPwrLimit = 0; in iceland_populate_bapm_parameters_in_dpm_table()
1883 dpm_table->PPM_TemperatureLimit = 0; in iceland_populate_bapm_parameters_in_dpm_table()
1893 for (i = 0; i < SMU71_DTE_ITERATIONS; i++) { in iceland_populate_bapm_parameters_in_dpm_table()
1894 for (j = 0; j < SMU71_DTE_SOURCES; j++) { in iceland_populate_bapm_parameters_in_dpm_table()
1895 for (k = 0; k < SMU71_DTE_SINKS; k++) { in iceland_populate_bapm_parameters_in_dpm_table()
1904 return 0; in iceland_populate_bapm_parameters_in_dpm_table()
1926 return 0; in iceland_populate_smc_svi2_config()
1938 memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table)); in iceland_init_smc_table()
1959 PP_ASSERT_WITH_CODE(0 == result, in iceland_init_smc_table()
1963 ixCG_ULV_PARAMETER, 0x40035); in iceland_init_smc_table()
1967 PP_ASSERT_WITH_CODE(0 == result, in iceland_init_smc_table()
1971 PP_ASSERT_WITH_CODE(0 == result, in iceland_init_smc_table()
1975 PP_ASSERT_WITH_CODE(0 == result, in iceland_init_smc_table()
1979 PP_ASSERT_WITH_CODE(0 == result, in iceland_init_smc_table()
1983 PP_ASSERT_WITH_CODE(0 == result, in iceland_init_smc_table()
1987 PP_ASSERT_WITH_CODE(0 == result, in iceland_init_smc_table()
1993 PP_ASSERT_WITH_CODE(0 == result, in iceland_init_smc_table()
1997 PP_ASSERT_WITH_CODE(0 == result, in iceland_init_smc_table()
2000 table->GraphicsBootLevel = 0; in iceland_init_smc_table()
2001 table->MemoryBootLevel = 0; in iceland_init_smc_table()
2004 PP_ASSERT_WITH_CODE(0 == result, in iceland_init_smc_table()
2008 PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot State!", return result); in iceland_init_smc_table()
2011 PP_ASSERT_WITH_CODE(0 == result, "Failed to populate BAPM Parameters!", return result); in iceland_init_smc_table()
2028 table->VoltageResponseTime = 0; in iceland_init_smc_table()
2029 table->PhaseResponseTime = 0; in iceland_init_smc_table()
2031 table->PCIeBootLinkLevel = 0; in iceland_init_smc_table()
2035 PP_ASSERT_WITH_CODE(0 == result, in iceland_init_smc_table()
2039 table->SclkStepSize = 0x4000; in iceland_init_smc_table()
2063 PP_ASSERT_WITH_CODE(0 == result, in iceland_init_smc_table()
2075 PP_ASSERT_WITH_CODE((0 == result), in iceland_init_smc_table()
2079 PP_ASSERT_WITH_CODE(0 == result, in iceland_init_smc_table()
2082 return 0; in iceland_init_smc_table()
2097 return 0; in iceland_thermal_setup_fan_table()
2102 return 0; in iceland_thermal_setup_fan_table()
2105 if (0 == smu7_data->fan_table_start) { in iceland_thermal_setup_fan_table()
2107 return 0; in iceland_thermal_setup_fan_table()
2112 if (0 == duty100) { in iceland_thermal_setup_fan_table()
2114 return 0; in iceland_thermal_setup_fan_table()
2171 return 0; in iceland_program_mem_timing_parameters()
2179 int result = 0; in iceland_update_sclk_threshold()
2180 uint32_t low_sclk_interrupt_threshold = 0; in iceland_update_sclk_threshold()
2184 && (data->low_sclk_interrupt_threshold != 0)) { in iceland_update_sclk_threshold()
2202 PP_ASSERT_WITH_CODE((0 == result), "Failed to upload MC reg table!", return result); in iceland_update_sclk_threshold()
2205 PP_ASSERT_WITH_CODE((result == 0), in iceland_update_sclk_threshold()
2251 return 0; in iceland_get_offsetof()
2275 return 0; in iceland_get_mac_definition()
2292 if (0 == result) { in iceland_process_firmware_header()
2296 error |= (0 != result); in iceland_process_firmware_header()
2303 if (0 == result) { in iceland_process_firmware_header()
2308 error |= (0 != result); in iceland_process_firmware_header()
2316 if (0 == result) { in iceland_process_firmware_header()
2325 if (0 == result) { in iceland_process_firmware_header()
2329 error |= (0 != result); in iceland_process_firmware_header()
2336 if (0 == result) { in iceland_process_firmware_header()
2340 error |= (0 != result); in iceland_process_firmware_header()
2348 if (0 == result) { in iceland_process_firmware_header()
2352 error |= (0 != result); in iceland_process_firmware_header()
2359 if (0 == result) { in iceland_process_firmware_header()
2363 error |= (0 != result); in iceland_process_firmware_header()
2365 return error ? 1 : 0; in iceland_process_firmware_header()
2372 return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16)); in iceland_get_memory_modile_index()
2473 for (i = 0; i < table->last; i++) { in iceland_set_s0_mc_reg_index()
2478 return 0; in iceland_set_s0_mc_reg_index()
2491 for (i = 0; i < table->last; i++) { in iceland_copy_vbios_smc_reg_table()
2496 for (i = 0; i < table->num_entries; i++) { in iceland_copy_vbios_smc_reg_table()
2499 for (j = 0; j < table->last; j++) { in iceland_copy_vbios_smc_reg_table()
2507 return 0; in iceland_copy_vbios_smc_reg_table()
2517 for (i = 0, j = table->last; i < table->last; i++) { in iceland_set_mc_special_registers()
2527 for (k = 0; k < table->num_entries; k++) { in iceland_set_mc_special_registers()
2529 ((temp_reg & 0xffff0000)) | in iceland_set_mc_special_registers()
2530 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); in iceland_set_mc_special_registers()
2539 for (k = 0; k < table->num_entries; k++) { in iceland_set_mc_special_registers()
2541 (temp_reg & 0xffff0000) | in iceland_set_mc_special_registers()
2542 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in iceland_set_mc_special_registers()
2545 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; in iceland_set_mc_special_registers()
2555 for (k = 0; k < table->num_entries; k++) { in iceland_set_mc_special_registers()
2557 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; in iceland_set_mc_special_registers()
2568 for (k = 0; k < table->num_entries; k++) { in iceland_set_mc_special_registers()
2570 (temp_reg & 0xffff0000) | in iceland_set_mc_special_registers()
2571 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in iceland_set_mc_special_registers()
2584 return 0; in iceland_set_mc_special_registers()
2590 for (i = 0; i < table->last; i++) { in iceland_set_valid_flag()
2600 return 0; in iceland_set_valid_flag()
2640 if (0 == result) in iceland_initialize_mc_reg_table()
2643 if (0 == result) { in iceland_initialize_mc_reg_table()
2648 if (0 == result) in iceland_initialize_mc_reg_table()