Lines Matching +full:0 +full:x30750000
54 #define FIJI_SMC_SIZE 0x20000
58 #define MC_CG_ARB_FREQ_F1 0x0b
64 {600, 1050, 3, 0}, {600, 1050, 6, 1} };
70 { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
73 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
77 {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
81 {1, 0xF, 0xFD,
83 0x19, 5, 45}
89 …0x3c0fd047, 0x30750000, 0x00, 0x03, 0x1e00, 0x00200410, 0x87020000, 0x21680000, 0x0c000000…
90 …0xa00fd047, 0x409c0000, 0x01, 0x04, 0x1e00, 0x00800510, 0x87020000, 0x21680000, 0x11000000…
91 …0x0410d047, 0x50c30000, 0x01, 0x00, 0x1e00, 0x00600410, 0x87020000, 0x21680000, 0x0d000000…
92 …0x6810d047, 0x60ea0000, 0x01, 0x00, 0x1e00, 0x00800410, 0x87020000, 0x21680000, 0x0e000000…
93 …0xcc10d047, 0xe8fd0000, 0x01, 0x00, 0x1e00, 0x00e00410, 0x87020000, 0x21680000, 0x0f000000…
94 …0x3011d047, 0x70110100, 0x01, 0x00, 0x1e00, 0x00400510, 0x87020000, 0x21680000, 0x10000000…
95 …0x9411d047, 0xf8240100, 0x01, 0x00, 0x1e00, 0x00a00510, 0x87020000, 0x21680000, 0x11000000…
96 …0xf811d047, 0x80380100, 0x01, 0x00, 0x1e00, 0x00000610, 0x87020000, 0x21680000, 0x12000000…
101 int result = 0; in fiji_start_smu_in_protection_mode()
105 RCU_UC_EVENTS, boot_seq_done, 0); */ in fiji_start_smu_in_protection_mode()
116 ixSMU_STATUS, 0); in fiji_start_smu_in_protection_mode()
119 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); in fiji_start_smu_in_protection_mode()
123 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in fiji_start_smu_in_protection_mode()
127 SMC_INTR_CNTL_MASK_0, 0x10040, 0xFFFFFFFF); */ in fiji_start_smu_in_protection_mode()
135 ixFIRMWARE_FLAGS, 0); in fiji_start_smu_in_protection_mode()
140 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_Test, 0x20000, NULL); in fiji_start_smu_in_protection_mode()
144 SMU_STATUS, SMU_DONE, 0); in fiji_start_smu_in_protection_mode()
162 int result = 0; in fiji_start_smu_in_non_protection_mode()
166 RCU_UC_EVENTS, boot_seq_done, 0); in fiji_start_smu_in_non_protection_mode()
170 ixFIRMWARE_FLAGS, 0); in fiji_start_smu_in_non_protection_mode()
180 /* Set smc instruct start point at 0x0 */ in fiji_start_smu_in_non_protection_mode()
185 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); in fiji_start_smu_in_non_protection_mode()
189 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in fiji_start_smu_in_non_protection_mode()
200 int result = 0; in fiji_start_avfs_btc()
203 if (0 != smu_data->avfs_btc_param) { in fiji_start_avfs_btc()
204 if (0 != smum_send_msg_to_smc_with_parameter(hwmgr, in fiji_start_avfs_btc()
213 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000); in fiji_start_avfs_btc()
215 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff); in fiji_start_avfs_btc()
217 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0); in fiji_start_avfs_btc()
229 PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr, in fiji_setup_graphics_level_structure()
232 &table_start, 0x40000), in fiji_setup_graphics_level_structure()
239 vr_config = 0x01000500; /* Real value:0x50001 */ in fiji_setup_graphics_level_structure()
244 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_addr, in fiji_setup_graphics_level_structure()
245 (uint8_t *)&vr_config, sizeof(int32_t), 0x40000), in fiji_setup_graphics_level_structure()
252 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, level_addr, in fiji_setup_graphics_level_structure()
253 (uint8_t *)(&avfs_graphics_level), level_size, 0x40000), in fiji_setup_graphics_level_structure()
257 return 0; in fiji_setup_graphics_level_structure()
263 return 0; in fiji_avfs_event_mgr()
265 PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(hwmgr), in fiji_avfs_event_mgr()
269 PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr), in fiji_avfs_event_mgr()
273 PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(hwmgr), in fiji_avfs_event_mgr()
278 return 0; in fiji_avfs_event_mgr()
283 int result = 0; in fiji_start_smu()
289 if (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, in fiji_start_smu()
310 &(priv->smu7_data.soft_regs_start), 0x40000); in fiji_start_smu()
320 uint32_t efuse = 0; in fiji_is_hw_avfs_present()
349 return 0; in fiji_smu_init()
359 *voltage = *mvdd = 0; in fiji_get_dependency_volt_by_clk()
363 if (dep_table->count == 0) in fiji_get_dependency_volt_by_clk()
366 for (i = 0; i < dep_table->count; i++) { in fiji_get_dependency_volt_by_clk()
392 return 0; in fiji_get_dependency_volt_by_clk()
414 return 0; in fiji_get_dependency_volt_by_clk()
461 *scl = 0; in get_scl_sda_value()
462 *sda = 0; in get_scl_sda_value()
480 smu_data->power_tune_defaults = &fiji_power_tune_data_set_array[0]; in fiji_initialize_power_tune_defaults()
564 return 0; in fiji_populate_bapm_parameters_in_dpm_table()
576 smu_data->power_tune_table.SviLoadLineOffsetVddC = 0; in fiji_populate_svi_load_line()
578 return 0; in fiji_populate_svi_load_line()
600 return 0; in fiji_populate_tdc_limit()
619 (uint8_t)((temp >> 16) & 0xff); in fiji_populate_dw8()
621 (uint8_t)((temp >> 8) & 0xff); in fiji_populate_dw8()
622 smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff); in fiji_populate_dw8()
624 return 0; in fiji_populate_dw8()
633 for (i = 0; i < 16; i++) in fiji_populate_temperature_scaler()
634 smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0; in fiji_populate_temperature_scaler()
636 return 0; in fiji_populate_temperature_scaler()
645 0 == hwmgr->thermal_controller.advanceFanControlParameters. in fiji_populate_fuzzy_fan()
654 return 0; in fiji_populate_fuzzy_fan()
663 for (i = 0; i < 16; i++) in fiji_populate_gnb_lpml()
664 smu_data->power_tune_table.GnbLPML[i] = 0; in fiji_populate_gnb_lpml()
666 return 0; in fiji_populate_gnb_lpml()
686 return 0; in fiji_populate_bapm_vddc_base_leakage_sidd()
721 if (0 != fiji_populate_temperature_scaler(hwmgr)) in fiji_populate_pm_fuses()
751 return 0; in fiji_populate_pm_fuses()
770 for (count = 0; count < lookup_table->count; count++) { in fiji_populate_cac_table()
779 return 0; in fiji_populate_cac_table()
788 PP_ASSERT_WITH_CODE(0 == result, in fiji_populate_smc_voltage_tables()
792 return 0; in fiji_populate_smc_voltage_tables()
798 int result = 0; in fiji_populate_ulv_level()
803 state->CcPwrDynRm = 0; in fiji_populate_ulv_level()
804 state->CcPwrDynRm1 = 0; in fiji_populate_ulv_level()
836 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in fiji_populate_smc_link_level()
842 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff); in fiji_populate_smc_link_level()
852 return 0; in fiji_populate_smc_link_level()
873 PP_ASSERT_WITH_CODE(result == 0, in fiji_calculate_sclk_params()
882 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in fiji_calculate_sclk_params()
933 return 0; in fiji_calculate_sclk_params()
958 PP_ASSERT_WITH_CODE((0 == result), in fiji_populate_single_graphic_level()
965 level->CcPwrDynRm = 0; in fiji_populate_single_graphic_level()
966 level->CcPwrDynRm1 = 0; in fiji_populate_single_graphic_level()
967 level->EnabledForActivity = 0; in fiji_populate_single_graphic_level()
971 level->VoltageDownHyst = 0; in fiji_populate_single_graphic_level()
972 level->PowerThrottle = 0; in fiji_populate_single_graphic_level()
996 return 0; in fiji_populate_single_graphic_level()
1009 int result = 0; in fiji_populate_all_graphic_levels()
1017 uint8_t hightest_pcie_level_enabled = 0, in fiji_populate_all_graphic_levels()
1018 lowest_pcie_level_enabled = 0, in fiji_populate_all_graphic_levels()
1019 mid_pcie_level_enabled = 0, in fiji_populate_all_graphic_levels()
1020 count = 0; in fiji_populate_all_graphic_levels()
1022 for (i = 0; i < dpm_table->sclk_table.count; i++) { in fiji_populate_all_graphic_levels()
1029 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */ in fiji_populate_all_graphic_levels()
1031 levels[i].DeepSleepDivId = 0; in fiji_populate_all_graphic_levels()
1034 /* Only enable level 0 for now.*/ in fiji_populate_all_graphic_levels()
1035 levels[0].EnabledForActivity = 1; in fiji_populate_all_graphic_levels()
1051 for (i = 0; i < dpm_table->sclk_table.count; i++) in fiji_populate_all_graphic_levels()
1057 (1 << (hightest_pcie_level_enabled + 1))) != 0)) in fiji_populate_all_graphic_levels()
1062 (1 << lowest_pcie_level_enabled)) == 0)) in fiji_populate_all_graphic_levels()
1067 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0)) in fiji_populate_all_graphic_levels()
1080 levels[0].pcieDpmLevel = lowest_pcie_level_enabled; in fiji_populate_all_graphic_levels()
1095 * SEQ_CG_RESP Bit[31:24] - 0x0
1097 * 0x0 <= 100MHz, 450 < 0x8 <= 500MHz
1098 * 100 < 0x1 <= 150MHz, 500 < 0x9 <= 550MHz
1099 * 150 < 0x2 <= 200MHz, 550 < 0xA <= 600MHz
1100 * 200 < 0x3 <= 250MHz, 600 < 0xB <= 650MHz
1101 * 250 < 0x4 <= 300MHz, 650 < 0xC <= 700MHz
1102 * 300 < 0x5 <= 350MHz, 700 < 0xD <= 750MHz
1103 * 350 < 0x6 <= 400MHz, 750 < 0xE <= 800MHz
1104 * 400 < 0x7 <= 450MHz, 800 < 0xF
1109 return 0x0; in fiji_get_mclk_frequency_ratio()
1111 return 0x1; in fiji_get_mclk_frequency_ratio()
1113 return 0x2; in fiji_get_mclk_frequency_ratio()
1115 return 0x3; in fiji_get_mclk_frequency_ratio()
1117 return 0x4; in fiji_get_mclk_frequency_ratio()
1119 return 0x5; in fiji_get_mclk_frequency_ratio()
1121 return 0x6; in fiji_get_mclk_frequency_ratio()
1123 return 0x7; in fiji_get_mclk_frequency_ratio()
1125 return 0x8; in fiji_get_mclk_frequency_ratio()
1127 return 0x9; in fiji_get_mclk_frequency_ratio()
1129 return 0xa; in fiji_get_mclk_frequency_ratio()
1131 return 0xb; in fiji_get_mclk_frequency_ratio()
1133 return 0xc; in fiji_get_mclk_frequency_ratio()
1135 return 0xd; in fiji_get_mclk_frequency_ratio()
1137 return 0xe; in fiji_get_mclk_frequency_ratio()
1139 return 0xf; in fiji_get_mclk_frequency_ratio()
1149 PP_ASSERT_WITH_CODE((0 == result), in fiji_calculate_mclk_params()
1167 int result = 0; in fiji_populate_single_memory_level()
1180 PP_ASSERT_WITH_CODE((0 == result), in fiji_populate_single_memory_level()
1186 mem_level->EnabledForActivity = 0; in fiji_populate_single_memory_level()
1189 mem_level->VoltageDownHyst = 0; in fiji_populate_single_memory_level()
1206 STUTTER_ENABLE) & 0x1)) in fiji_populate_single_memory_level()
1234 for (i = 0; i < dpm_table->mclk_table.count; i++) { in fiji_populate_all_memory_levels()
1235 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in fiji_populate_all_memory_levels()
1245 /* Only enable level 0 for now. */ in fiji_populate_all_memory_levels()
1246 levels[0].EnabledForActivity = 1; in fiji_populate_all_memory_levels()
1253 levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target; in fiji_populate_all_memory_levels()
1254 CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel); in fiji_populate_all_memory_levels()
1277 uint32_t i = 0; in fiji_populate_mvdd_value()
1281 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) { in fiji_populate_mvdd_value()
1293 return 0; in fiji_populate_mvdd_value()
1299 int result = 0; in fiji_populate_smc_acpi_level()
1316 data->dpm_table.sclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1321 PP_ASSERT_WITH_CODE((0 == result), in fiji_populate_smc_acpi_level()
1335 PP_ASSERT_WITH_CODE(result == 0, in fiji_populate_smc_acpi_level()
1341 table->ACPILevel.DeepSleepDivId = 0; in fiji_populate_smc_acpi_level()
1344 SPLL_PWRON, 0); in fiji_populate_smc_acpi_level()
1356 table->ACPILevel.CcPwrDynRm = 0; in fiji_populate_smc_acpi_level()
1357 table->ACPILevel.CcPwrDynRm1 = 0; in fiji_populate_smc_acpi_level()
1374 data->dpm_table.mclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1379 PP_ASSERT_WITH_CODE((0 == result), in fiji_populate_smc_acpi_level()
1389 us_mvdd = 0; in fiji_populate_smc_acpi_level()
1395 data->dpm_table.mclk_table.dpm_levels[0].value, in fiji_populate_smc_acpi_level()
1403 table->MemoryACPILevel.EnabledForThrottle = 0; in fiji_populate_smc_acpi_level()
1404 table->MemoryACPILevel.EnabledForActivity = 0; in fiji_populate_smc_acpi_level()
1405 table->MemoryACPILevel.UpHyst = 0; in fiji_populate_smc_acpi_level()
1407 table->MemoryACPILevel.VoltageDownHyst = 0; in fiji_populate_smc_acpi_level()
1430 table->VceBootLevel = 0; in fiji_populate_smc_vce_level()
1432 for (count = 0; count < table->VceLevelCount; count++) { in fiji_populate_smc_vce_level()
1434 table->VceLevel[count].MinVoltage = 0; in fiji_populate_smc_vce_level()
1445 PP_ASSERT_WITH_CODE((0 == result), in fiji_populate_smc_vce_level()
1469 table->AcpBootLevel = 0; in fiji_populate_smc_acp_level()
1471 for (count = 0; count < table->AcpLevelCount; count++) { in fiji_populate_smc_acp_level()
1482 PP_ASSERT_WITH_CODE((0 == result), in fiji_populate_smc_acp_level()
1505 PP_ASSERT_WITH_CODE(result == 0, in fiji_populate_memory_timing_parameters()
1521 return 0; in fiji_populate_memory_timing_parameters()
1530 int result = 0; in fiji_program_memory_timing_parameters()
1532 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in fiji_program_memory_timing_parameters()
1533 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in fiji_program_memory_timing_parameters()
1565 table->UvdBootLevel = 0; in fiji_populate_smc_uvd_level()
1567 for (count = 0; count < table->UvdLevelCount; count++) { in fiji_populate_smc_uvd_level()
1568 table->UvdLevel[count].MinVoltage = 0; in fiji_populate_smc_uvd_level()
1580 PP_ASSERT_WITH_CODE((0 == result), in fiji_populate_smc_uvd_level()
1587 PP_ASSERT_WITH_CODE((0 == result), in fiji_populate_smc_uvd_level()
1605 table->GraphicsBootLevel = 0; in fiji_populate_smc_boot_level()
1606 table->MemoryBootLevel = 0; in fiji_populate_smc_boot_level()
1628 return 0; in fiji_populate_smc_boot_level()
1640 for (level = 0; level < count; level++) { in fiji_populate_smc_initailial_state()
1649 for (level = 0; level < count; level++) { in fiji_populate_smc_initailial_state()
1657 return 0; in fiji_populate_smc_initailial_state()
1667 volt_offset = 0; in fiji_populate_clock_stretcher_data_table()
1682 efuse &= 0xFF000000; in fiji_populate_clock_stretcher_data_table()
1684 efuse2 &= 0xF; in fiji_populate_clock_stretcher_data_table()
1692 type = 0; in fiji_populate_clock_stretcher_data_table()
1700 for (i = 0; i < sclk_table->count; i++) { in fiji_populate_clock_stretcher_data_table()
1716 STRETCH_ENABLE, 0x0); in fiji_populate_clock_stretcher_data_table()
1718 masterReset, 0x1); in fiji_populate_clock_stretcher_data_table()
1720 staticEnable, 0x1); in fiji_populate_clock_stretcher_data_table()
1722 masterReset, 0x0); in fiji_populate_clock_stretcher_data_table()
1726 stretch_amount2 = 0; in fiji_populate_clock_stretcher_data_table()
1739 value &= 0xFFC2FF87; in fiji_populate_clock_stretcher_data_table()
1740 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq = in fiji_populate_clock_stretcher_data_table()
1741 fiji_clock_stretcher_lookup_table[stretch_amount2][0]; in fiji_populate_clock_stretcher_data_table()
1742 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq = in fiji_populate_clock_stretcher_data_table()
1747 if (fiji_clock_stretcher_lookup_table[stretch_amount2][0] < in fiji_populate_clock_stretcher_data_table()
1761 CKS_LOOKUPTableEntry[0].minFreq); in fiji_populate_clock_stretcher_data_table()
1763 CKS_LOOKUPTableEntry[0].maxFreq); in fiji_populate_clock_stretcher_data_table()
1764 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting = in fiji_populate_clock_stretcher_data_table()
1765 fiji_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F; in fiji_populate_clock_stretcher_data_table()
1766 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |= in fiji_populate_clock_stretcher_data_table()
1773 for (i = 0; i < 4; i++) { in fiji_populate_clock_stretcher_data_table()
1786 for (j = 0; j < smu_data->smc_state_table.GraphicsDpmLevelCount; j++) { in fiji_populate_clock_stretcher_data_table()
1787 cks_setting = 0; in fiji_populate_clock_stretcher_data_table()
1796 (fiji_clock_stretcher_ddt_table[type][i][0]) * 100) { in fiji_populate_clock_stretcher_data_table()
1797 cks_setting |= 0x2; in fiji_populate_clock_stretcher_data_table()
1800 cks_setting |= 0x1; in fiji_populate_clock_stretcher_data_table()
1811 value &= 0xFFFFFFFE; in fiji_populate_clock_stretcher_data_table()
1814 return 0; in fiji_populate_clock_stretcher_data_table()
1858 return 0; in fiji_populate_vr_config()
1881 tmp &= 0x00FFFFFF; in fiji_init_arb_table_index()
1891 int result = 0; in fiji_setup_dpm_led_config()
1892 u32 mask = 0; in fiji_setup_dpm_led_config()
1897 if (result == 0) { in fiji_setup_dpm_led_config()
1901 for (i = 0, j = 0; i < 32; i++) { in fiji_setup_dpm_led_config()
1915 return 0; in fiji_setup_dpm_led_config()
1934 table->SystemFlags = 0; in fiji_init_smc_table()
1949 PP_ASSERT_WITH_CODE(0 == result, in fiji_init_smc_table()
1952 ixCG_ULV_PARAMETER, 0x40035); in fiji_init_smc_table()
1956 PP_ASSERT_WITH_CODE(0 == result, in fiji_init_smc_table()
1960 PP_ASSERT_WITH_CODE(0 == result, in fiji_init_smc_table()
1964 PP_ASSERT_WITH_CODE(0 == result, in fiji_init_smc_table()
1968 PP_ASSERT_WITH_CODE(0 == result, in fiji_init_smc_table()
1972 PP_ASSERT_WITH_CODE(0 == result, in fiji_init_smc_table()
1976 PP_ASSERT_WITH_CODE(0 == result, in fiji_init_smc_table()
1984 PP_ASSERT_WITH_CODE(0 == result, in fiji_init_smc_table()
1988 PP_ASSERT_WITH_CODE(0 == result, in fiji_init_smc_table()
1992 PP_ASSERT_WITH_CODE(0 == result, in fiji_init_smc_table()
1996 PP_ASSERT_WITH_CODE(0 == result, in fiji_init_smc_table()
2000 PP_ASSERT_WITH_CODE(0 == result, in fiji_init_smc_table()
2006 PP_ASSERT_WITH_CODE(0 == result, in fiji_init_smc_table()
2024 table->VoltageResponseTime = 0; in fiji_init_smc_table()
2025 table->PhaseResponseTime = 0; in fiji_init_smc_table()
2027 table->PCIeBootLinkLevel = 0; /* 0:Gen1 1:Gen2 2:Gen3*/ in fiji_init_smc_table()
2029 table->VRConfig = 0; in fiji_init_smc_table()
2032 PP_ASSERT_WITH_CODE(0 == result, in fiji_init_smc_table()
2036 table->SclkStepSize = 0x4000; in fiji_init_smc_table()
2072 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) & in fiji_init_smc_table()
2073 (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0; in fiji_init_smc_table()
2090 for (i = 0; i < SMU73_MAX_ENTRIES_SMIO; i++) in fiji_init_smc_table()
2110 PP_ASSERT_WITH_CODE(0 == result, in fiji_init_smc_table()
2114 PP_ASSERT_WITH_CODE(0 == result, in fiji_init_smc_table()
2118 PP_ASSERT_WITH_CODE(0 == result, in fiji_init_smc_table()
2122 PP_ASSERT_WITH_CODE(0 == result, in fiji_init_smc_table()
2125 return 0; in fiji_init_smc_table()
2143 return 0; in fiji_thermal_setup_fan_table()
2146 if (smu_data->smu7_data.fan_table_start == 0) { in fiji_thermal_setup_fan_table()
2149 return 0; in fiji_thermal_setup_fan_table()
2155 if (duty100 == 0) { in fiji_thermal_setup_fan_table()
2158 return 0; in fiji_thermal_setup_fan_table()
2236 return 0; in fiji_thermal_setup_fan_table()
2243 return 0; in fiji_thermal_avfs_enable()
2247 return 0; in fiji_thermal_avfs_enable()
2258 return 0; in fiji_program_mem_timing_parameters()
2266 int result = 0; in fiji_update_sclk_threshold()
2267 uint32_t low_sclk_interrupt_threshold = 0; in fiji_update_sclk_threshold()
2271 && (data->low_sclk_interrupt_threshold != 0)) { in fiji_update_sclk_threshold()
2287 PP_ASSERT_WITH_CODE((result == 0), in fiji_update_sclk_threshold()
2336 return 0; in fiji_get_offsetof()
2361 return 0; in fiji_get_mac_definition()
2372 smu_data->smc_state_table.UvdBootLevel = 0; in fiji_update_uvd_smc_table()
2373 if (table_info->mm_dep_table->count > 0) in fiji_update_uvd_smc_table()
2382 mm_boot_level_value &= 0x00FFFFFF; in fiji_update_uvd_smc_table()
2395 return 0; in fiji_update_uvd_smc_table()
2410 smu_data->smc_state_table.VceBootLevel = 0; in fiji_update_vce_smc_table()
2418 mm_boot_level_value &= 0xFF00FFFF; in fiji_update_vce_smc_table()
2428 return 0; in fiji_update_vce_smc_table()
2443 return 0; in fiji_update_smc_table()
2459 if (0 == result) in fiji_process_firmware_header()
2462 error |= (0 != result); in fiji_process_firmware_header()
2474 error |= (0 != result); in fiji_process_firmware_header()
2492 error |= (0 != result); in fiji_process_firmware_header()
2502 error |= (0 != result); in fiji_process_firmware_header()
2512 error |= (0 != result); in fiji_process_firmware_header()
2514 return error ? -1 : 0; in fiji_process_firmware_header()
2538 return 0; in fiji_initialize_mc_reg_table()
2575 for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) { in fiji_update_dpm_settings()
2582 offset = clk_activity_offset & ~0x3; in fiji_update_dpm_settings()
2596 offset = up_hyst_offset & ~0x3; in fiji_update_dpm_settings()
2610 for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) { in fiji_update_dpm_settings()
2617 offset = clk_activity_offset & ~0x3; in fiji_update_dpm_settings()
2631 offset = up_hyst_offset & ~0x3; in fiji_update_dpm_settings()
2641 return 0; in fiji_update_dpm_settings()