Lines Matching refs:hwmgr
94 static int ci_set_smc_sram_address(struct pp_hwmgr *hwmgr, in ci_set_smc_sram_address() argument
103 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, smc_addr); in ci_set_smc_sram_address()
104 PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); in ci_set_smc_sram_address()
108 static int ci_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, in ci_copy_bytes_to_smc() argument
129 result = ci_set_smc_sram_address(hwmgr, addr, limit); in ci_copy_bytes_to_smc()
134 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data); in ci_copy_bytes_to_smc()
145 result = ci_set_smc_sram_address(hwmgr, addr, limit); in ci_copy_bytes_to_smc()
151 original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0); in ci_copy_bytes_to_smc()
165 result = ci_set_smc_sram_address(hwmgr, addr, limit); in ci_copy_bytes_to_smc()
170 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data); in ci_copy_bytes_to_smc()
177 static int ci_program_jump_on_start(struct pp_hwmgr *hwmgr) in ci_program_jump_on_start() argument
181 ci_copy_bytes_to_smc(hwmgr, 0x0, data, 4, sizeof(data)+1); in ci_program_jump_on_start()
186 static bool ci_is_smc_ram_running(struct pp_hwmgr *hwmgr) in ci_is_smc_ram_running() argument
188 return ((0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, in ci_is_smc_ram_running()
190 && (0x20100 <= cgs_read_ind_register(hwmgr->device, in ci_is_smc_ram_running()
194 static int ci_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, in ci_read_smc_sram_dword() argument
199 result = ci_set_smc_sram_address(hwmgr, smc_addr, limit); in ci_read_smc_sram_dword()
204 *value = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0); in ci_read_smc_sram_dword()
208 static int ci_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) in ci_send_msg_to_smc() argument
210 struct amdgpu_device *adev = hwmgr->adev; in ci_send_msg_to_smc()
213 cgs_write_register(hwmgr->device, mmSMC_RESP_0, 0); in ci_send_msg_to_smc()
214 cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg); in ci_send_msg_to_smc()
216 PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); in ci_send_msg_to_smc()
218 ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP); in ci_send_msg_to_smc()
227 static int ci_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, in ci_send_msg_to_smc_with_parameter() argument
230 cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter); in ci_send_msg_to_smc_with_parameter()
231 return ci_send_msg_to_smc(hwmgr, msg); in ci_send_msg_to_smc_with_parameter()
234 static void ci_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) in ci_initialize_power_tune_defaults() argument
236 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_initialize_power_tune_defaults()
237 struct amdgpu_device *adev = hwmgr->adev; in ci_initialize_power_tune_defaults()
277 static int ci_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, in ci_get_dependency_volt_by_clk() argument
297 static int ci_calculate_sclk_params(struct pp_hwmgr *hwmgr, in ci_calculate_sclk_params() argument
300 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_calculate_sclk_params()
313 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, ÷rs); in ci_calculate_sclk_params()
320 ref_clock = atomctrl_get_reference_clock(hwmgr); in ci_calculate_sclk_params()
340 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in ci_calculate_sclk_params()
345 if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr, in ci_calculate_sclk_params()
371 static void ci_populate_phase_value_based_on_sclk(struct pp_hwmgr *hwmgr, in ci_populate_phase_value_based_on_sclk() argument
408 static int ci_populate_single_graphic_level(struct pp_hwmgr *hwmgr, in ci_populate_single_graphic_level() argument
412 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_single_graphic_level()
415 result = ci_calculate_sclk_params(hwmgr, clock, level); in ci_populate_single_graphic_level()
418 result = ci_get_dependency_volt_by_clk(hwmgr, in ci_populate_single_graphic_level()
419 hwmgr->dyn_state.vddc_dependency_on_sclk, clock, in ci_populate_single_graphic_level()
430 ci_populate_phase_value_based_on_sclk(hwmgr, in ci_populate_single_graphic_level()
431 hwmgr->dyn_state.vddc_phase_shed_limits_table, in ci_populate_single_graphic_level()
447 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in ci_populate_single_graphic_level()
472 static int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) in ci_populate_all_graphic_levels() argument
474 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_all_graphic_levels()
475 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_all_graphic_levels()
487 result = ci_populate_single_graphic_level(hwmgr, in ci_populate_all_graphic_levels()
505 result = ci_copy_bytes_to_smc(hwmgr, array, in ci_populate_all_graphic_levels()
513 static int ci_populate_svi_load_line(struct pp_hwmgr *hwmgr) in ci_populate_svi_load_line() argument
515 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_svi_load_line()
526 static int ci_populate_tdc_limit(struct pp_hwmgr *hwmgr) in ci_populate_tdc_limit() argument
529 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_tdc_limit()
532 tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256); in ci_populate_tdc_limit()
542 static int ci_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) in ci_populate_dw8() argument
544 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_dw8()
548 if (ci_read_smc_sram_dword(hwmgr, in ci_populate_dw8()
561 static int ci_populate_fuzzy_fan(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) in ci_populate_fuzzy_fan() argument
564 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_fuzzy_fan()
566 if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15)) in ci_populate_fuzzy_fan()
567 || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity) in ci_populate_fuzzy_fan()
568 tmp = hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity; in ci_populate_fuzzy_fan()
570 tmp = hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity; in ci_populate_fuzzy_fan()
577 static int ci_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr) in ci_populate_bapm_vddc_vid_sidd() argument
580 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_bapm_vddc_vid_sidd()
585 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table, in ci_populate_bapm_vddc_vid_sidd()
587 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8, in ci_populate_bapm_vddc_vid_sidd()
589 …PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_… in ci_populate_bapm_vddc_vid_sidd()
592 for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) { in ci_populate_bapm_vddc_vid_sidd()
593 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EVV)) { in ci_populate_bapm_vddc_vid_sidd()
594 lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1); in ci_populate_bapm_vddc_vid_sidd()
595 hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2); in ci_populate_bapm_vddc_vid_sidd()
596 hi2_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc3); in ci_populate_bapm_vddc_vid_sidd()
598 lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc); in ci_populate_bapm_vddc_vid_sidd()
599 hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Leakage); in ci_populate_bapm_vddc_vid_sidd()
606 static int ci_populate_vddc_vid(struct pp_hwmgr *hwmgr) in ci_populate_vddc_vid() argument
609 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_vddc_vid()
611 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_vddc_vid()
623 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct pp_hwmgr *hwmgr) in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc() argument
625 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
655 static int ci_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) in ci_populate_bapm_vddc_base_leakage_sidd() argument
657 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_bapm_vddc_base_leakage_sidd()
660 struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table; in ci_populate_bapm_vddc_base_leakage_sidd()
673 static int ci_populate_pm_fuses(struct pp_hwmgr *hwmgr) in ci_populate_pm_fuses() argument
675 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_pm_fuses()
679 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in ci_populate_pm_fuses()
681 if (ci_read_smc_sram_dword(hwmgr, in ci_populate_pm_fuses()
690 ret = ci_populate_bapm_vddc_vid_sidd(hwmgr); in ci_populate_pm_fuses()
692 ret |= ci_populate_vddc_vid(hwmgr); in ci_populate_pm_fuses()
694 ret |= ci_populate_svi_load_line(hwmgr); in ci_populate_pm_fuses()
696 ret |= ci_populate_tdc_limit(hwmgr); in ci_populate_pm_fuses()
698 ret |= ci_populate_dw8(hwmgr, pm_fuse_table_offset); in ci_populate_pm_fuses()
700 ret |= ci_populate_fuzzy_fan(hwmgr, pm_fuse_table_offset); in ci_populate_pm_fuses()
702 ret |= ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(hwmgr); in ci_populate_pm_fuses()
704 ret |= ci_populate_bapm_vddc_base_leakage_sidd(hwmgr); in ci_populate_pm_fuses()
708 ret = ci_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset, in ci_populate_pm_fuses()
715 static int ci_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) in ci_populate_bapm_parameters_in_dpm_table() argument
717 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_bapm_parameters_in_dpm_table()
718 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_bapm_parameters_in_dpm_table()
721 struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table; in ci_populate_bapm_parameters_in_dpm_table()
722 struct phm_ppm_table *ppm = hwmgr->dyn_state.ppm_parameter_table; in ci_populate_bapm_parameters_in_dpm_table()
764 static int ci_get_std_voltage_value_sidd(struct pp_hwmgr *hwmgr, in ci_get_std_voltage_value_sidd() argument
773 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk, in ci_get_std_voltage_value_sidd()
777 if (NULL == hwmgr->dyn_state.cac_leakage_table) { in ci_get_std_voltage_value_sidd()
782 for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in ci_get_std_voltage_value_sidd()
783 if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { in ci_get_std_voltage_value_sidd()
785 if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) { in ci_get_std_voltage_value_sidd()
786 *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
787 *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage * VOLTAGE_SCALE); in ci_get_std_voltage_value_sidd()
790 …*lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].V… in ci_get_std_voltage_value_sidd()
791 …*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->c… in ci_get_std_voltage_value_sidd()
798 …for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in ci_get_std_voltage_value_sidd()
799 if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { in ci_get_std_voltage_value_sidd()
801 if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) { in ci_get_std_voltage_value_sidd()
802 *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
803 *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage) * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
806 …*lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].V… in ci_get_std_voltage_value_sidd()
807 …*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->c… in ci_get_std_voltage_value_sidd()
820 static int ci_populate_smc_voltage_table(struct pp_hwmgr *hwmgr, in ci_populate_smc_voltage_table() argument
826 result = ci_get_std_voltage_value_sidd(hwmgr, tab, in ci_populate_smc_voltage_table()
841 static int ci_populate_smc_vddc_table(struct pp_hwmgr *hwmgr, in ci_populate_smc_vddc_table() argument
846 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_smc_vddc_table()
850 result = ci_populate_smc_voltage_table(hwmgr, in ci_populate_smc_vddc_table()
870 static int ci_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr, in ci_populate_smc_vdd_ci_table() argument
873 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_smc_vdd_ci_table()
880 result = ci_populate_smc_voltage_table(hwmgr, in ci_populate_smc_vdd_ci_table()
898 static int ci_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr, in ci_populate_smc_mvdd_table() argument
901 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_smc_mvdd_table()
908 result = ci_populate_smc_voltage_table(hwmgr, in ci_populate_smc_mvdd_table()
927 static int ci_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr, in ci_populate_smc_voltage_tables() argument
932 result = ci_populate_smc_vddc_table(hwmgr, table); in ci_populate_smc_voltage_tables()
936 result = ci_populate_smc_vdd_ci_table(hwmgr, table); in ci_populate_smc_voltage_tables()
940 result = ci_populate_smc_mvdd_table(hwmgr, table); in ci_populate_smc_voltage_tables()
947 static int ci_populate_ulv_level(struct pp_hwmgr *hwmgr, in ci_populate_ulv_level() argument
952 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_ulv_level()
957 result = pp_tables_get_response_times(hwmgr, &voltage_response_time, &ulv_voltage); in ci_populate_ulv_level()
967 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in ci_populate_ulv_level()
971 …state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltag… in ci_populate_ulv_level()
974 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in ci_populate_ulv_level()
978 (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage) in ci_populate_ulv_level()
991 static int ci_populate_ulv_state(struct pp_hwmgr *hwmgr, in ci_populate_ulv_state() argument
994 return ci_populate_ulv_level(hwmgr, ulv_level); in ci_populate_ulv_state()
997 static int ci_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmTable *table) in ci_populate_smc_link_level() argument
999 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_smc_link_level()
1001 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_smc_link_level()
1024 struct pp_hwmgr *hwmgr, in ci_calculate_mclk_params() argument
1031 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_calculate_mclk_params()
1045 result = atomctrl_get_memory_pll_dividers_si(hwmgr, in ci_calculate_mclk_params()
1069 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in ci_calculate_mclk_params()
1074 uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr); in ci_calculate_mclk_params()
1086 if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) { in ci_calculate_mclk_params()
1157 static int ci_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_she… in ci_populate_phase_value_based_on_mclk() argument
1175 struct pp_hwmgr *hwmgr, in ci_populate_single_memory_level() argument
1180 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_single_memory_level()
1187 if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) { in ci_populate_single_memory_level()
1188 result = ci_get_dependency_volt_by_clk(hwmgr, in ci_populate_single_memory_level()
1189 hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc); in ci_populate_single_memory_level()
1194 if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) { in ci_populate_single_memory_level()
1195 result = ci_get_dependency_volt_by_clk(hwmgr, in ci_populate_single_memory_level()
1196 hwmgr->dyn_state.vddci_dependency_on_mclk, in ci_populate_single_memory_level()
1203 if (NULL != hwmgr->dyn_state.mvdd_dependency_on_mclk) { in ci_populate_single_memory_level()
1204 result = ci_get_dependency_volt_by_clk(hwmgr, in ci_populate_single_memory_level()
1205 hwmgr->dyn_state.mvdd_dependency_on_mclk, in ci_populate_single_memory_level()
1215 ci_populate_phase_value_based_on_mclk(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table, in ci_populate_single_memory_level()
1236 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in ci_populate_single_memory_level()
1237 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in ci_populate_single_memory_level()
1262 ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) in ci_populate_single_memory_level()
1263 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; in ci_populate_single_memory_level()
1265 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0; in ci_populate_single_memory_level()
1271 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; in ci_populate_single_memory_level()
1274 result = ci_calculate_mclk_params(hwmgr, in ci_populate_single_memory_level()
1300 static int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr) in ci_populate_all_memory_levels() argument
1302 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_all_memory_levels()
1303 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_all_memory_levels()
1306 struct amdgpu_device *adev = hwmgr->adev; in ci_populate_all_memory_levels()
1319 result = ci_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
1343 result = ci_copy_bytes_to_smc(hwmgr, in ci_populate_all_memory_levels()
1350 static int ci_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, in ci_populate_mvdd_value() argument
1353 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_mvdd_value()
1359 for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) { in ci_populate_mvdd_value()
1360 if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) { in ci_populate_mvdd_value()
1367 PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count, in ci_populate_mvdd_value()
1377 static int ci_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, in ci_populate_smc_acpi_level() argument
1381 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_smc_acpi_level()
1401 table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr); in ci_populate_smc_acpi_level()
1404 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, in ci_populate_smc_acpi_level()
1458 if (0 == ci_populate_mvdd_value(hwmgr, 0, &voltage_level)) in ci_populate_smc_acpi_level()
1518 static int ci_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, in ci_populate_smc_uvd_level() argument
1525 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; in ci_populate_smc_uvd_level()
1538 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, in ci_populate_smc_uvd_level()
1545 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, in ci_populate_smc_uvd_level()
1559 static int ci_populate_smc_vce_level(struct pp_hwmgr *hwmgr, in ci_populate_smc_vce_level() argument
1566 hwmgr->dyn_state.vce_clock_voltage_dependency_table; in ci_populate_smc_vce_level()
1577 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, in ci_populate_smc_vce_level()
1591 static int ci_populate_smc_acp_level(struct pp_hwmgr *hwmgr, in ci_populate_smc_acp_level() argument
1598 hwmgr->dyn_state.acp_clock_voltage_dependency_table; in ci_populate_smc_acp_level()
1608 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, in ci_populate_smc_acp_level()
1622 struct pp_hwmgr *hwmgr, in ci_populate_memory_timing_parameters() argument
1633 result = atomctrl_set_engine_dram_timings_rv770(hwmgr, in ci_populate_memory_timing_parameters()
1639 dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); in ci_populate_memory_timing_parameters()
1640 dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); in ci_populate_memory_timing_parameters()
1641 burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); in ci_populate_memory_timing_parameters()
1650 static int ci_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) in ci_program_memory_timing_parameters() argument
1652 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_program_memory_timing_parameters()
1653 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_program_memory_timing_parameters()
1663 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in ci_program_memory_timing_parameters()
1674 hwmgr, in ci_program_memory_timing_parameters()
1685 static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr, in ci_populate_smc_boot_level() argument
1689 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_smc_boot_level()
1690 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_smc_boot_level()
1723 static int ci_populate_mc_reg_address(struct pp_hwmgr *hwmgr, in ci_populate_mc_reg_address() argument
1726 const struct ci_smumgr *smu_data = (struct ci_smumgr *)hwmgr->smu_backend; in ci_populate_mc_reg_address()
1763 struct pp_hwmgr *hwmgr, in ci_convert_mc_reg_table_entry_to_smc() argument
1768 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_convert_mc_reg_table_entry_to_smc()
1788 static int ci_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, in ci_convert_mc_reg_table_to_smc() argument
1792 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_convert_mc_reg_table_to_smc()
1798 hwmgr, in ci_convert_mc_reg_table_to_smc()
1810 static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) in ci_update_and_upload_mc_reg_table() argument
1812 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_update_and_upload_mc_reg_table()
1813 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_update_and_upload_mc_reg_table()
1823 result = ci_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs)); in ci_update_and_upload_mc_reg_table()
1830 return ci_copy_bytes_to_smc(hwmgr, address, in ci_update_and_upload_mc_reg_table()
1836 static int ci_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) in ci_populate_initial_mc_reg_table() argument
1839 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_initial_mc_reg_table()
1842 result = ci_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs)); in ci_populate_initial_mc_reg_table()
1846 result = ci_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs); in ci_populate_initial_mc_reg_table()
1850 return ci_copy_bytes_to_smc(hwmgr, smu_data->mc_reg_table_start, in ci_populate_initial_mc_reg_table()
1854 static int ci_populate_smc_initial_state(struct pp_hwmgr *hwmgr) in ci_populate_smc_initial_state() argument
1856 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_smc_initial_state()
1857 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_smc_initial_state()
1860 count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count); in ci_populate_smc_initial_state()
1863 if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[level].clk in ci_populate_smc_initial_state()
1870 count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count); in ci_populate_smc_initial_state()
1873 if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk in ci_populate_smc_initial_state()
1883 static int ci_populate_smc_svi2_config(struct pp_hwmgr *hwmgr, in ci_populate_smc_svi2_config() argument
1886 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_smc_svi2_config()
1895 static int ci_start_smc(struct pp_hwmgr *hwmgr) in ci_start_smc() argument
1898 ci_program_jump_on_start(hwmgr); in ci_start_smc()
1901 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); in ci_start_smc()
1903 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0); in ci_start_smc()
1905 PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, in ci_start_smc()
1911 static int ci_populate_vr_config(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmTable *table) in ci_populate_vr_config() argument
1913 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_vr_config()
1942 static int ci_init_smc_table(struct pp_hwmgr *hwmgr) in ci_init_smc_table() argument
1945 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_init_smc_table()
1946 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_init_smc_table()
1951 ci_initialize_power_tune_defaults(hwmgr); in ci_init_smc_table()
1955 ci_populate_smc_voltage_tables(hwmgr, table); in ci_init_smc_table()
1957 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in ci_init_smc_table()
1962 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in ci_init_smc_table()
1970 result = ci_populate_ulv_state(hwmgr, &(table->Ulv)); in ci_init_smc_table()
1974 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in ci_init_smc_table()
1978 result = ci_populate_all_graphic_levels(hwmgr); in ci_init_smc_table()
1982 result = ci_populate_all_memory_levels(hwmgr); in ci_init_smc_table()
1986 result = ci_populate_smc_link_level(hwmgr, table); in ci_init_smc_table()
1990 result = ci_populate_smc_acpi_level(hwmgr, table); in ci_init_smc_table()
1994 result = ci_populate_smc_vce_level(hwmgr, table); in ci_init_smc_table()
1998 result = ci_populate_smc_acp_level(hwmgr, table); in ci_init_smc_table()
2004 result = ci_program_memory_timing_parameters(hwmgr); in ci_init_smc_table()
2008 result = ci_populate_smc_uvd_level(hwmgr, table); in ci_init_smc_table()
2020 result = ci_populate_smc_boot_level(hwmgr, table); in ci_init_smc_table()
2024 result = ci_populate_smc_initial_state(hwmgr); in ci_init_smc_table()
2027 result = ci_populate_bapm_parameters_in_dpm_table(hwmgr); in ci_init_smc_table()
2061 result = ci_populate_vr_config(hwmgr, table); in ci_init_smc_table()
2066 ci_populate_smc_svi2_config(hwmgr, table); in ci_init_smc_table()
2073 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) { in ci_init_smc_table()
2075 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in ci_init_smc_table()
2079 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in ci_init_smc_table()
2103 result = ci_copy_bytes_to_smc(hwmgr, smu_data->dpm_table_start + in ci_init_smc_table()
2112 result = ci_populate_initial_mc_reg_table(hwmgr); in ci_init_smc_table()
2116 result = ci_populate_pm_fuses(hwmgr); in ci_init_smc_table()
2120 ci_start_smc(hwmgr); in ci_init_smc_table()
2125 static int ci_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) in ci_thermal_setup_fan_table() argument
2127 struct ci_smumgr *ci_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_thermal_setup_fan_table()
2136 …if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl… in ci_thermal_setup_fan_table()
2139 if (hwmgr->thermal_controller.fanInfo.bNoFan) { in ci_thermal_setup_fan_table()
2140 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in ci_thermal_setup_fan_table()
2146 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl); in ci_thermal_setup_fan_table()
2150 …duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100… in ci_thermal_setup_fan_table()
2153 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl); in ci_thermal_setup_fan_table()
2157 tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100; in ci_thermal_setup_fan_table()
2161 …t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed - hwmgr->thermal_controller… in ci_thermal_setup_fan_table()
2162 …t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - hwmgr->thermal_controlle… in ci_thermal_setup_fan_table()
2164 …pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - hwmgr->thermal_contro… in ci_thermal_setup_fan_table()
2165 …pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - hwmgr->thermal_contr… in ci_thermal_setup_fan_table()
2170 …fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin… in ci_thermal_setup_fan_table()
2171 …fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed… in ci_thermal_setup_fan_table()
2172 …fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax… in ci_thermal_setup_fan_table()
2179 fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst); in ci_thermal_setup_fan_table()
2187 reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); in ci_thermal_setup_fan_table()
2189 …fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCyc… in ci_thermal_setup_fan_table()
2193 …fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT… in ci_thermal_setup_fan_table()
2195 …res = ci_copy_bytes_to_smc(hwmgr, ci_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeo… in ci_thermal_setup_fan_table()
2200 static int ci_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) in ci_program_mem_timing_parameters() argument
2202 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_program_mem_timing_parameters()
2206 return ci_program_memory_timing_parameters(hwmgr); in ci_program_mem_timing_parameters()
2211 static int ci_update_sclk_threshold(struct pp_hwmgr *hwmgr) in ci_update_sclk_threshold() argument
2213 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_update_sclk_threshold()
2214 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_update_sclk_threshold()
2219 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in ci_update_sclk_threshold()
2228 hwmgr, in ci_update_sclk_threshold()
2237 result = ci_update_and_upload_mc_reg_table(hwmgr); in ci_update_sclk_threshold()
2241 result = ci_program_mem_timing_parameters(hwmgr); in ci_update_sclk_threshold()
2313 static int ci_load_smc_ucode(struct pp_hwmgr *hwmgr) in ci_load_smc_ucode() argument
2321 cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info); in ci_load_smc_ucode()
2323 hwmgr->is_kicker = info.is_kicker; in ci_load_smc_ucode()
2324 hwmgr->smu_version = info.version; in ci_load_smc_ucode()
2334 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr); in ci_load_smc_ucode()
2335 PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1); in ci_load_smc_ucode()
2339 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data); in ci_load_smc_ucode()
2342 PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); in ci_load_smc_ucode()
2352 static int ci_upload_firmware(struct pp_hwmgr *hwmgr) in ci_upload_firmware() argument
2354 if (ci_is_smc_ram_running(hwmgr)) { in ci_upload_firmware()
2358 PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, in ci_upload_firmware()
2360 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_MISC_CNTL, in ci_upload_firmware()
2363 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1); in ci_upload_firmware()
2364 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1); in ci_upload_firmware()
2365 return ci_load_smc_ucode(hwmgr); in ci_upload_firmware()
2368 static int ci_process_firmware_header(struct pp_hwmgr *hwmgr) in ci_process_firmware_header() argument
2370 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_process_firmware_header()
2371 struct ci_smumgr *ci_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_process_firmware_header()
2377 if (ci_upload_firmware(hwmgr)) in ci_process_firmware_header()
2380 result = ci_read_smc_sram_dword(hwmgr, in ci_process_firmware_header()
2390 result = ci_read_smc_sram_dword(hwmgr, in ci_process_firmware_header()
2402 result = ci_read_smc_sram_dword(hwmgr, in ci_process_firmware_header()
2410 result = ci_read_smc_sram_dword(hwmgr, in ci_process_firmware_header()
2420 result = ci_read_smc_sram_dword(hwmgr, in ci_process_firmware_header()
2430 result = ci_read_smc_sram_dword(hwmgr, in ci_process_firmware_header()
2436 hwmgr->microcode_version_info.SMC = tmp; in ci_process_firmware_header()
2443 static uint8_t ci_get_memory_modile_index(struct pp_hwmgr *hwmgr) in ci_get_memory_modile_index() argument
2445 return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16)); in ci_get_memory_modile_index()
2583 static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr, in ci_set_mc_special_registers() argument
2588 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_set_mc_special_registers()
2597 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS); in ci_set_mc_special_registers()
2609 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS); in ci_set_mc_special_registers()
2637 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1); in ci_set_mc_special_registers()
2676 static int ci_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) in ci_initialize_mc_reg_table() argument
2679 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_initialize_mc_reg_table()
2682 uint8_t module_index = ci_get_memory_modile_index(hwmgr); in ci_initialize_mc_reg_table()
2690 …cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SE… in ci_initialize_mc_reg_table()
2691 …cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SE… in ci_initialize_mc_reg_table()
2692 …cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_… in ci_initialize_mc_reg_table()
2693 …cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SE… in ci_initialize_mc_reg_table()
2694 …cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SE… in ci_initialize_mc_reg_table()
2695 …cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SE… in ci_initialize_mc_reg_table()
2696 …cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_S… in ci_initialize_mc_reg_table()
2697 …cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_S… in ci_initialize_mc_reg_table()
2698 …cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_S… in ci_initialize_mc_reg_table()
2699 …cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_… in ci_initialize_mc_reg_table()
2700 …cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_… in ci_initialize_mc_reg_table()
2701 …cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_P… in ci_initialize_mc_reg_table()
2702 …cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_… in ci_initialize_mc_reg_table()
2703 …cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ… in ci_initialize_mc_reg_table()
2704 …cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ… in ci_initialize_mc_reg_table()
2705 …cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ… in ci_initialize_mc_reg_table()
2706 …cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ… in ci_initialize_mc_reg_table()
2707 …cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SE… in ci_initialize_mc_reg_table()
2708 …cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_… in ci_initialize_mc_reg_table()
2709 …cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_… in ci_initialize_mc_reg_table()
2711 result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table); in ci_initialize_mc_reg_table()
2718 result = ci_set_mc_special_registers(hwmgr, ni_table); in ci_initialize_mc_reg_table()
2729 static bool ci_is_dpm_running(struct pp_hwmgr *hwmgr) in ci_is_dpm_running() argument
2731 return ci_is_smc_ram_running(hwmgr); in ci_is_dpm_running()
2734 static int ci_smu_init(struct pp_hwmgr *hwmgr) in ci_smu_init() argument
2743 hwmgr->smu_backend = ci_priv; in ci_smu_init()
2748 static int ci_smu_fini(struct pp_hwmgr *hwmgr) in ci_smu_fini() argument
2750 kfree(hwmgr->smu_backend); in ci_smu_fini()
2751 hwmgr->smu_backend = NULL; in ci_smu_fini()
2755 static int ci_start_smu(struct pp_hwmgr *hwmgr) in ci_start_smu() argument
2760 static int ci_update_dpm_settings(struct pp_hwmgr *hwmgr, in ci_update_dpm_settings() argument
2763 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_update_dpm_settings()
2765 (hwmgr->smu_backend); in ci_update_dpm_settings()
2786 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel, NULL); in ci_update_dpm_settings()
2795 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in ci_update_dpm_settings()
2797 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); in ci_update_dpm_settings()
2809 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in ci_update_dpm_settings()
2812 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); in ci_update_dpm_settings()
2816 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel, NULL); in ci_update_dpm_settings()
2821 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel, NULL); in ci_update_dpm_settings()
2830 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in ci_update_dpm_settings()
2832 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); in ci_update_dpm_settings()
2844 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in ci_update_dpm_settings()
2847 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); in ci_update_dpm_settings()
2851 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel, NULL); in ci_update_dpm_settings()
2856 static int ci_update_uvd_smc_table(struct pp_hwmgr *hwmgr) in ci_update_uvd_smc_table() argument
2858 struct amdgpu_device *adev = hwmgr->adev; in ci_update_uvd_smc_table()
2859 struct smu7_hwmgr *data = hwmgr->backend; in ci_update_uvd_smc_table()
2860 struct ci_smumgr *smu_data = hwmgr->smu_backend; in ci_update_uvd_smc_table()
2862 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; in ci_update_uvd_smc_table()
2867 uint32_t max_vddc = adev->pm.ac_power ? hwmgr->dyn_state.max_clock_voltage_on_ac.vddc : in ci_update_uvd_smc_table()
2868 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc; in ci_update_uvd_smc_table()
2876 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, DPM_TABLE_475, in ci_update_uvd_smc_table()
2884 if (hwmgr->dpm_level & profile_mode_mask || !PP_CAP(PHM_PlatformCaps_UVDDPM)) in ci_update_uvd_smc_table()
2887 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_UVDDPM_SetEnabledMask, in ci_update_uvd_smc_table()
2894 static int ci_update_vce_smc_table(struct pp_hwmgr *hwmgr) in ci_update_vce_smc_table() argument
2896 struct amdgpu_device *adev = hwmgr->adev; in ci_update_vce_smc_table()
2897 struct smu7_hwmgr *data = hwmgr->backend; in ci_update_vce_smc_table()
2899 hwmgr->dyn_state.vce_clock_voltage_dependency_table; in ci_update_vce_smc_table()
2904 uint32_t max_vddc = adev->pm.ac_power ? hwmgr->dyn_state.max_clock_voltage_on_ac.vddc : in ci_update_vce_smc_table()
2905 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc; in ci_update_vce_smc_table()
2908 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, DPM_TABLE_475, in ci_update_vce_smc_table()
2916 if (hwmgr->dpm_level & profile_mode_mask || !PP_CAP(PHM_PlatformCaps_VCEDPM)) in ci_update_vce_smc_table()
2919 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_VCEDPM_SetEnabledMask, in ci_update_vce_smc_table()
2926 static int ci_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) in ci_update_smc_table() argument
2930 ci_update_uvd_smc_table(hwmgr); in ci_update_smc_table()
2933 ci_update_vce_smc_table(hwmgr); in ci_update_smc_table()
2941 static void ci_reset_smc(struct pp_hwmgr *hwmgr) in ci_reset_smc() argument
2943 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in ci_reset_smc()
2949 static void ci_stop_smc_clock(struct pp_hwmgr *hwmgr) in ci_stop_smc_clock() argument
2951 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in ci_stop_smc_clock()
2956 static int ci_stop_smc(struct pp_hwmgr *hwmgr) in ci_stop_smc() argument
2958 ci_reset_smc(hwmgr); in ci_stop_smc()
2959 ci_stop_smc_clock(hwmgr); in ci_stop_smc()