Lines Matching +full:0 +full:x255
58 #define MC_CG_ARB_FREQ_F0 0x0a
59 #define MC_CG_ARB_FREQ_F1 0x0b
60 #define MC_CG_ARB_FREQ_F2 0x0c
61 #define MC_CG_ARB_FREQ_F3 0x0d
63 #define SMC_RAM_END 0x40000
69 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
70 …{ 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD,…
71 …{ 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9…
75 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
76 …{ 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD,…
77 …{ 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9…
81 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
82 …{ 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D,…
83 …{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5…
88 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
89 …{ 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D,…
90 …{ 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9…
97 if ((0 != (3 & smc_addr)) in ci_set_smc_sram_address()
104 PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); in ci_set_smc_sram_address()
105 return 0; in ci_set_smc_sram_address()
112 uint32_t data = 0; in ci_copy_bytes_to_smc()
114 uint32_t addr = 0; in ci_copy_bytes_to_smc()
127 data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3]; in ci_copy_bytes_to_smc()
131 if (0 != result) in ci_copy_bytes_to_smc()
141 if (0 != byte_count) { in ci_copy_bytes_to_smc()
143 data = 0; in ci_copy_bytes_to_smc()
147 if (0 != result) in ci_copy_bytes_to_smc()
155 while (byte_count > 0) { in ci_copy_bytes_to_smc()
157 data = (0x100 * data) + *src++; in ci_copy_bytes_to_smc()
163 data |= (original_data & ~((~0UL) << extra_shift)); in ci_copy_bytes_to_smc()
167 if (0 != result) in ci_copy_bytes_to_smc()
173 return 0; in ci_copy_bytes_to_smc()
179 static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 }; in ci_program_jump_on_start()
181 ci_copy_bytes_to_smc(hwmgr, 0x0, data, 4, sizeof(data)+1); in ci_program_jump_on_start()
183 return 0; in ci_program_jump_on_start()
188 return ((0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, in ci_is_smc_ram_running()
190 && (0x20100 <= cgs_read_ind_register(hwmgr->device, in ci_is_smc_ram_running()
205 return 0; in ci_read_smc_sram_dword()
213 cgs_write_register(hwmgr->device, mmSMC_RESP_0, 0); in ci_send_msg_to_smc()
216 PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); in ci_send_msg_to_smc()
224 return 0; in ci_send_msg_to_smc()
243 case 0x67BA: in ci_initialize_power_tune_defaults()
244 case 0x67B1: in ci_initialize_power_tune_defaults()
247 case 0x67B8: in ci_initialize_power_tune_defaults()
248 case 0x66B0: in ci_initialize_power_tune_defaults()
251 case 0x6640: in ci_initialize_power_tune_defaults()
252 case 0x6641: in ci_initialize_power_tune_defaults()
253 case 0x6646: in ci_initialize_power_tune_defaults()
254 case 0x6647: in ci_initialize_power_tune_defaults()
257 case 0x6649: in ci_initialize_power_tune_defaults()
258 case 0x6650: in ci_initialize_power_tune_defaults()
259 case 0x6651: in ci_initialize_power_tune_defaults()
260 case 0x6658: in ci_initialize_power_tune_defaults()
261 case 0x665C: in ci_initialize_power_tune_defaults()
262 case 0x665D: in ci_initialize_power_tune_defaults()
263 case 0x67A0: in ci_initialize_power_tune_defaults()
264 case 0x67A1: in ci_initialize_power_tune_defaults()
265 case 0x67A2: in ci_initialize_power_tune_defaults()
266 case 0x67A8: in ci_initialize_power_tune_defaults()
267 case 0x67A9: in ci_initialize_power_tune_defaults()
268 case 0x67AA: in ci_initialize_power_tune_defaults()
269 case 0x67B9: in ci_initialize_power_tune_defaults()
270 case 0x67BE: in ci_initialize_power_tune_defaults()
281 uint32_t i = 0; in ci_get_dependency_volt_by_clk()
283 if (allowed_clock_voltage_table->count == 0) in ci_get_dependency_volt_by_clk()
286 for (i = 0; i < allowed_clock_voltage_table->count; i++) { in ci_get_dependency_volt_by_clk()
289 return 0; in ci_get_dependency_volt_by_clk()
294 return 0; in ci_get_dependency_volt_by_clk()
315 PP_ASSERT_WITH_CODE(result == 0, in ci_calculate_sclk_params()
324 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in ci_calculate_sclk_params()
368 return 0; in ci_calculate_sclk_params()
380 for (i = 0; i < pl->count; i++) { in ci_populate_phase_value_based_on_sclk()
397 return 0; in ci_get_sleep_divider_id_from_clock()
402 if (temp >= min || i == 0) in ci_get_sleep_divider_id_from_clock()
436 level->CcPwrDynRm = 0; in ci_populate_single_graphic_level()
437 level->CcPwrDynRm1 = 0; in ci_populate_single_graphic_level()
438 level->EnabledForActivity = 0; in ci_populate_single_graphic_level()
443 level->VoltageDownH = 0; in ci_populate_single_graphic_level()
444 level->PowerThrottle = 0; in ci_populate_single_graphic_level()
456 if (0 == result) { in ci_populate_single_graphic_level()
477 int result = 0; in ci_populate_all_graphic_levels()
486 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
493 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()
499 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()
521 smu_data->power_tune_table.SviLoadLineOffsetVddC = 0; in ci_populate_svi_load_line()
523 return 0; in ci_populate_svi_load_line()
539 return 0; in ci_populate_tdc_limit()
558 return 0; in ci_populate_dw8()
567 || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity) in ci_populate_fuzzy_fan()
574 return 0; in ci_populate_fuzzy_fan()
592 for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) { in ci_populate_bapm_vddc_vid_sidd()
603 return 0; in ci_populate_bapm_vddc_vid_sidd()
617 for (i = 0; i < (int)data->vddc_voltage_table.count; i++) in ci_populate_vddc_vid()
620 return 0; in ci_populate_vddc_vid()
630 min = max = hi_vid[0]; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
631 for (i = 0; i < 8; i++) { in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
632 if (0 != hi_vid[i]) { in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
639 if (0 != lo_vid[i]) { in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
647 if ((min == 0) || (max == 0)) in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
652 return 0; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
670 return 0; in ci_populate_bapm_vddc_base_leakage_sidd()
677 int ret = 0; in ci_populate_pm_fuses()
729 dpm_table->DTETjOffset = 0; in ci_populate_bapm_parameters_in_dpm_table()
739 dpm_table->PPM_PkgPwrLimit = 0; in ci_populate_bapm_parameters_in_dpm_table()
740 dpm_table->PPM_TemperatureLimit = 0; in ci_populate_bapm_parameters_in_dpm_table()
750 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) { in ci_populate_bapm_parameters_in_dpm_table()
751 for (j = 0; j < SMU7_DTE_SOURCES; j++) { in ci_populate_bapm_parameters_in_dpm_table()
752 for (k = 0; k < SMU7_DTE_SINKS; k++) { in ci_populate_bapm_parameters_in_dpm_table()
761 return 0; in ci_populate_bapm_parameters_in_dpm_table()
779 return 0; in ci_get_std_voltage_value_sidd()
782 for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in ci_get_std_voltage_value_sidd()
798 …for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in ci_get_std_voltage_value_sidd()
817 return 0; in ci_get_std_voltage_value_sidd()
838 return 0; in ci_populate_smc_voltage_table()
849 for (count = 0; count < table->VddcLevelCount; count++) { in ci_populate_smc_vddc_table()
853 PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL); in ci_populate_smc_vddc_table()
861 table->VddcLevel[count].Smio = 0; in ci_populate_smc_vddc_table()
867 return 0; in ci_populate_smc_vddc_table()
879 for (count = 0; count < table->VddciLevelCount; count++) { in ci_populate_smc_vdd_ci_table()
883 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL); in ci_populate_smc_vdd_ci_table()
889 table->VddciLevel[count].Smio = 0; in ci_populate_smc_vdd_ci_table()
895 return 0; in ci_populate_smc_vdd_ci_table()
907 for (count = 0; count < table->MvddLevelCount; count++) { in ci_populate_smc_mvdd_table()
911 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL); in ci_populate_smc_mvdd_table()
917 table->MvddLevel[count].Smio = 0; in ci_populate_smc_mvdd_table()
923 return 0; in ci_populate_smc_mvdd_table()
933 PP_ASSERT_WITH_CODE(0 == result, in ci_populate_smc_voltage_tables()
937 PP_ASSERT_WITH_CODE(0 == result, in ci_populate_smc_voltage_tables()
941 PP_ASSERT_WITH_CODE(0 == result, in ci_populate_smc_voltage_tables()
944 return 0; in ci_populate_smc_voltage_tables()
954 state->CcPwrDynRm = 0; in ci_populate_ulv_level()
955 state->CcPwrDynRm1 = 0; in ci_populate_ulv_level()
958 PP_ASSERT_WITH_CODE((0 == result), "can not get ULV voltage value", return result;); in ci_populate_ulv_level()
960 if (ulv_voltage == 0) { in ci_populate_ulv_level()
962 return 0; in ci_populate_ulv_level()
967 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in ci_populate_ulv_level()
968 state->VddcOffset = 0; in ci_populate_ulv_level()
971 …state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltag… in ci_populate_ulv_level()
974 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in ci_populate_ulv_level()
975 state->VddcOffsetVid = 0; in ci_populate_ulv_level()
978 (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage) in ci_populate_ulv_level()
988 return 0; in ci_populate_ulv_level()
1005 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in ci_populate_smc_link_level()
1020 return 0; in ci_populate_smc_link_level()
1047 PP_ASSERT_WITH_CODE(0 == result, in ci_calculate_mclk_params()
1086 if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) { in ci_calculate_mclk_params()
1116 return 0; in ci_calculate_mclk_params()
1126 mc_para_index = 0x00; in ci_get_mclk_frequency_ratio()
1128 mc_para_index = 0x0f; in ci_get_mclk_frequency_ratio()
1133 mc_para_index = 0x00; in ci_get_mclk_frequency_ratio()
1135 mc_para_index = 0x0f; in ci_get_mclk_frequency_ratio()
1148 mc_para_index = 0; in ci_get_ddr3_mclk_frequency_ratio()
1150 mc_para_index = 0x0f; in ci_get_ddr3_mclk_frequency_ratio()
1164 for (i = 0; i < pl->count; i++) { in ci_populate_phase_value_based_on_mclk()
1171 return 0; in ci_populate_phase_value_based_on_mclk()
1181 int result = 0; in ci_populate_single_memory_level()
1190 PP_ASSERT_WITH_CODE((0 == result), in ci_populate_single_memory_level()
1199 PP_ASSERT_WITH_CODE((0 == result), in ci_populate_single_memory_level()
1208 PP_ASSERT_WITH_CODE((0 == result), in ci_populate_single_memory_level()
1223 memory_level->VoltageDownH = 0; in ci_populate_single_memory_level()
1227 memory_level->StutterEnable = 0; in ci_populate_single_memory_level()
1228 memory_level->StrobeEnable = 0; in ci_populate_single_memory_level()
1229 memory_level->EdcReadEnable = 0; in ci_populate_single_memory_level()
1230 memory_level->EdcWriteEnable = 0; in ci_populate_single_memory_level()
1231 memory_level->RttEnable = 0; in ci_populate_single_memory_level()
1242 memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) && in ci_populate_single_memory_level()
1250 if ((mclk_edc_enable_threshold != 0) && in ci_populate_single_memory_level()
1255 if ((mclk_edc_wr_enable_threshold != 0) && in ci_populate_single_memory_level()
1262 ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) in ci_populate_single_memory_level()
1263 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; in ci_populate_single_memory_level()
1265 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0; in ci_populate_single_memory_level()
1271 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; in ci_populate_single_memory_level()
1277 if (0 == result) { in ci_populate_single_memory_level()
1314 memset(levels, 0x00, level_array_size); in ci_populate_all_memory_levels()
1316 for (i = 0; i < dpm_table->mclk_table.count; i++) { in ci_populate_all_memory_levels()
1317 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in ci_populate_all_memory_levels()
1321 if (0 != result) in ci_populate_all_memory_levels()
1325 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in ci_populate_all_memory_levels()
1330 && ((dev_id == 0x67B0) || (dev_id == 0x67B1))) { in ci_populate_all_memory_levels()
1332 smu_data->smc_state_table.MemoryLevel[0].MinVddci; in ci_populate_all_memory_levels()
1334 smu_data->smc_state_table.MemoryLevel[0].MinMvdd; in ci_populate_all_memory_levels()
1336 smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; in ci_populate_all_memory_levels()
1337 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel); in ci_populate_all_memory_levels()
1355 uint32_t i = 0; in ci_populate_mvdd_value()
1359 for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) { in ci_populate_mvdd_value()
1374 return 0; in ci_populate_mvdd_value()
1380 int result = 0; in ci_populate_smc_acpi_level()
1399 table->ACPILevel.MinVddcPhases = data->vddc_phase_shed_control ? 0 : 1; in ci_populate_smc_acpi_level()
1407 PP_ASSERT_WITH_CODE(result == 0, in ci_populate_smc_acpi_level()
1413 table->ACPILevel.DeepSleepDivId = 0; in ci_populate_smc_acpi_level()
1416 CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0); in ci_populate_smc_acpi_level()
1428 table->ACPILevel.CcPwrDynRm = 0; in ci_populate_smc_acpi_level()
1429 table->ACPILevel.CcPwrDynRm1 = 0; in ci_populate_smc_acpi_level()
1452 if (data->acpi_vddci != 0) in ci_populate_smc_acpi_level()
1458 if (0 == ci_populate_mvdd_value(hwmgr, 0, &voltage_level)) in ci_populate_smc_acpi_level()
1462 table->MemoryACPILevel.MinMvdd = 0; in ci_populate_smc_acpi_level()
1466 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1); in ci_populate_smc_acpi_level()
1468 MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1); in ci_populate_smc_acpi_level()
1472 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0); in ci_populate_smc_acpi_level()
1474 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0); in ci_populate_smc_acpi_level()
1478 DLL_CNTL, MRDCK0_BYPASS, 0); in ci_populate_smc_acpi_level()
1480 DLL_CNTL, MRDCK1_BYPASS, 0); in ci_populate_smc_acpi_level()
1501 table->MemoryACPILevel.EnabledForThrottle = 0; in ci_populate_smc_acpi_level()
1502 table->MemoryACPILevel.EnabledForActivity = 0; in ci_populate_smc_acpi_level()
1503 table->MemoryACPILevel.UpH = 0; in ci_populate_smc_acpi_level()
1505 table->MemoryACPILevel.VoltageDownH = 0; in ci_populate_smc_acpi_level()
1509 table->MemoryACPILevel.StutterEnable = 0; in ci_populate_smc_acpi_level()
1510 table->MemoryACPILevel.StrobeEnable = 0; in ci_populate_smc_acpi_level()
1511 table->MemoryACPILevel.EdcReadEnable = 0; in ci_populate_smc_acpi_level()
1512 table->MemoryACPILevel.EdcWriteEnable = 0; in ci_populate_smc_acpi_level()
1513 table->MemoryACPILevel.RttEnable = 0; in ci_populate_smc_acpi_level()
1521 int result = 0; in ci_populate_smc_uvd_level()
1529 for (count = 0; count < table->UvdLevelCount; count++) { in ci_populate_smc_uvd_level()
1540 PP_ASSERT_WITH_CODE((0 == result), in ci_populate_smc_uvd_level()
1547 PP_ASSERT_WITH_CODE((0 == result), in ci_populate_smc_uvd_level()
1569 table->VceBootLevel = 0; in ci_populate_smc_vce_level()
1571 for (count = 0; count < table->VceLevelCount; count++) { in ci_populate_smc_vce_level()
1579 PP_ASSERT_WITH_CODE((0 == result), in ci_populate_smc_vce_level()
1601 table->AcpBootLevel = 0; in ci_populate_smc_acp_level()
1603 for (count = 0; count < table->AcpLevelCount; count++) { in ci_populate_smc_acp_level()
1610 PP_ASSERT_WITH_CODE((0 == result), in ci_populate_smc_acp_level()
1636 PP_ASSERT_WITH_CODE(result == 0, in ci_populate_memory_timing_parameters()
1647 return 0; in ci_populate_memory_timing_parameters()
1654 int result = 0; in ci_program_memory_timing_parameters()
1658 memset(&arb_regs, 0x00, sizeof(SMU7_Discrete_MCArbDramTimingTable)); in ci_program_memory_timing_parameters()
1660 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in ci_program_memory_timing_parameters()
1661 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in ci_program_memory_timing_parameters()
1667 if (0 != result) in ci_program_memory_timing_parameters()
1672 if (0 == result) { in ci_program_memory_timing_parameters()
1688 int result = 0; in ci_populate_smc_boot_level()
1692 table->GraphicsBootLevel = 0; in ci_populate_smc_boot_level()
1693 table->MemoryBootLevel = 0; in ci_populate_smc_boot_level()
1700 if (0 != result) { in ci_populate_smc_boot_level()
1701 smu_data->smc_state_table.GraphicsBootLevel = 0; in ci_populate_smc_boot_level()
1702 …r("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0!\n"); in ci_populate_smc_boot_level()
1703 result = 0; in ci_populate_smc_boot_level()
1710 if (0 != result) { in ci_populate_smc_boot_level()
1711 smu_data->smc_state_table.MemoryBootLevel = 0; in ci_populate_smc_boot_level()
1712 …pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\… in ci_populate_smc_boot_level()
1713 result = 0; in ci_populate_smc_boot_level()
1730 for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) { in ci_populate_mc_reg_address()
1744 return 0; in ci_populate_mc_reg_address()
1754 for (i = 0, j = 0; j < num_entries; j++) { in ci_convert_mc_registers()
1769 uint32_t i = 0; in ci_convert_mc_reg_table_entry_to_smc()
1771 for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) { in ci_convert_mc_reg_table_entry_to_smc()
1778 if ((i == smu_data->mc_reg_table.num_entries) && (i > 0)) in ci_convert_mc_reg_table_entry_to_smc()
1785 return 0; in ci_convert_mc_reg_table_entry_to_smc()
1791 int result = 0; in ci_convert_mc_reg_table_to_smc()
1796 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { in ci_convert_mc_reg_table_to_smc()
1803 if (0 != res) in ci_convert_mc_reg_table_to_smc()
1817 if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in ci_update_and_upload_mc_reg_table()
1818 return 0; in ci_update_and_upload_mc_reg_table()
1821 memset(&smu_data->mc_regs, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_update_and_upload_mc_reg_table()
1825 if (result != 0) in ci_update_and_upload_mc_reg_table()
1828 address = smu_data->mc_reg_table_start + (uint32_t)offsetof(SMU7_Discrete_MCRegisters, data[0]); in ci_update_and_upload_mc_reg_table()
1831 (uint8_t *)&smu_data->mc_regs.data[0], in ci_update_and_upload_mc_reg_table()
1841 memset(&smu_data->mc_regs, 0x00, sizeof(SMU7_Discrete_MCRegisters)); in ci_populate_initial_mc_reg_table()
1843 PP_ASSERT_WITH_CODE(0 == result, in ci_populate_initial_mc_reg_table()
1847 PP_ASSERT_WITH_CODE(0 == result, in ci_populate_initial_mc_reg_table()
1862 for (level = 0; level < count; level++) { in ci_populate_smc_initial_state()
1872 for (level = 0; level < count; level++) { in ci_populate_smc_initial_state()
1880 return 0; in ci_populate_smc_initial_state()
1891 table->SVI2Enable = 0; in ci_populate_smc_svi2_config()
1892 return 0; in ci_populate_smc_svi2_config()
1897 /* set smc instruct start point at 0x0 */ in ci_start_smc()
1901 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); in ci_start_smc()
1903 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0); in ci_start_smc()
1908 return 0; in ci_start_smc()
1939 return 0; in ci_populate_vr_config()
1952 memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table)); in ci_init_smc_table()
1971 PP_ASSERT_WITH_CODE(0 == result, in ci_init_smc_table()
1975 ixCG_ULV_PARAMETER, 0x40035); in ci_init_smc_table()
1979 PP_ASSERT_WITH_CODE(0 == result, in ci_init_smc_table()
1983 PP_ASSERT_WITH_CODE(0 == result, in ci_init_smc_table()
1987 PP_ASSERT_WITH_CODE(0 == result, in ci_init_smc_table()
1991 PP_ASSERT_WITH_CODE(0 == result, in ci_init_smc_table()
1995 PP_ASSERT_WITH_CODE(0 == result, in ci_init_smc_table()
1999 PP_ASSERT_WITH_CODE(0 == result, in ci_init_smc_table()
2005 PP_ASSERT_WITH_CODE(0 == result, in ci_init_smc_table()
2009 PP_ASSERT_WITH_CODE(0 == result, in ci_init_smc_table()
2012 table->UvdBootLevel = 0; in ci_init_smc_table()
2013 table->VceBootLevel = 0; in ci_init_smc_table()
2014 table->AcpBootLevel = 0; in ci_init_smc_table()
2015 table->SamuBootLevel = 0; in ci_init_smc_table()
2017 table->GraphicsBootLevel = 0; in ci_init_smc_table()
2018 table->MemoryBootLevel = 0; in ci_init_smc_table()
2021 PP_ASSERT_WITH_CODE(0 == result, in ci_init_smc_table()
2025 PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot State!", return result); in ci_init_smc_table()
2028 PP_ASSERT_WITH_CODE(0 == result, "Failed to populate BAPM Parameters!", return result); in ci_init_smc_table()
2049 table->VoltageResponseTime = 0; in ci_init_smc_table()
2051 table->PhaseResponseTime = 0; in ci_init_smc_table()
2062 PP_ASSERT_WITH_CODE(0 == result, in ci_init_smc_table()
2068 for (i = 0; i < SMU7_MAX_ENTRIES_SMIO; i++) in ci_init_smc_table()
2072 table->SclkStepSize = 0x4000; in ci_init_smc_table()
2109 PP_ASSERT_WITH_CODE(0 == result, in ci_init_smc_table()
2113 PP_ASSERT_WITH_CODE((0 == result), in ci_init_smc_table()
2117 PP_ASSERT_WITH_CODE(0 == result, in ci_init_smc_table()
2122 return 0; in ci_init_smc_table()
2137 return 0; in ci_thermal_setup_fan_table()
2142 return 0; in ci_thermal_setup_fan_table()
2145 if (0 == ci_data->fan_table_start) { in ci_thermal_setup_fan_table()
2147 return 0; in ci_thermal_setup_fan_table()
2152 if (0 == duty100) { in ci_thermal_setup_fan_table()
2154 return 0; in ci_thermal_setup_fan_table()
2208 return 0; in ci_program_mem_timing_parameters()
2216 int result = 0; in ci_update_sclk_threshold()
2217 uint32_t low_sclk_interrupt_threshold = 0; in ci_update_sclk_threshold()
2221 && (data->low_sclk_interrupt_threshold != 0)) { in ci_update_sclk_threshold()
2239 PP_ASSERT_WITH_CODE((0 == result), "Failed to upload MC reg table!", return result); in ci_update_sclk_threshold()
2242 PP_ASSERT_WITH_CODE((result == 0), in ci_update_sclk_threshold()
2286 return 0; in ci_get_offsetof()
2310 return 0; in ci_get_mac_definition()
2319 struct cgs_firmware_info info = {0}; in ci_load_smc_ucode()
2338 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; in ci_load_smc_ucode()
2342 PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); in ci_load_smc_ucode()
2344 if (0 != byte_count) { in ci_load_smc_ucode()
2349 return 0; in ci_load_smc_ucode()
2356 return 0; in ci_upload_firmware()
2373 uint32_t tmp = 0; in ci_process_firmware_header()
2385 if (0 == result) in ci_process_firmware_header()
2388 error |= (0 != result); in ci_process_firmware_header()
2395 if (0 == result) { in ci_process_firmware_header()
2400 error |= (0 != result); in ci_process_firmware_header()
2407 if (0 == result) in ci_process_firmware_header()
2415 if (0 == result) in ci_process_firmware_header()
2418 error |= (0 != result); in ci_process_firmware_header()
2425 if (0 == result) in ci_process_firmware_header()
2428 error |= (0 != result); in ci_process_firmware_header()
2435 if (0 == result) in ci_process_firmware_header()
2438 error |= (0 != result); in ci_process_firmware_header()
2440 return error ? 1 : 0; in ci_process_firmware_header()
2445 return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16)); in ci_get_memory_modile_index()
2546 for (i = 0; i < table->last; i++) { in ci_set_s0_mc_reg_index()
2551 return 0; in ci_set_s0_mc_reg_index()
2564 for (i = 0; i < table->last; i++) in ci_copy_vbios_smc_reg_table()
2569 for (i = 0; i < table->num_entries; i++) { in ci_copy_vbios_smc_reg_table()
2572 for (j = 0; j < table->last; j++) { in ci_copy_vbios_smc_reg_table()
2580 return 0; in ci_copy_vbios_smc_reg_table()
2590 for (i = 0, j = table->last; i < table->last; i++) { in ci_set_mc_special_registers()
2600 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
2602 ((temp_reg & 0xffff0000)) | in ci_set_mc_special_registers()
2603 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); in ci_set_mc_special_registers()
2612 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
2614 (temp_reg & 0xffff0000) | in ci_set_mc_special_registers()
2615 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in ci_set_mc_special_registers()
2618 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; in ci_set_mc_special_registers()
2627 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
2629 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; in ci_set_mc_special_registers()
2640 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
2642 (temp_reg & 0xffff0000) | in ci_set_mc_special_registers()
2643 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in ci_set_mc_special_registers()
2656 return 0; in ci_set_mc_special_registers()
2663 for (i = 0; i < table->last; i++) { in ci_set_valid_flag()
2673 return 0; in ci_set_valid_flag()
2713 if (0 == result) in ci_initialize_mc_reg_table()
2716 if (0 == result) { in ci_initialize_mc_reg_table()
2721 if (0 == result) in ci_initialize_mc_reg_table()
2745 return 0; in ci_smu_init()
2752 return 0; in ci_smu_fini()
2757 return 0; in ci_start_smu()
2787 for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) { in ci_update_dpm_settings()
2794 offset = clk_activity_offset & ~0x3; in ci_update_dpm_settings()
2808 offset = up_hyst_offset & ~0x3; in ci_update_dpm_settings()
2822 for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) { in ci_update_dpm_settings()
2829 offset = clk_activity_offset & ~0x3; in ci_update_dpm_settings()
2843 offset = up_hyst_offset & ~0x3; in ci_update_dpm_settings()
2853 return 0; in ci_update_dpm_settings()
2871 if (PP_CAP(PHM_PlatformCaps_UVDDPM) || uvd_table->count <= 0) in ci_update_uvd_smc_table()
2872 smu_data->smc_state_table.UvdBootLevel = 0; in ci_update_uvd_smc_table()
2879 data->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; in ci_update_uvd_smc_table()
2881 for (i = uvd_table->count - 1; i >= 0; i--) { in ci_update_uvd_smc_table()
2891 return 0; in ci_update_uvd_smc_table()
2909 VceBootLevel, 0); /* temp hard code to level 0, vce can set min evclk*/ in ci_update_vce_smc_table()
2911 data->dpm_level_enable_mask.vce_dpm_enable_mask = 0; in ci_update_vce_smc_table()
2913 for (i = vce_table->count - 1; i >= 0; i--) { in ci_update_vce_smc_table()
2923 return 0; in ci_update_vce_smc_table()
2938 return 0; in ci_update_smc_table()
2961 return 0; in ci_stop_smc()