Lines Matching +full:high +full:- +full:dynamic
93 …Caps_ExclusiveModeAlwaysHigh, /* In Exclusive (3D) mode always stay in High state. */
96 PHM_PlatformCaps_UVDAlwaysHigh, /* In UVD mode always stay in High state */
112 …PHM_PlatformCaps_DynamicACTiming, /* if the SMC dynamically re-programs MC S…
114 …tStateOnAlert, /* Go to boot state on alerts, e.g. on an AC->DC transition. */
115 …rVBlankOnAlert, /* Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). */
143 …PHM_PlatformCaps_GFXDynamicMGPowerGating, /* Enable Dynamic MG PowerGating on Trinit…
148 …PHM_PlatformCaps_UVDDynamicPowerGating, /* enable UVD Dynamic power gating, suppor…
156 PHM_PlatformCaps_DynamicUVDState, /* Dynamic UVD State */
189 …MclkHigh, /* Disable memory clock switching by forcing memory clock high */
257 …((PHM_PlatformCaps_Max + ((PHM_MAX_NUM_CAPS_BITS_PER_FIELD) - 1)) / (PHM_MAX_NUM_CAPS_BITS_PER_FIE…
286 (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1))); in phm_cap_set()
292 caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &= ~(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1))); in phm_cap_unset()
298 (1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1))))); in phm_cap_enabled()
301 #define PP_CAP(c) phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (c))
305 PP_PCIEGen1 = 0, /* PCIE 1.0 - Transfer rate of 2.5 GT/s */
306 PP_PCIEGen2, /*PCIE 2.0 - Transfer rate of 5.0 GT/s */
307 PP_PCIEGen3 /*PCIE 3.0 - Transfer rate of 8.0 GT/s */
394 /* variable-sized array, specify by num_of_pl. */