Lines Matching +full:deep +full:- +full:sleep
102 …leepForUVD, /* With HW ECOs, we don't need to disable SCLK Deep Sleep for UVD state. */
112 …PHM_PlatformCaps_DynamicACTiming, /* if the SMC dynamically re-programs MC S…
114 …tStateOnAlert, /* Go to boot state on alerts, e.g. on an AC->DC transition. */
115 …rVBlankOnAlert, /* Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). */
119 PHM_PlatformCaps_DisableLightSleep, /* Light sleep for evergreen family. */
120 PHM_PlatformCaps_DisableMCLS, /* MC Light sleep */
125 PHM_PlatformCaps_SclkDeepSleep, /* support sclk deep sleep */
138 …PHM_PlatformCaps_DisableLSClockGating, /* to disable Light Sleep control for HDP …
155 …PHM_PlatformCaps_SclkDeepSleepAboveLow, /* Enable SCLK Deep Sleep on all DPM state…
257 …((PHM_PlatformCaps_Max + ((PHM_MAX_NUM_CAPS_BITS_PER_FIELD) - 1)) / (PHM_MAX_NUM_CAPS_BITS_PER_FIE…
286 (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1))); in phm_cap_set()
292 caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &= ~(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1))); in phm_cap_unset()
298 (1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1))))); in phm_cap_enabled()
301 #define PP_CAP(c) phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (c))
305 PP_PCIEGen1 = 0, /* PCIE 1.0 - Transfer rate of 2.5 GT/s */
306 PP_PCIEGen2, /*PCIE 2.0 - Transfer rate of 5.0 GT/s */
307 PP_PCIEGen3 /*PCIE 3.0 - Transfer rate of 8.0 GT/s */
394 /* variable-sized array, specify by num_of_pl. */