197 			(struct phm_ppt_v2_information *)hwmgr->pptable;  in vega10_set_features_platform_caps()
307 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_odn_initial_default_setting()
531 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_get_socclk_for_voltage_evv()
568 			(struct phm_ppt_v2_information *)hwmgr->pptable;  in vega10_get_evv_voltages()
673 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_patch_voltage_dependency_tables_with_lookup_table()
749 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_complete_dependency_tables()
778 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_set_private_data_based_on_pptable()
1174 			(struct phm_ppt_v2_information *)hwmgr->pptable;  in vega10_construct_voltage_tables()
1263 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_setup_default_pcie_table()
1311 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_setup_default_dpm_tables()
1481 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_populate_ulv_state()
1618 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_populate_single_gfx_level()
1686 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_populate_single_soc_level()
1731 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_populate_all_graphic_levels()
1788 	struct phm_ppt_v2_information *table_info = hwmgr->pptable;  in vega10_populate_vddc_soc_levels()
1823 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_populate_single_memory_level()
1927 			(hwmgr->pptable);  in vega10_populate_single_display_type()
1994 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_populate_single_eclock_level()
2088 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_populate_smc_uvd_levels()
2155 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_populate_clock_stretcher_table()
2174 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_populate_avfs_parameters()
2532 	struct phm_ppt_v2_information *table_info = hwmgr->pptable;  in vega10_check_dpm_table_updated()
2568 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_init_smc_table()
3029 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_populate_umdpstate_clocks()
3293 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_apply_state_adjust_rules()
3633 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_get_soc_index_for_max_uclk()
4103 			(struct phm_ppt_v2_information *)hwmgr->pptable;  in vega10_notify_smc_display_config_after_ps_adjustment()
4223 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_get_profiling_clk_mask()
4394 			(struct phm_ppt_v2_information *)hwmgr->pptable;  in vega10_get_dal_power_level()
4408 			(struct phm_ppt_v2_information *)hwmgr->pptable;  in vega10_get_sclks()
4428 			(struct phm_ppt_v2_information *)hwmgr->pptable;  in vega10_get_memclocks()
4454 			(struct phm_ppt_v2_information *)hwmgr->pptable;  in vega10_get_dcefclocks()
4470 			(struct phm_ppt_v2_information *)hwmgr->pptable;  in vega10_get_socclocks()
4511 			(struct phm_ppt_v2_information *)hwmgr->pptable;  in vega10_get_clock_by_type_with_voltage()
4692 	PPTable_t *pptable = &(data->smc_state_table.pp_table);  in vega10_emit_clock_levels()  local
4764 			gen_speed = pptable->PcieGenSpeed[i];  in vega10_emit_clock_levels()
4765 			lane_width = pptable->PcieLaneCount[i];  in vega10_emit_clock_levels()
4838 	PPTable_t *pptable = &(data->smc_state_table.pp_table);  in vega10_print_clock_levels()  local
4908 			gen_speed = pptable->PcieGenSpeed[i];  in vega10_print_clock_levels()
4909 			lane_width = pptable->PcieLaneCount[i];  in vega10_print_clock_levels()
5293 		(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_get_thermal_temperature_range()
5524 	struct phm_ppt_v2_information *table_info = hwmgr->pptable;  in vega10_odn_update_soc_table()