Lines Matching refs:hwmgr

115 static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr)  in vega10_set_default_registry_data()  argument
117 struct vega10_hwmgr *data = hwmgr->backend; in vega10_set_default_registry_data()
120 hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
122 hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
124 hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
126 hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true; in vega10_set_default_registry_data()
129 hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
131 if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) { in vega10_set_default_registry_data()
138 hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false; in vega10_set_default_registry_data()
141 hwmgr->feature_mask & PP_ULV_MASK ? true : false; in vega10_set_default_registry_data()
144 hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false; in vega10_set_default_registry_data()
153 hwmgr->feature_mask & PP_AVFS_MASK ? true : false; in vega10_set_default_registry_data()
193 static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr) in vega10_set_features_platform_caps() argument
195 struct vega10_hwmgr *data = hwmgr->backend; in vega10_set_features_platform_caps()
197 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega10_set_features_platform_caps()
198 struct amdgpu_device *adev = hwmgr->adev; in vega10_set_features_platform_caps()
200 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
203 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
207 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
210 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
214 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
218 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
221 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
224 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
227 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
230 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
233 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
238 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
240 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
242 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
244 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
246 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
248 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
250 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
252 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
254 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
256 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
260 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport); in vega10_set_features_platform_caps()
262 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping); in vega10_set_features_platform_caps()
264 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping); in vega10_set_features_platform_caps()
266 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping); in vega10_set_features_platform_caps()
268 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping); in vega10_set_features_platform_caps()
270 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping); in vega10_set_features_platform_caps()
272 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable); in vega10_set_features_platform_caps()
274 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC); in vega10_set_features_platform_caps()
276 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM); in vega10_set_features_platform_caps()
280 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
282 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
287 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
290 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
292 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
295 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
297 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega10_set_features_platform_caps()
303 static int vega10_odn_initial_default_setting(struct pp_hwmgr *hwmgr) in vega10_odn_initial_default_setting() argument
305 struct vega10_hwmgr *data = hwmgr->backend; in vega10_odn_initial_default_setting()
307 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_odn_initial_default_setting()
317 result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params); in vega10_odn_initial_default_setting()
347 …od_table[2]->entries[i].clk = hwmgr->platform_descriptor.overdriveLimit.memoryClock > od_table[2]-… in vega10_odn_initial_default_setting()
348 hwmgr->platform_descriptor.overdriveLimit.memoryClock : in vega10_odn_initial_default_setting()
357 static int vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) in vega10_init_dpm_defaults() argument
359 struct vega10_hwmgr *data = hwmgr->backend; in vega10_init_dpm_defaults()
362 struct amdgpu_device *adev = hwmgr->adev; in vega10_init_dpm_defaults()
365 vega10_initialize_power_tune_defaults(hwmgr); in vega10_init_dpm_defaults()
488 ret = smum_send_msg_to_smc(hwmgr, in vega10_init_dpm_defaults()
490 &hwmgr->smu_version); in vega10_init_dpm_defaults()
495 if ((hwmgr->smu_version & 0xff000000) == 0x5000000) in vega10_init_dpm_defaults()
503 if ((hwmgr->chip_id == 0x6862 || in vega10_init_dpm_defaults()
504 hwmgr->chip_id == 0x6861 || in vega10_init_dpm_defaults()
505 hwmgr->chip_id == 0x6868) && in vega10_init_dpm_defaults()
511 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32); in vega10_init_dpm_defaults()
515 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32); in vega10_init_dpm_defaults()
524 static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr, in vega10_get_socclk_for_voltage_evv() argument
531 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_get_socclk_for_voltage_evv()
560 static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr) in vega10_get_evv_voltages() argument
562 struct vega10_hwmgr *data = hwmgr->backend; in vega10_get_evv_voltages()
568 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega10_get_evv_voltages()
576 if (!vega10_get_socclk_for_voltage_evv(hwmgr, in vega10_get_evv_voltages()
588 PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, in vega10_get_evv_voltages()
617 static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr, in vega10_patch_with_vdd_leakage() argument
644 static int vega10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr, in vega10_patch_lookup_table_with_leakage() argument
651 vega10_patch_with_vdd_leakage(hwmgr, in vega10_patch_lookup_table_with_leakage()
658 struct pp_hwmgr *hwmgr, struct vega10_leakage_voltage *leakage_table, in vega10_patch_clock_voltage_limits_with_vddc_leakage() argument
661 vega10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table); in vega10_patch_clock_voltage_limits_with_vddc_leakage()
668 struct pp_hwmgr *hwmgr) in vega10_patch_voltage_dependency_tables_with_lookup_table() argument
673 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_patch_voltage_dependency_tables_with_lookup_table()
720 static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr, in vega10_sort_lookup_table() argument
744 static int vega10_complete_dependency_tables(struct pp_hwmgr *hwmgr) in vega10_complete_dependency_tables() argument
749 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_complete_dependency_tables()
751 struct vega10_hwmgr *data = hwmgr->backend; in vega10_complete_dependency_tables()
753 tmp_result = vega10_patch_lookup_table_with_leakage(hwmgr, in vega10_complete_dependency_tables()
758 tmp_result = vega10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr, in vega10_complete_dependency_tables()
764 tmp_result = vega10_patch_voltage_dependency_tables_with_lookup_table(hwmgr); in vega10_complete_dependency_tables()
768 tmp_result = vega10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table); in vega10_complete_dependency_tables()
775 static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) in vega10_set_private_data_based_on_pptable() argument
778 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_set_private_data_based_on_pptable()
803 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = in vega10_set_private_data_based_on_pptable()
805 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = in vega10_set_private_data_based_on_pptable()
807 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = in vega10_set_private_data_based_on_pptable()
809 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = in vega10_set_private_data_based_on_pptable()
815 static int vega10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) in vega10_hwmgr_backend_fini() argument
817 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); in vega10_hwmgr_backend_fini()
818 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; in vega10_hwmgr_backend_fini()
820 kfree(hwmgr->backend); in vega10_hwmgr_backend_fini()
821 hwmgr->backend = NULL; in vega10_hwmgr_backend_fini()
826 static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) in vega10_hwmgr_backend_init() argument
832 struct amdgpu_device *adev = hwmgr->adev; in vega10_hwmgr_backend_init()
838 hwmgr->backend = data; in vega10_hwmgr_backend_init()
840 hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; in vega10_hwmgr_backend_init()
841 hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; in vega10_hwmgr_backend_init()
842 hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; in vega10_hwmgr_backend_init()
844 vega10_set_default_registry_data(hwmgr); in vega10_hwmgr_backend_init()
853 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr, in vega10_hwmgr_backend_init()
855 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr, in vega10_hwmgr_backend_init()
863 kfree(hwmgr->backend); in vega10_hwmgr_backend_init()
864 hwmgr->backend = NULL; in vega10_hwmgr_backend_init()
871 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr, in vega10_hwmgr_backend_init()
873 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr, in vega10_hwmgr_backend_init()
885 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr, in vega10_hwmgr_backend_init()
892 vega10_set_features_platform_caps(hwmgr); in vega10_hwmgr_backend_init()
894 result = vega10_init_dpm_defaults(hwmgr); in vega10_hwmgr_backend_init()
900 PP_ASSERT_WITH_CODE(!vega10_get_evv_voltages(hwmgr), in vega10_hwmgr_backend_init()
908 vega10_complete_dependency_tables(hwmgr); in vega10_hwmgr_backend_init()
911 vega10_set_private_data_based_on_pptable(hwmgr); in vega10_hwmgr_backend_init()
915 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = in vega10_hwmgr_backend_init()
917 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; in vega10_hwmgr_backend_init()
918 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; in vega10_hwmgr_backend_init()
920 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ in vega10_hwmgr_backend_init()
922 hwmgr->platform_descriptor.clockStep.engineClock = 500; in vega10_hwmgr_backend_init()
923 hwmgr->platform_descriptor.clockStep.memoryClock = 500; in vega10_hwmgr_backend_init()
926 if (!hwmgr->not_vf) in vega10_hwmgr_backend_init()
931 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM; in vega10_hwmgr_backend_init()
933 hwmgr->thermal_controller. in vega10_hwmgr_backend_init()
936 hwmgr->thermal_controller.advanceFanControlParameters. in vega10_hwmgr_backend_init()
939 hwmgr->thermal_controller. in vega10_hwmgr_backend_init()
941 hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100; in vega10_hwmgr_backend_init()
953 static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr) in vega10_init_sclk_threshold() argument
955 struct vega10_hwmgr *data = hwmgr->backend; in vega10_init_sclk_threshold()
962 static int vega10_setup_dpm_led_config(struct pp_hwmgr *hwmgr) in vega10_setup_dpm_led_config() argument
964 struct vega10_hwmgr *data = hwmgr->backend; in vega10_setup_dpm_led_config()
973 ret = pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_LEDDPM, in vega10_setup_dpm_led_config()
994 static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr) in vega10_setup_asic_task() argument
996 if (!hwmgr->not_vf) in vega10_setup_asic_task()
999 PP_ASSERT_WITH_CODE(!vega10_init_sclk_threshold(hwmgr), in vega10_setup_asic_task()
1003 PP_ASSERT_WITH_CODE(!vega10_setup_dpm_led_config(hwmgr), in vega10_setup_asic_task()
1007 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_setup_asic_task()
1022 static int vega10_trim_voltage_table(struct pp_hwmgr *hwmgr, in vega10_trim_voltage_table() argument
1066 static int vega10_get_mvdd_voltage_table(struct pp_hwmgr *hwmgr, in vega10_get_mvdd_voltage_table() argument
1085 PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, in vega10_get_mvdd_voltage_table()
1093 static int vega10_get_vddci_voltage_table(struct pp_hwmgr *hwmgr, in vega10_get_vddci_voltage_table() argument
1112 PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, vol_table), in vega10_get_vddci_voltage_table()
1119 static int vega10_get_vdd_voltage_table(struct pp_hwmgr *hwmgr, in vega10_get_vdd_voltage_table() argument
1147 struct pp_hwmgr *hwmgr, in vega10_trim_voltage_table_to_fit_state_table() argument
1170 static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr) in vega10_construct_voltage_tables() argument
1172 struct vega10_hwmgr *data = hwmgr->backend; in vega10_construct_voltage_tables()
1174 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega10_construct_voltage_tables()
1179 result = vega10_get_mvdd_voltage_table(hwmgr, in vega10_construct_voltage_tables()
1188 result = vega10_get_vddci_voltage_table(hwmgr, in vega10_construct_voltage_tables()
1198 result = vega10_get_vdd_voltage_table(hwmgr, in vega10_construct_voltage_tables()
1208 vega10_trim_voltage_table_to_fit_state_table(hwmgr, in vega10_construct_voltage_tables()
1213 vega10_trim_voltage_table_to_fit_state_table(hwmgr, in vega10_construct_voltage_tables()
1218 vega10_trim_voltage_table_to_fit_state_table(hwmgr, in vega10_construct_voltage_tables()
1240 static void vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr, in vega10_setup_default_single_dpm_table() argument
1258 static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr) in vega10_setup_default_pcie_table() argument
1260 struct vega10_hwmgr *data = hwmgr->backend; in vega10_setup_default_pcie_table()
1263 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_setup_default_pcie_table()
1307 static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) in vega10_setup_default_dpm_tables() argument
1309 struct vega10_hwmgr *data = hwmgr->backend; in vega10_setup_default_dpm_tables()
1311 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_setup_default_dpm_tables()
1355 vega10_setup_default_single_dpm_table(hwmgr, in vega10_setup_default_dpm_tables()
1362 vega10_setup_default_single_dpm_table(hwmgr, in vega10_setup_default_dpm_tables()
1365 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) in vega10_setup_default_dpm_tables()
1366 hwmgr->platform_descriptor.overdriveLimit.engineClock = in vega10_setup_default_dpm_tables()
1373 vega10_setup_default_single_dpm_table(hwmgr, in vega10_setup_default_dpm_tables()
1376 if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0) in vega10_setup_default_dpm_tables()
1377 hwmgr->platform_descriptor.overdriveLimit.memoryClock = in vega10_setup_default_dpm_tables()
1425 vega10_setup_default_single_dpm_table(hwmgr, in vega10_setup_default_dpm_tables()
1432 vega10_setup_default_single_dpm_table(hwmgr, in vega10_setup_default_dpm_tables()
1439 vega10_setup_default_single_dpm_table(hwmgr, in vega10_setup_default_dpm_tables()
1446 vega10_setup_default_single_dpm_table(hwmgr, in vega10_setup_default_dpm_tables()
1452 vega10_setup_default_pcie_table(hwmgr); in vega10_setup_default_dpm_tables()
1477 static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr) in vega10_populate_ulv_state() argument
1479 struct vega10_hwmgr *data = hwmgr->backend; in vega10_populate_ulv_state()
1481 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_populate_ulv_state()
1500 static int vega10_populate_single_lclk_level(struct pp_hwmgr *hwmgr, in vega10_populate_single_lclk_level() argument
1506 hwmgr, in vega10_populate_single_lclk_level()
1517 static int vega10_override_pcie_parameters(struct pp_hwmgr *hwmgr) in vega10_override_pcie_parameters() argument
1519 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); in vega10_override_pcie_parameters()
1521 (struct vega10_hwmgr *)(hwmgr->backend); in vega10_override_pcie_parameters()
1566 static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr) in vega10_populate_smc_link_levels() argument
1569 struct vega10_hwmgr *data = hwmgr->backend; in vega10_populate_smc_link_levels()
1579 result = vega10_populate_single_lclk_level(hwmgr, in vega10_populate_smc_link_levels()
1592 result = vega10_populate_single_lclk_level(hwmgr, in vega10_populate_smc_link_levels()
1613 static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr, in vega10_populate_single_gfx_level() argument
1618 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_populate_single_gfx_level()
1620 struct vega10_hwmgr *data = hwmgr->backend; in vega10_populate_single_gfx_level()
1623 hwmgr->platform_descriptor.overdriveLimit.engineClock; in vega10_populate_single_gfx_level()
1626 if (hwmgr->od_enabled) in vega10_populate_single_gfx_level()
1648 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, in vega10_populate_single_gfx_level()
1680 static int vega10_populate_single_soc_level(struct pp_hwmgr *hwmgr, in vega10_populate_single_soc_level() argument
1684 struct vega10_hwmgr *data = hwmgr->backend; in vega10_populate_single_soc_level()
1686 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_populate_single_soc_level()
1691 if (hwmgr->od_enabled) { in vega10_populate_single_soc_level()
1710 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, in vega10_populate_single_soc_level()
1727 static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) in vega10_populate_all_graphic_levels() argument
1729 struct vega10_hwmgr *data = hwmgr->backend; in vega10_populate_all_graphic_levels()
1731 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_populate_all_graphic_levels()
1738 result = vega10_populate_single_gfx_level(hwmgr, in vega10_populate_all_graphic_levels()
1748 result = vega10_populate_single_gfx_level(hwmgr, in vega10_populate_all_graphic_levels()
1762 result = vega10_populate_single_soc_level(hwmgr, in vega10_populate_all_graphic_levels()
1772 result = vega10_populate_single_soc_level(hwmgr, in vega10_populate_all_graphic_levels()
1784 static void vega10_populate_vddc_soc_levels(struct pp_hwmgr *hwmgr) in vega10_populate_vddc_soc_levels() argument
1786 struct vega10_hwmgr *data = hwmgr->backend; in vega10_populate_vddc_soc_levels()
1788 struct phm_ppt_v2_information *table_info = hwmgr->pptable; in vega10_populate_vddc_soc_levels()
1794 if (hwmgr->od_enabled) in vega10_populate_vddc_soc_levels()
1817 static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr, in vega10_populate_single_memory_level() argument
1821 struct vega10_hwmgr *data = hwmgr->backend; in vega10_populate_single_memory_level()
1823 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_populate_single_memory_level()
1827 hwmgr->platform_descriptor.overdriveLimit.memoryClock; in vega10_populate_single_memory_level()
1830 if (hwmgr->od_enabled) in vega10_populate_single_memory_level()
1853 hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, &dividers), in vega10_populate_single_memory_level()
1878 static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) in vega10_populate_all_memory_levels() argument
1880 struct vega10_hwmgr *data = hwmgr->backend; in vega10_populate_all_memory_levels()
1888 result = vega10_populate_single_memory_level(hwmgr, in vega10_populate_all_memory_levels()
1899 result = vega10_populate_single_memory_level(hwmgr, in vega10_populate_all_memory_levels()
1920 static int vega10_populate_single_display_type(struct pp_hwmgr *hwmgr, in vega10_populate_single_display_type() argument
1923 struct vega10_hwmgr *data = hwmgr->backend; in vega10_populate_single_display_type()
1927 (hwmgr->pptable); in vega10_populate_single_display_type()
1976 static int vega10_populate_all_display_clock_levels(struct pp_hwmgr *hwmgr) in vega10_populate_all_display_clock_levels() argument
1981 PP_ASSERT_WITH_CODE(!vega10_populate_single_display_type(hwmgr, i), in vega10_populate_all_display_clock_levels()
1989 static int vega10_populate_single_eclock_level(struct pp_hwmgr *hwmgr, in vega10_populate_single_eclock_level() argument
1994 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_populate_single_eclock_level()
2000 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, in vega10_populate_single_eclock_level()
2016 static int vega10_populate_smc_vce_levels(struct pp_hwmgr *hwmgr) in vega10_populate_smc_vce_levels() argument
2018 struct vega10_hwmgr *data = hwmgr->backend; in vega10_populate_smc_vce_levels()
2025 result = vega10_populate_single_eclock_level(hwmgr, in vega10_populate_smc_vce_levels()
2035 result = vega10_populate_single_eclock_level(hwmgr, in vega10_populate_smc_vce_levels()
2047 static int vega10_populate_single_vclock_level(struct pp_hwmgr *hwmgr, in vega10_populate_single_vclock_level() argument
2052 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, in vega10_populate_single_vclock_level()
2063 static int vega10_populate_single_dclock_level(struct pp_hwmgr *hwmgr, in vega10_populate_single_dclock_level() argument
2068 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, in vega10_populate_single_dclock_level()
2079 static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr) in vega10_populate_smc_uvd_levels() argument
2081 struct vega10_hwmgr *data = hwmgr->backend; in vega10_populate_smc_uvd_levels()
2088 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_populate_smc_uvd_levels()
2095 result = vega10_populate_single_vclock_level(hwmgr, in vega10_populate_smc_uvd_levels()
2104 result = vega10_populate_single_vclock_level(hwmgr, in vega10_populate_smc_uvd_levels()
2113 result = vega10_populate_single_dclock_level(hwmgr, in vega10_populate_smc_uvd_levels()
2122 result = vega10_populate_single_dclock_level(hwmgr, in vega10_populate_smc_uvd_levels()
2150 static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr) in vega10_populate_clock_stretcher_table() argument
2152 struct vega10_hwmgr *data = hwmgr->backend; in vega10_populate_clock_stretcher_table()
2155 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_populate_clock_stretcher_table()
2169 static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) in vega10_populate_avfs_parameters() argument
2171 struct vega10_hwmgr *data = hwmgr->backend; in vega10_populate_avfs_parameters()
2174 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_populate_avfs_parameters()
2185 result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params); in vega10_populate_avfs_parameters()
2360 static int vega10_acg_enable(struct pp_hwmgr *hwmgr) in vega10_acg_enable() argument
2362 struct vega10_hwmgr *data = hwmgr->backend; in vega10_acg_enable()
2367 if (0 == vega10_enable_smc_features(hwmgr, true, in vega10_acg_enable()
2371 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg, NULL); in vega10_acg_enable()
2375 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc, &agc_btc_response); in vega10_acg_enable()
2381 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInClosedLoop, NULL); in vega10_acg_enable()
2383 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInOpenLoop, NULL); in vega10_acg_enable()
2384 if (0 == vega10_enable_smc_features(hwmgr, true, in vega10_acg_enable()
2396 static int vega10_acg_disable(struct pp_hwmgr *hwmgr) in vega10_acg_disable() argument
2398 struct vega10_hwmgr *data = hwmgr->backend; in vega10_acg_disable()
2402 if (!vega10_enable_smc_features(hwmgr, false, in vega10_acg_disable()
2409 static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr) in vega10_populate_gpio_parameters() argument
2411 struct vega10_hwmgr *data = hwmgr->backend; in vega10_populate_gpio_parameters()
2416 result = pp_atomfwctrl_get_gpio_information(hwmgr, &gpio_params); in vega10_populate_gpio_parameters()
2444 static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable) in vega10_avfs_enable() argument
2446 struct vega10_hwmgr *data = hwmgr->backend; in vega10_avfs_enable()
2454 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, in vega10_avfs_enable()
2461 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, in vega10_avfs_enable()
2473 static int vega10_update_avfs(struct pp_hwmgr *hwmgr) in vega10_update_avfs() argument
2475 struct vega10_hwmgr *data = hwmgr->backend; in vega10_update_avfs()
2478 vega10_avfs_enable(hwmgr, false); in vega10_update_avfs()
2480 vega10_avfs_enable(hwmgr, false); in vega10_update_avfs()
2481 vega10_avfs_enable(hwmgr, true); in vega10_update_avfs()
2483 vega10_avfs_enable(hwmgr, true); in vega10_update_avfs()
2489 static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr) in vega10_populate_and_upload_avfs_fuse_override() argument
2497 struct vega10_hwmgr *data = hwmgr->backend; in vega10_populate_and_upload_avfs_fuse_override()
2500 result = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32); in vega10_populate_and_upload_avfs_fuse_override()
2503 result = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32); in vega10_populate_and_upload_avfs_fuse_override()
2518 result = smum_smc_table_manager(hwmgr, (uint8_t *)avfs_fuse_table, in vega10_populate_and_upload_avfs_fuse_override()
2528 static void vega10_check_dpm_table_updated(struct pp_hwmgr *hwmgr) in vega10_check_dpm_table_updated() argument
2530 struct vega10_hwmgr *data = hwmgr->backend; in vega10_check_dpm_table_updated()
2532 struct phm_ppt_v2_information *table_info = hwmgr->pptable; in vega10_check_dpm_table_updated()
2563 static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) in vega10_init_smc_table() argument
2566 struct vega10_hwmgr *data = hwmgr->backend; in vega10_init_smc_table()
2568 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_init_smc_table()
2574 result = vega10_setup_default_dpm_tables(hwmgr); in vega10_init_smc_table()
2579 if (!hwmgr->not_vf) in vega10_init_smc_table()
2583 if (hwmgr->od_enabled) { in vega10_init_smc_table()
2586 vega10_check_dpm_table_updated(hwmgr); in vega10_init_smc_table()
2588 vega10_odn_initial_default_setting(hwmgr); in vega10_init_smc_table()
2592 result = pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_VDDC, in vega10_init_smc_table()
2620 result = vega10_populate_ulv_state(hwmgr); in vega10_init_smc_table()
2626 result = vega10_populate_smc_link_levels(hwmgr); in vega10_init_smc_table()
2631 result = vega10_override_pcie_parameters(hwmgr); in vega10_init_smc_table()
2636 result = vega10_populate_all_graphic_levels(hwmgr); in vega10_init_smc_table()
2641 result = vega10_populate_all_memory_levels(hwmgr); in vega10_init_smc_table()
2646 vega10_populate_vddc_soc_levels(hwmgr); in vega10_init_smc_table()
2648 result = vega10_populate_all_display_clock_levels(hwmgr); in vega10_init_smc_table()
2653 result = vega10_populate_smc_vce_levels(hwmgr); in vega10_init_smc_table()
2658 result = vega10_populate_smc_uvd_levels(hwmgr); in vega10_init_smc_table()
2664 result = vega10_populate_clock_stretcher_table(hwmgr); in vega10_init_smc_table()
2670 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values); in vega10_init_smc_table()
2677 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, in vega10_init_smc_table()
2680 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, in vega10_init_smc_table()
2686 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_init_smc_table()
2694 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_init_smc_table()
2700 result = vega10_populate_avfs_parameters(hwmgr); in vega10_init_smc_table()
2705 result = vega10_populate_gpio_parameters(hwmgr); in vega10_init_smc_table()
2719 vega10_populate_and_upload_avfs_fuse_override(hwmgr); in vega10_init_smc_table()
2721 result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false); in vega10_init_smc_table()
2726 result = vega10_avfs_enable(hwmgr, true); in vega10_init_smc_table()
2729 vega10_acg_enable(hwmgr); in vega10_init_smc_table()
2734 static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr) in vega10_enable_thermal_protection() argument
2736 struct vega10_hwmgr *data = hwmgr->backend; in vega10_enable_thermal_protection()
2743 !vega10_enable_smc_features(hwmgr, in vega10_enable_thermal_protection()
2754 static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr) in vega10_disable_thermal_protection() argument
2756 struct vega10_hwmgr *data = hwmgr->backend; in vega10_disable_thermal_protection()
2763 !vega10_enable_smc_features(hwmgr, in vega10_disable_thermal_protection()
2774 static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr) in vega10_enable_vrhot_feature() argument
2776 struct vega10_hwmgr *data = hwmgr->backend; in vega10_enable_vrhot_feature()
2781 !vega10_enable_smc_features(hwmgr, in vega10_enable_vrhot_feature()
2790 !vega10_enable_smc_features(hwmgr, in vega10_enable_vrhot_feature()
2802 static int vega10_enable_ulv(struct pp_hwmgr *hwmgr) in vega10_enable_ulv() argument
2804 struct vega10_hwmgr *data = hwmgr->backend; in vega10_enable_ulv()
2807 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, in vega10_enable_ulv()
2817 static int vega10_disable_ulv(struct pp_hwmgr *hwmgr) in vega10_disable_ulv() argument
2819 struct vega10_hwmgr *data = hwmgr->backend; in vega10_disable_ulv()
2822 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, in vega10_disable_ulv()
2832 static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) in vega10_enable_deep_sleep_master_switch() argument
2834 struct vega10_hwmgr *data = hwmgr->backend; in vega10_enable_deep_sleep_master_switch()
2837 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, in vega10_enable_deep_sleep_master_switch()
2845 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, in vega10_enable_deep_sleep_master_switch()
2853 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, in vega10_enable_deep_sleep_master_switch()
2861 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, in vega10_enable_deep_sleep_master_switch()
2871 static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) in vega10_disable_deep_sleep_master_switch() argument
2873 struct vega10_hwmgr *data = hwmgr->backend; in vega10_disable_deep_sleep_master_switch()
2876 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, in vega10_disable_deep_sleep_master_switch()
2884 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, in vega10_disable_deep_sleep_master_switch()
2892 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, in vega10_disable_deep_sleep_master_switch()
2900 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, in vega10_disable_deep_sleep_master_switch()
2910 static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) in vega10_stop_dpm() argument
2912 struct vega10_hwmgr *data = hwmgr->backend; in vega10_stop_dpm()
2915 if (!hwmgr->not_vf) in vega10_stop_dpm()
2919 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, in vega10_stop_dpm()
2937 return vega10_enable_smc_features(hwmgr, false, feature_mask); in vega10_stop_dpm()
2947 static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) in vega10_start_dpm() argument
2949 struct vega10_hwmgr *data = hwmgr->backend; in vega10_start_dpm()
2964 if (vega10_enable_smc_features(hwmgr, in vega10_start_dpm()
2974 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, in vega10_start_dpm()
2981 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_start_dpm()
2989 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, in vega10_start_dpm()
2998 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, in vega10_start_dpm()
3009 static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable) in vega10_enable_disable_PCC_limit_feature() argument
3011 struct vega10_hwmgr *data = hwmgr->backend; in vega10_enable_disable_PCC_limit_feature()
3016 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, in vega10_enable_disable_PCC_limit_feature()
3026 static void vega10_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) in vega10_populate_umdpstate_clocks() argument
3029 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_populate_umdpstate_clocks()
3033 hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk; in vega10_populate_umdpstate_clocks()
3034 hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk; in vega10_populate_umdpstate_clocks()
3036 hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; in vega10_populate_umdpstate_clocks()
3037 hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[0].clk; in vega10_populate_umdpstate_clocks()
3040hwmgr->pstate_sclk_peak = table_info->vdd_dep_on_sclk->entries[table_info->vdd_dep_on_sclk->count … in vega10_populate_umdpstate_clocks()
3041hwmgr->pstate_mclk_peak = table_info->vdd_dep_on_mclk->entries[table_info->vdd_dep_on_mclk->count … in vega10_populate_umdpstate_clocks()
3044 hwmgr->pstate_sclk /= 100; in vega10_populate_umdpstate_clocks()
3045 hwmgr->pstate_mclk /= 100; in vega10_populate_umdpstate_clocks()
3046 hwmgr->pstate_sclk_peak /= 100; in vega10_populate_umdpstate_clocks()
3047 hwmgr->pstate_mclk_peak /= 100; in vega10_populate_umdpstate_clocks()
3050 static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) in vega10_enable_dpm_tasks() argument
3052 struct vega10_hwmgr *data = hwmgr->backend; in vega10_enable_dpm_tasks()
3055 if (hwmgr->not_vf) { in vega10_enable_dpm_tasks()
3056 vega10_enable_disable_PCC_limit_feature(hwmgr, true); in vega10_enable_dpm_tasks()
3058 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_enable_dpm_tasks()
3062 tmp_result = vega10_construct_voltage_tables(hwmgr); in vega10_enable_dpm_tasks()
3068 if (hwmgr->not_vf || hwmgr->pp_one_vf) { in vega10_enable_dpm_tasks()
3069 tmp_result = vega10_init_smc_table(hwmgr); in vega10_enable_dpm_tasks()
3075 if (hwmgr->not_vf) { in vega10_enable_dpm_tasks()
3077 tmp_result = vega10_enable_thermal_protection(hwmgr); in vega10_enable_dpm_tasks()
3083 tmp_result = vega10_enable_vrhot_feature(hwmgr); in vega10_enable_dpm_tasks()
3088 tmp_result = vega10_enable_deep_sleep_master_switch(hwmgr); in vega10_enable_dpm_tasks()
3094 if (hwmgr->not_vf) { in vega10_enable_dpm_tasks()
3095 tmp_result = vega10_start_dpm(hwmgr, SMC_DPM_FEATURES); in vega10_enable_dpm_tasks()
3100 if (hwmgr->not_vf) { in vega10_enable_dpm_tasks()
3102 tmp_result = vega10_enable_didt_config(hwmgr); in vega10_enable_dpm_tasks()
3107 tmp_result = vega10_enable_power_containment(hwmgr); in vega10_enable_dpm_tasks()
3112 if (hwmgr->not_vf) { in vega10_enable_dpm_tasks()
3113 tmp_result = vega10_power_control_set_level(hwmgr); in vega10_enable_dpm_tasks()
3118 tmp_result = vega10_enable_ulv(hwmgr); in vega10_enable_dpm_tasks()
3124 vega10_populate_umdpstate_clocks(hwmgr); in vega10_enable_dpm_tasks()
3129 static int vega10_get_power_state_size(struct pp_hwmgr *hwmgr) in vega10_get_power_state_size() argument
3134 static int vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr, in vega10_get_pp_table_entry_callback_func() argument
3200 hwmgr->platform_descriptor. in vega10_get_pp_table_entry_callback_func()
3221 if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0)) in vega10_get_pp_table_entry_callback_func()
3229 if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0)) in vega10_get_pp_table_entry_callback_func()
3241 static int vega10_get_pp_table_entry(struct pp_hwmgr *hwmgr, in vega10_get_pp_table_entry() argument
3251 result = vega10_get_powerplay_table_entry(hwmgr, entry_index, state, in vega10_get_pp_table_entry()
3270 static int vega10_patch_boot_state(struct pp_hwmgr *hwmgr, in vega10_patch_boot_state() argument
3276 static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, in vega10_apply_state_adjust_rules() argument
3280 struct amdgpu_device *adev = hwmgr->adev; in vega10_apply_state_adjust_rules()
3291 struct vega10_hwmgr *data = hwmgr->backend; in vega10_apply_state_adjust_rules()
3293 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_apply_state_adjust_rules()
3310 &(hwmgr->dyn_state.max_clock_voltage_on_ac) : in vega10_apply_state_adjust_rules()
3311 &(hwmgr->dyn_state.max_clock_voltage_on_dc); in vega10_apply_state_adjust_rules()
3328 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in vega10_apply_state_adjust_rules()
3329 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega10_apply_state_adjust_rules()
3340 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); in vega10_apply_state_adjust_rules()
3369 if (hwmgr->display_config->num_display == 0) in vega10_apply_state_adjust_rules()
3372 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega10_apply_state_adjust_rules()
3373 !hwmgr->display_config->multi_monitor_in_sync) || in vega10_apply_state_adjust_rules()
3405 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega10_apply_state_adjust_rules()
3432 static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) in vega10_find_dpm_states_clocks_in_dpm_table() argument
3434 struct vega10_hwmgr *data = hwmgr->backend; in vega10_find_dpm_states_clocks_in_dpm_table()
3475 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) in vega10_find_dpm_states_clocks_in_dpm_table()
3482 struct pp_hwmgr *hwmgr, const void *input) in vega10_populate_and_upload_sclk_mclk_dpm_levels() argument
3485 struct vega10_hwmgr *data = hwmgr->backend; in vega10_populate_and_upload_sclk_mclk_dpm_levels()
3494 if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { in vega10_populate_and_upload_sclk_mclk_dpm_levels()
3500 if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { in vega10_populate_and_upload_sclk_mclk_dpm_levels()
3507 result = vega10_populate_all_graphic_levels(hwmgr); in vega10_populate_and_upload_sclk_mclk_dpm_levels()
3515 result = vega10_populate_all_memory_levels(hwmgr); in vega10_populate_and_upload_sclk_mclk_dpm_levels()
3521 vega10_populate_vddc_soc_levels(hwmgr); in vega10_populate_and_upload_sclk_mclk_dpm_levels()
3526 static int vega10_trim_single_dpm_states(struct pp_hwmgr *hwmgr, in vega10_trim_single_dpm_states() argument
3542 static int vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr, in vega10_trim_single_dpm_states_with_mask() argument
3561 static int vega10_trim_dpm_states(struct pp_hwmgr *hwmgr, in vega10_trim_dpm_states() argument
3564 struct vega10_hwmgr *data = hwmgr->backend; in vega10_trim_dpm_states()
3573 vega10_trim_single_dpm_states(hwmgr, in vega10_trim_dpm_states()
3578 vega10_trim_single_dpm_states_with_mask(hwmgr, in vega10_trim_dpm_states()
3584 vega10_trim_single_dpm_states(hwmgr, in vega10_trim_dpm_states()
3624 struct pp_hwmgr *hwmgr) in vega10_apply_dal_minimum_voltage_request() argument
3629 static int vega10_get_soc_index_for_max_uclk(struct pp_hwmgr *hwmgr) in vega10_get_soc_index_for_max_uclk() argument
3633 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_get_soc_index_for_max_uclk()
3640 static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr) in vega10_upload_dpm_bootup_level() argument
3642 struct vega10_hwmgr *data = hwmgr->backend; in vega10_upload_dpm_bootup_level()
3645 vega10_apply_dal_minimum_voltage_request(hwmgr); in vega10_upload_dpm_bootup_level()
3650 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_upload_dpm_bootup_level()
3664 && hwmgr->not_vf) { in vega10_upload_dpm_bootup_level()
3665 socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr); in vega10_upload_dpm_bootup_level()
3666 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_upload_dpm_bootup_level()
3671 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_upload_dpm_bootup_level()
3681 if (!hwmgr->not_vf) in vega10_upload_dpm_bootup_level()
3687 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_upload_dpm_bootup_level()
3699 static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr) in vega10_upload_dpm_max_level() argument
3701 struct vega10_hwmgr *data = hwmgr->backend; in vega10_upload_dpm_max_level()
3703 vega10_apply_dal_minimum_voltage_request(hwmgr); in vega10_upload_dpm_max_level()
3708 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_upload_dpm_max_level()
3720 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_upload_dpm_max_level()
3729 if (!hwmgr->not_vf) in vega10_upload_dpm_max_level()
3735 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_upload_dpm_max_level()
3748 struct pp_hwmgr *hwmgr, const void *input) in vega10_generate_dpm_level_enable_mask() argument
3750 struct vega10_hwmgr *data = hwmgr->backend; in vega10_generate_dpm_level_enable_mask()
3760 PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps), in vega10_generate_dpm_level_enable_mask()
3777 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), in vega10_generate_dpm_level_enable_mask()
3780 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), in vega10_generate_dpm_level_enable_mask()
3796 int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) in vega10_enable_disable_vce_dpm() argument
3798 struct vega10_hwmgr *data = hwmgr->backend; in vega10_enable_disable_vce_dpm()
3801 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, in vega10_enable_disable_vce_dpm()
3812 static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr) in vega10_update_sclk_threshold() argument
3814 struct vega10_hwmgr *data = hwmgr->backend; in vega10_update_sclk_threshold()
3826 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_update_sclk_threshold()
3835 static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr, in vega10_set_power_state_tasks() argument
3839 struct vega10_hwmgr *data = hwmgr->backend; in vega10_set_power_state_tasks()
3842 tmp_result = vega10_find_dpm_states_clocks_in_dpm_table(hwmgr, input); in vega10_set_power_state_tasks()
3847 tmp_result = vega10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input); in vega10_set_power_state_tasks()
3852 tmp_result = vega10_generate_dpm_level_enable_mask(hwmgr, input); in vega10_set_power_state_tasks()
3857 tmp_result = vega10_update_sclk_threshold(hwmgr); in vega10_set_power_state_tasks()
3862 result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false); in vega10_set_power_state_tasks()
3870 if(hwmgr->hardcode_pp_table != NULL) in vega10_set_power_state_tasks()
3873 vega10_update_avfs(hwmgr); in vega10_set_power_state_tasks()
3884 static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) in vega10_dpm_get_sclk() argument
3889 if (hwmgr == NULL) in vega10_dpm_get_sclk()
3892 ps = hwmgr->request_ps; in vega10_dpm_get_sclk()
3906 static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) in vega10_dpm_get_mclk() argument
3911 if (hwmgr == NULL) in vega10_dpm_get_mclk()
3914 ps = hwmgr->request_ps; in vega10_dpm_get_mclk()
3928 static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr, in vega10_get_gpu_power() argument
3937 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr, &value); in vega10_get_gpu_power()
3947 static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx, in vega10_read_sensor() argument
3950 struct amdgpu_device *adev = hwmgr->adev; in vega10_read_sensor()
3952 struct vega10_hwmgr *data = hwmgr->backend; in vega10_read_sensor()
3959 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGfxclkActualFrequency, &sclk_mhz); in vega10_read_sensor()
3966 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &mclk_idx); in vega10_read_sensor()
3977 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0, in vega10_read_sensor()
3983 *((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr); in vega10_read_sensor()
3987 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHotspot, (uint32_t *)value); in vega10_read_sensor()
3993 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHBM, (uint32_t *)value); in vega10_read_sensor()
4007 ret = vega10_get_gpu_power(hwmgr, (uint32_t *)value); in vega10_read_sensor()
4016 ret = vega10_get_enabled_smc_features(hwmgr, (uint64_t *)value); in vega10_read_sensor()
4028 static void vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr, in vega10_notify_smc_display_change() argument
4031 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_notify_smc_display_change()
4037 static int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr, in vega10_display_clock_voltage_request() argument
4067 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_display_clock_voltage_request()
4076 static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr, in vega10_get_uclk_index() argument
4097 struct pp_hwmgr *hwmgr) in vega10_notify_smc_display_config_after_ps_adjustment() argument
4099 struct vega10_hwmgr *data = hwmgr->backend; in vega10_notify_smc_display_config_after_ps_adjustment()
4103 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega10_notify_smc_display_config_after_ps_adjustment()
4110 if ((hwmgr->display_config->num_display > 1) && in vega10_notify_smc_display_config_after_ps_adjustment()
4111 !hwmgr->display_config->multi_monitor_in_sync && in vega10_notify_smc_display_config_after_ps_adjustment()
4112 !hwmgr->display_config->nb_pstate_switch_disable) in vega10_notify_smc_display_config_after_ps_adjustment()
4113 vega10_notify_smc_display_change(hwmgr, false); in vega10_notify_smc_display_config_after_ps_adjustment()
4115 vega10_notify_smc_display_change(hwmgr, true); in vega10_notify_smc_display_config_after_ps_adjustment()
4117 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega10_notify_smc_display_config_after_ps_adjustment()
4118 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega10_notify_smc_display_config_after_ps_adjustment()
4119 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega10_notify_smc_display_config_after_ps_adjustment()
4129 if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) { in vega10_notify_smc_display_config_after_ps_adjustment()
4131 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk, in vega10_notify_smc_display_config_after_ps_adjustment()
4142 idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock); in vega10_notify_smc_display_config_after_ps_adjustment()
4143 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx, in vega10_notify_smc_display_config_after_ps_adjustment()
4151 static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr) in vega10_force_dpm_highest() argument
4153 struct vega10_hwmgr *data = hwmgr->backend; in vega10_force_dpm_highest()
4162 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), in vega10_force_dpm_highest()
4166 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), in vega10_force_dpm_highest()
4173 static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr) in vega10_force_dpm_lowest() argument
4175 struct vega10_hwmgr *data = hwmgr->backend; in vega10_force_dpm_lowest()
4184 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), in vega10_force_dpm_lowest()
4188 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), in vega10_force_dpm_lowest()
4196 static int vega10_unforce_dpm_levels(struct pp_hwmgr *hwmgr) in vega10_unforce_dpm_levels() argument
4198 struct vega10_hwmgr *data = hwmgr->backend; in vega10_unforce_dpm_levels()
4209 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), in vega10_unforce_dpm_levels()
4213 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), in vega10_unforce_dpm_levels()
4219 static int vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, in vega10_get_profiling_clk_mask() argument
4223 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_get_profiling_clk_mask()
4241 if (hwmgr->pp_one_vf) in vega10_get_profiling_clk_mask()
4252 static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) in vega10_set_fan_control_mode() argument
4254 if (!hwmgr->not_vf) in vega10_set_fan_control_mode()
4259 vega10_fan_ctrl_set_fan_speed_pwm(hwmgr, 255); in vega10_set_fan_control_mode()
4263 vega10_fan_ctrl_stop_smc_fan_control(hwmgr); in vega10_set_fan_control_mode()
4267 vega10_fan_ctrl_start_smc_fan_control(hwmgr); in vega10_set_fan_control_mode()
4274 static int vega10_force_clock_level(struct pp_hwmgr *hwmgr, in vega10_force_clock_level() argument
4277 struct vega10_hwmgr *data = hwmgr->backend; in vega10_force_clock_level()
4284 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), in vega10_force_clock_level()
4288 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), in vega10_force_clock_level()
4297 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), in vega10_force_clock_level()
4301 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), in vega10_force_clock_level()
4311 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), in vega10_force_clock_level()
4315 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), in vega10_force_clock_level()
4333 static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, in vega10_dpm_force_dpm_level() argument
4343 ret = vega10_force_dpm_highest(hwmgr); in vega10_dpm_force_dpm_level()
4346 ret = vega10_force_dpm_lowest(hwmgr); in vega10_dpm_force_dpm_level()
4349 ret = vega10_unforce_dpm_levels(hwmgr); in vega10_dpm_force_dpm_level()
4355 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega10_dpm_force_dpm_level()
4358 vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); in vega10_dpm_force_dpm_level()
4359 vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); in vega10_dpm_force_dpm_level()
4367 if (!hwmgr->not_vf) in vega10_dpm_force_dpm_level()
4371 …if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE… in vega10_dpm_force_dpm_level()
4372 vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE); in vega10_dpm_force_dpm_level()
4373 …else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PR… in vega10_dpm_force_dpm_level()
4374 vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO); in vega10_dpm_force_dpm_level()
4380 static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr) in vega10_get_fan_control_mode() argument
4382 struct vega10_hwmgr *data = hwmgr->backend; in vega10_get_fan_control_mode()
4390 static int vega10_get_dal_power_level(struct pp_hwmgr *hwmgr, in vega10_get_dal_power_level() argument
4394 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega10_get_dal_power_level()
4404 static void vega10_get_sclks(struct pp_hwmgr *hwmgr, in vega10_get_sclks() argument
4408 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega10_get_sclks()
4424 static void vega10_get_memclocks(struct pp_hwmgr *hwmgr, in vega10_get_memclocks() argument
4428 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega10_get_memclocks()
4431 struct vega10_hwmgr *data = hwmgr->backend; in vega10_get_memclocks()
4450 static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr, in vega10_get_dcefclocks() argument
4454 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega10_get_dcefclocks()
4466 static void vega10_get_socclocks(struct pp_hwmgr *hwmgr, in vega10_get_socclocks() argument
4470 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega10_get_socclocks()
4482 static int vega10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, in vega10_get_clock_by_type_with_latency() argument
4488 vega10_get_sclks(hwmgr, clocks); in vega10_get_clock_by_type_with_latency()
4491 vega10_get_memclocks(hwmgr, clocks); in vega10_get_clock_by_type_with_latency()
4494 vega10_get_dcefclocks(hwmgr, clocks); in vega10_get_clock_by_type_with_latency()
4497 vega10_get_socclocks(hwmgr, clocks); in vega10_get_clock_by_type_with_latency()
4506 static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, in vega10_get_clock_by_type_with_voltage() argument
4511 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega10_get_clock_by_type_with_voltage()
4548 static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, in vega10_set_watermarks_for_clocks_ranges() argument
4551 struct vega10_hwmgr *data = hwmgr->backend; in vega10_set_watermarks_for_clocks_ranges()
4563 static int vega10_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf) in vega10_get_ppfeature_status() argument
4607 ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled); in vega10_get_ppfeature_status()
4627 static int vega10_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks) in vega10_set_ppfeature_status() argument
4637 ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled); in vega10_set_ppfeature_status()
4650 ret = vega10_enable_smc_features(hwmgr, false, features_to_disable); in vega10_set_ppfeature_status()
4656 ret = vega10_enable_smc_features(hwmgr, true, features_to_enable); in vega10_set_ppfeature_status()
4664 static int vega10_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr) in vega10_get_current_pcie_link_width_level() argument
4666 struct amdgpu_device *adev = hwmgr->adev; in vega10_get_current_pcie_link_width_level()
4673 static int vega10_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr) in vega10_get_current_pcie_link_speed_level() argument
4675 struct amdgpu_device *adev = hwmgr->adev; in vega10_get_current_pcie_link_speed_level()
4682 static int vega10_emit_clock_levels(struct pp_hwmgr *hwmgr, in vega10_emit_clock_levels() argument
4685 struct vega10_hwmgr *data = hwmgr->backend; in vega10_emit_clock_levels()
4702 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex, &now); in vega10_emit_clock_levels()
4706 if (hwmgr->pp_one_vf && in vega10_emit_clock_levels()
4707 (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) in vega10_emit_clock_levels()
4720 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now); in vega10_emit_clock_levels()
4733 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now); in vega10_emit_clock_levels()
4746 ret = smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_emit_clock_levels()
4760 vega10_get_current_pcie_link_speed_level(hwmgr); in vega10_emit_clock_levels()
4762 vega10_get_current_pcie_link_width_level(hwmgr); in vega10_emit_clock_levels()
4785 if (!hwmgr->od_enabled) in vega10_emit_clock_levels()
4796 if (!hwmgr->od_enabled) in vega10_emit_clock_levels()
4807 if (!hwmgr->od_enabled) in vega10_emit_clock_levels()
4813 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); in vega10_emit_clock_levels()
4816 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); in vega10_emit_clock_levels()
4828 static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, in vega10_print_clock_levels() argument
4831 struct vega10_hwmgr *data = hwmgr->backend; in vega10_print_clock_levels()
4847 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex, &now); in vega10_print_clock_levels()
4851 if (hwmgr->pp_one_vf && in vega10_print_clock_levels()
4852 (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) in vega10_print_clock_levels()
4865 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now); in vega10_print_clock_levels()
4878 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now); in vega10_print_clock_levels()
4891 ret = smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_print_clock_levels()
4904 vega10_get_current_pcie_link_speed_level(hwmgr); in vega10_print_clock_levels()
4906 vega10_get_current_pcie_link_width_level(hwmgr); in vega10_print_clock_levels()
4929 if (hwmgr->od_enabled) { in vega10_print_clock_levels()
4939 if (hwmgr->od_enabled) { in vega10_print_clock_levels()
4949 if (hwmgr->od_enabled) { in vega10_print_clock_levels()
4953 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); in vega10_print_clock_levels()
4956 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); in vega10_print_clock_levels()
4968 static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr) in vega10_display_configuration_changed_task() argument
4970 struct vega10_hwmgr *data = hwmgr->backend; in vega10_display_configuration_changed_task()
4976 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false); in vega10_display_configuration_changed_task()
4982 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_display_configuration_changed_task()
4983 PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display, in vega10_display_configuration_changed_task()
4990 static int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) in vega10_enable_disable_uvd_dpm() argument
4992 struct vega10_hwmgr *data = hwmgr->backend; in vega10_enable_disable_uvd_dpm()
4995 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, in vega10_enable_disable_uvd_dpm()
5005 static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate) in vega10_power_gate_vce() argument
5007 struct vega10_hwmgr *data = hwmgr->backend; in vega10_power_gate_vce()
5010 vega10_enable_disable_vce_dpm(hwmgr, !bgate); in vega10_power_gate_vce()
5013 static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate) in vega10_power_gate_uvd() argument
5015 struct vega10_hwmgr *data = hwmgr->backend; in vega10_power_gate_uvd()
5018 vega10_enable_disable_uvd_dpm(hwmgr, !bgate); in vega10_power_gate_uvd()
5030 static int vega10_check_states_equal(struct pp_hwmgr *hwmgr, in vega10_check_states_equal() argument
5076 vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) in vega10_check_smc_update_required_for_display_configuration() argument
5078 struct vega10_hwmgr *data = hwmgr->backend; in vega10_check_smc_update_required_for_display_configuration()
5081 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) in vega10_check_smc_update_required_for_display_configuration()
5085 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr) in vega10_check_smc_update_required_for_display_configuration()
5092 static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) in vega10_disable_dpm_tasks() argument
5096 if (!hwmgr->not_vf) in vega10_disable_dpm_tasks()
5100 vega10_disable_thermal_protection(hwmgr); in vega10_disable_dpm_tasks()
5102 tmp_result = vega10_disable_power_containment(hwmgr); in vega10_disable_dpm_tasks()
5106 tmp_result = vega10_disable_didt_config(hwmgr); in vega10_disable_dpm_tasks()
5110 tmp_result = vega10_avfs_enable(hwmgr, false); in vega10_disable_dpm_tasks()
5114 tmp_result = vega10_stop_dpm(hwmgr, SMC_DPM_FEATURES); in vega10_disable_dpm_tasks()
5118 tmp_result = vega10_disable_deep_sleep_master_switch(hwmgr); in vega10_disable_dpm_tasks()
5122 tmp_result = vega10_disable_ulv(hwmgr); in vega10_disable_dpm_tasks()
5126 tmp_result = vega10_acg_disable(hwmgr); in vega10_disable_dpm_tasks()
5130 vega10_enable_disable_PCC_limit_feature(hwmgr, false); in vega10_disable_dpm_tasks()
5134 static int vega10_power_off_asic(struct pp_hwmgr *hwmgr) in vega10_power_off_asic() argument
5136 struct vega10_hwmgr *data = hwmgr->backend; in vega10_power_off_asic()
5139 result = vega10_disable_dpm_tasks(hwmgr); in vega10_power_off_asic()
5148 static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr) in vega10_get_sclk_od() argument
5150 struct vega10_hwmgr *data = hwmgr->backend; in vega10_get_sclk_od()
5164 static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) in vega10_set_sclk_od() argument
5166 struct vega10_hwmgr *data = hwmgr->backend; in vega10_set_sclk_od()
5172 ps = hwmgr->request_ps; in vega10_set_sclk_od()
5191 hwmgr->platform_descriptor.overdriveLimit.engineClock) { in vega10_set_sclk_od()
5194 hwmgr->platform_descriptor.overdriveLimit.engineClock; in vega10_set_sclk_od()
5196 hwmgr->platform_descriptor.overdriveLimit.engineClock); in vega10_set_sclk_od()
5201 static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr) in vega10_get_mclk_od() argument
5203 struct vega10_hwmgr *data = hwmgr->backend; in vega10_get_mclk_od()
5217 static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) in vega10_set_mclk_od() argument
5219 struct vega10_hwmgr *data = hwmgr->backend; in vega10_set_mclk_od()
5225 ps = hwmgr->request_ps; in vega10_set_mclk_od()
5244 hwmgr->platform_descriptor.overdriveLimit.memoryClock) { in vega10_set_mclk_od()
5247 hwmgr->platform_descriptor.overdriveLimit.memoryClock; in vega10_set_mclk_od()
5249 hwmgr->platform_descriptor.overdriveLimit.memoryClock); in vega10_set_mclk_od()
5255 static int vega10_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, in vega10_notify_cac_buffer_info() argument
5262 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_notify_cac_buffer_info()
5266 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_notify_cac_buffer_info()
5270 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_notify_cac_buffer_info()
5275 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_notify_cac_buffer_info()
5280 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_notify_cac_buffer_info()
5287 static int vega10_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, in vega10_get_thermal_temperature_range() argument
5290 struct vega10_hwmgr *data = hwmgr->backend; in vega10_get_thermal_temperature_range()
5293 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_get_thermal_temperature_range()
5321 static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) in vega10_get_power_profile_mode() argument
5323 struct vega10_hwmgr *data = hwmgr->backend; in vega10_get_power_profile_mode()
5349 i, amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ", in vega10_get_power_profile_mode()
5354 amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ", in vega10_get_power_profile_mode()
5360 static bool vega10_get_power_profile_mode_quirks(struct pp_hwmgr *hwmgr) in vega10_get_power_profile_mode_quirks() argument
5362 struct amdgpu_device *adev = hwmgr->adev; in vega10_get_power_profile_mode_quirks()
5367 static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) in vega10_set_power_profile_mode() argument
5369 struct vega10_hwmgr *data = hwmgr->backend; in vega10_set_power_profile_mode()
5395 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_set_power_profile_mode()
5403 if (vega10_get_power_profile_mode_quirks(hwmgr)) in vega10_set_power_profile_mode()
5404 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask, in vega10_set_power_profile_mode()
5408 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask, in vega10_set_power_profile_mode()
5412 hwmgr->power_profile_mode = power_profile_mode; in vega10_set_power_profile_mode()
5418 static bool vega10_check_clk_voltage_valid(struct pp_hwmgr *hwmgr, in vega10_check_clk_voltage_valid() argument
5423 struct vega10_hwmgr *data = hwmgr->backend; in vega10_check_clk_voltage_valid()
5435 hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) { in vega10_check_clk_voltage_valid()
5438 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); in vega10_check_clk_voltage_valid()
5444 hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) { in vega10_check_clk_voltage_valid()
5447 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); in vega10_check_clk_voltage_valid()
5457 static void vega10_odn_update_power_state(struct pp_hwmgr *hwmgr) in vega10_odn_update_power_state() argument
5459 struct vega10_hwmgr *data = hwmgr->backend; in vega10_odn_update_power_state()
5460 struct pp_power_state *ps = hwmgr->request_ps; in vega10_odn_update_power_state()
5494 if (!hwmgr->ps) in vega10_odn_update_power_state()
5497 ps = (struct pp_power_state *)((unsigned long)(hwmgr->ps) + hwmgr->ps_size * (hwmgr->num_ps - 1)); in vega10_odn_update_power_state()
5520 static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr, in vega10_odn_update_soc_table() argument
5523 struct vega10_hwmgr *data = hwmgr->backend; in vega10_odn_update_soc_table()
5524 struct phm_ppt_v2_information *table_info = hwmgr->pptable; in vega10_odn_update_soc_table()
5588 vega10_odn_update_power_state(hwmgr); in vega10_odn_update_soc_table()
5591 static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr, in vega10_odn_edit_dpm_table() argument
5595 struct vega10_hwmgr *data = hwmgr->backend; in vega10_odn_edit_dpm_table()
5607 if (!hwmgr->od_enabled) { in vega10_odn_edit_dpm_table()
5622 vega10_odn_initial_default_setting(hwmgr); in vega10_odn_edit_dpm_table()
5623 vega10_odn_update_power_state(hwmgr); in vega10_odn_edit_dpm_table()
5630 vega10_check_dpm_table_updated(hwmgr); in vega10_odn_edit_dpm_table()
5645 if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) { in vega10_odn_edit_dpm_table()
5653 vega10_odn_update_soc_table(hwmgr, type); in vega10_odn_edit_dpm_table()
5657 static int vega10_set_mp1_state(struct pp_hwmgr *hwmgr, in vega10_set_mp1_state() argument
5674 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0, in vega10_set_mp1_state()
5681 static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *sta… in vega10_get_performance_level() argument
5688 if (level == NULL || hwmgr == NULL || state == NULL) in vega10_get_performance_level()
5704 static int vega10_disable_power_features_for_compute_performance(struct pp_hwmgr *hwmgr, bool disab… in vega10_disable_power_features_for_compute_performance() argument
5706 struct vega10_hwmgr *data = hwmgr->backend; in vega10_disable_power_features_for_compute_performance()
5734 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, in vega10_disable_power_features_for_compute_performance()
5829 int vega10_hwmgr_init(struct pp_hwmgr *hwmgr) in vega10_hwmgr_init() argument
5831 struct amdgpu_device *adev = hwmgr->adev; in vega10_hwmgr_init()
5833 hwmgr->hwmgr_func = &vega10_hwmgr_funcs; in vega10_hwmgr_init()
5834 hwmgr->pptable_func = &vega10_pptable_funcs; in vega10_hwmgr_init()
5836 return vega10_baco_set_cap(hwmgr); in vega10_hwmgr_init()