Lines Matching refs:hwmgr
68 static uint32_t smu8_get_eclk_level(struct pp_hwmgr *hwmgr, in smu8_get_eclk_level() argument
73 hwmgr->dyn_state.vce_clock_voltage_dependency_table; in smu8_get_eclk_level()
99 static uint32_t smu8_get_sclk_level(struct pp_hwmgr *hwmgr, in smu8_get_sclk_level() argument
104 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_sclk_level()
129 static uint32_t smu8_get_uvd_level(struct pp_hwmgr *hwmgr, in smu8_get_uvd_level() argument
134 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; in smu8_get_uvd_level()
160 static uint32_t smu8_get_max_sclk_level(struct pp_hwmgr *hwmgr) in smu8_get_max_sclk_level() argument
162 struct smu8_hwmgr *data = hwmgr->backend; in smu8_get_max_sclk_level()
165 smum_send_msg_to_smc(hwmgr, in smu8_get_max_sclk_level()
174 static int smu8_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) in smu8_initialize_dpm_defaults() argument
176 struct smu8_hwmgr *data = hwmgr->backend; in smu8_initialize_dpm_defaults()
177 struct amdgpu_device *adev = hwmgr->adev; in smu8_initialize_dpm_defaults()
199 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
202 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
205 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
210 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
217 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
220 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
222 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
230 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
233 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
235 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
239 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
242 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
251 struct pp_hwmgr *hwmgr, uint16_t voltage) in smu8_convert_8Bit_index_to_voltage() argument
256 static int smu8_construct_max_power_limits_table(struct pp_hwmgr *hwmgr, in smu8_construct_max_power_limits_table() argument
259 struct smu8_hwmgr *data = hwmgr->backend; in smu8_construct_max_power_limits_table()
262 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_construct_max_power_limits_table()
266 table->vddc = smu8_convert_8Bit_index_to_voltage(hwmgr, in smu8_construct_max_power_limits_table()
274 struct pp_hwmgr *hwmgr, in smu8_init_dynamic_state_adjustment_rule_settings() argument
304 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; in smu8_init_dynamic_state_adjustment_rule_settings()
309 static int smu8_get_system_info_data(struct pp_hwmgr *hwmgr) in smu8_get_system_info_data() argument
311 struct smu8_hwmgr *data = hwmgr->backend; in smu8_get_system_info_data()
318 info = (ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *)smu_atom_get_data_table(hwmgr->adev, in smu8_get_system_info_data()
398 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in smu8_get_system_info_data()
404 smu8_construct_max_power_limits_table (hwmgr, in smu8_get_system_info_data()
405 &hwmgr->dyn_state.max_clock_voltage_on_ac); in smu8_get_system_info_data()
407 smu8_init_dynamic_state_adjustment_rule_settings(hwmgr, in smu8_get_system_info_data()
413 static int smu8_construct_boot_state(struct pp_hwmgr *hwmgr) in smu8_construct_boot_state() argument
415 struct smu8_hwmgr *data = hwmgr->backend; in smu8_construct_boot_state()
435 static int smu8_upload_pptable_to_smu(struct pp_hwmgr *hwmgr) in smu8_upload_pptable_to_smu() argument
444 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_upload_pptable_to_smu()
446 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk; in smu8_upload_pptable_to_smu()
448 hwmgr->dyn_state.acp_clock_voltage_dependency_table; in smu8_upload_pptable_to_smu()
450 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; in smu8_upload_pptable_to_smu()
452 hwmgr->dyn_state.vce_clock_voltage_dependency_table; in smu8_upload_pptable_to_smu()
454 if (!hwmgr->need_pp_table_upload) in smu8_upload_pptable_to_smu()
457 ret = smum_download_powerplay_table(hwmgr, &table); in smu8_upload_pptable_to_smu()
484 atomctrl_get_engine_pll_dividers_kong(hwmgr, in smu8_upload_pptable_to_smu()
501 atomctrl_get_engine_pll_dividers_kong(hwmgr, in smu8_upload_pptable_to_smu()
515 atomctrl_get_engine_pll_dividers_kong(hwmgr, in smu8_upload_pptable_to_smu()
527 atomctrl_get_engine_pll_dividers_kong(hwmgr, in smu8_upload_pptable_to_smu()
541 atomctrl_get_engine_pll_dividers_kong(hwmgr, in smu8_upload_pptable_to_smu()
549 ret = smum_upload_powerplay_table(hwmgr); in smu8_upload_pptable_to_smu()
554 static int smu8_init_sclk_limit(struct pp_hwmgr *hwmgr) in smu8_init_sclk_limit() argument
556 struct smu8_hwmgr *data = hwmgr->backend; in smu8_init_sclk_limit()
558 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_init_sclk_limit()
567 level = smu8_get_max_sclk_level(hwmgr) - 1; in smu8_init_sclk_limit()
580 static int smu8_init_uvd_limit(struct pp_hwmgr *hwmgr) in smu8_init_uvd_limit() argument
582 struct smu8_hwmgr *data = hwmgr->backend; in smu8_init_uvd_limit()
584 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; in smu8_init_uvd_limit()
595 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxUvdLevel, &level); in smu8_init_uvd_limit()
610 static int smu8_init_vce_limit(struct pp_hwmgr *hwmgr) in smu8_init_vce_limit() argument
612 struct smu8_hwmgr *data = hwmgr->backend; in smu8_init_vce_limit()
614 hwmgr->dyn_state.vce_clock_voltage_dependency_table; in smu8_init_vce_limit()
625 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxEclkLevel, &level); in smu8_init_vce_limit()
640 static int smu8_init_acp_limit(struct pp_hwmgr *hwmgr) in smu8_init_acp_limit() argument
642 struct smu8_hwmgr *data = hwmgr->backend; in smu8_init_acp_limit()
644 hwmgr->dyn_state.acp_clock_voltage_dependency_table; in smu8_init_acp_limit()
655 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxAclkLevel, &level); in smu8_init_acp_limit()
669 static void smu8_init_power_gate_state(struct pp_hwmgr *hwmgr) in smu8_init_power_gate_state() argument
671 struct smu8_hwmgr *data = hwmgr->backend; in smu8_init_power_gate_state()
679 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ACPPowerOFF, NULL); in smu8_init_power_gate_state()
685 static void smu8_init_sclk_threshold(struct pp_hwmgr *hwmgr) in smu8_init_sclk_threshold() argument
687 struct smu8_hwmgr *data = hwmgr->backend; in smu8_init_sclk_threshold()
692 static int smu8_update_sclk_limit(struct pp_hwmgr *hwmgr) in smu8_update_sclk_limit() argument
694 struct smu8_hwmgr *data = hwmgr->backend; in smu8_update_sclk_limit()
696 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_update_sclk_limit()
704 level = smu8_get_max_sclk_level(hwmgr) - 1; in smu8_update_sclk_limit()
711 clock = hwmgr->display_config->min_core_set_clock; in smu8_update_sclk_limit()
718 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_update_sclk_limit()
720 smu8_get_sclk_level(hwmgr, in smu8_update_sclk_limit()
729 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu8_update_sclk_limit()
733 stable_pstate_sclk = (hwmgr->dyn_state.max_clock_voltage_on_ac.mclk * in smu8_update_sclk_limit()
742 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_update_sclk_limit()
744 smu8_get_sclk_level(hwmgr, in smu8_update_sclk_limit()
750 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu8_update_sclk_limit()
754 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_update_sclk_limit()
756 smu8_get_sclk_level(hwmgr, in smu8_update_sclk_limit()
765 static int smu8_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr) in smu8_set_deep_sleep_sclk_threshold() argument
767 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu8_set_deep_sleep_sclk_threshold()
769 uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr; in smu8_set_deep_sleep_sclk_threshold()
775 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_set_deep_sleep_sclk_threshold()
784 static int smu8_set_watermark_threshold(struct pp_hwmgr *hwmgr) in smu8_set_watermark_threshold() argument
787 hwmgr->backend; in smu8_set_watermark_threshold()
789 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_set_watermark_threshold()
797 static int smu8_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock) in smu8_nbdpm_pstate_enable_disable() argument
799 struct smu8_hwmgr *hw_data = hwmgr->backend; in smu8_nbdpm_pstate_enable_disable()
805 return smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_nbdpm_pstate_enable_disable()
812 return smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_nbdpm_pstate_enable_disable()
822 static int smu8_disable_nb_dpm(struct pp_hwmgr *hwmgr) in smu8_disable_nb_dpm() argument
826 struct smu8_hwmgr *data = hwmgr->backend; in smu8_disable_nb_dpm()
830 smu8_nbdpm_pstate_enable_disable(hwmgr, true, true); in smu8_disable_nb_dpm()
833 hwmgr, in smu8_disable_nb_dpm()
844 static int smu8_enable_nb_dpm(struct pp_hwmgr *hwmgr) in smu8_enable_nb_dpm() argument
848 struct smu8_hwmgr *data = hwmgr->backend; in smu8_enable_nb_dpm()
855 hwmgr, in smu8_enable_nb_dpm()
866 static int smu8_update_low_mem_pstate(struct pp_hwmgr *hwmgr, const void *input) in smu8_update_low_mem_pstate() argument
870 struct smu8_hwmgr *hw_data = hwmgr->backend; in smu8_update_low_mem_pstate()
879 smu8_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch); in smu8_update_low_mem_pstate()
881 smu8_nbdpm_pstate_enable_disable(hwmgr, true, disable_switch); in smu8_update_low_mem_pstate()
883 smu8_nbdpm_pstate_enable_disable(hwmgr, enable_low_mem_state, disable_switch); in smu8_update_low_mem_pstate()
888 static int smu8_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) in smu8_set_power_state_tasks() argument
892 smu8_update_sclk_limit(hwmgr); in smu8_set_power_state_tasks()
893 smu8_set_deep_sleep_sclk_threshold(hwmgr); in smu8_set_power_state_tasks()
894 smu8_set_watermark_threshold(hwmgr); in smu8_set_power_state_tasks()
895 ret = smu8_enable_nb_dpm(hwmgr); in smu8_set_power_state_tasks()
898 smu8_update_low_mem_pstate(hwmgr, input); in smu8_set_power_state_tasks()
904 static int smu8_setup_asic_task(struct pp_hwmgr *hwmgr) in smu8_setup_asic_task() argument
908 ret = smu8_upload_pptable_to_smu(hwmgr); in smu8_setup_asic_task()
911 ret = smu8_init_sclk_limit(hwmgr); in smu8_setup_asic_task()
914 ret = smu8_init_uvd_limit(hwmgr); in smu8_setup_asic_task()
917 ret = smu8_init_vce_limit(hwmgr); in smu8_setup_asic_task()
920 ret = smu8_init_acp_limit(hwmgr); in smu8_setup_asic_task()
924 smu8_init_power_gate_state(hwmgr); in smu8_setup_asic_task()
925 smu8_init_sclk_threshold(hwmgr); in smu8_setup_asic_task()
930 static void smu8_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr) in smu8_power_up_display_clock_sys_pll() argument
932 struct smu8_hwmgr *hw_data = hwmgr->backend; in smu8_power_up_display_clock_sys_pll()
938 static void smu8_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr) in smu8_clear_nb_dpm_flag() argument
940 struct smu8_hwmgr *hw_data = hwmgr->backend; in smu8_clear_nb_dpm_flag()
945 static void smu8_reset_cc6_data(struct pp_hwmgr *hwmgr) in smu8_reset_cc6_data() argument
947 struct smu8_hwmgr *hw_data = hwmgr->backend; in smu8_reset_cc6_data()
955 static void smu8_program_voting_clients(struct pp_hwmgr *hwmgr) in smu8_program_voting_clients() argument
957 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu8_program_voting_clients()
962 static void smu8_clear_voting_clients(struct pp_hwmgr *hwmgr) in smu8_clear_voting_clients() argument
964 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu8_clear_voting_clients()
968 static int smu8_start_dpm(struct pp_hwmgr *hwmgr) in smu8_start_dpm() argument
970 struct smu8_hwmgr *data = hwmgr->backend; in smu8_start_dpm()
974 return smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_start_dpm()
980 static int smu8_stop_dpm(struct pp_hwmgr *hwmgr) in smu8_stop_dpm() argument
983 struct smu8_hwmgr *data = hwmgr->backend; in smu8_stop_dpm()
989 ret = smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_stop_dpm()
997 static int smu8_program_bootup_state(struct pp_hwmgr *hwmgr) in smu8_program_bootup_state() argument
999 struct smu8_hwmgr *data = hwmgr->backend; in smu8_program_bootup_state()
1004 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_program_bootup_state()
1006 smu8_get_sclk_level(hwmgr, in smu8_program_bootup_state()
1011 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_program_bootup_state()
1013 smu8_get_sclk_level(hwmgr, in smu8_program_bootup_state()
1021 static void smu8_reset_acp_boot_level(struct pp_hwmgr *hwmgr) in smu8_reset_acp_boot_level() argument
1023 struct smu8_hwmgr *data = hwmgr->backend; in smu8_reset_acp_boot_level()
1028 static void smu8_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) in smu8_populate_umdpstate_clocks() argument
1031 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_populate_umdpstate_clocks()
1033 hwmgr->pstate_sclk = table->entries[0].clk / 100; in smu8_populate_umdpstate_clocks()
1034 hwmgr->pstate_mclk = 0; in smu8_populate_umdpstate_clocks()
1036 hwmgr->pstate_sclk_peak = table->entries[table->count - 1].clk / 100; in smu8_populate_umdpstate_clocks()
1037 hwmgr->pstate_mclk_peak = 0; in smu8_populate_umdpstate_clocks()
1040 static int smu8_enable_dpm_tasks(struct pp_hwmgr *hwmgr) in smu8_enable_dpm_tasks() argument
1042 smu8_program_voting_clients(hwmgr); in smu8_enable_dpm_tasks()
1043 if (smu8_start_dpm(hwmgr)) in smu8_enable_dpm_tasks()
1045 smu8_program_bootup_state(hwmgr); in smu8_enable_dpm_tasks()
1046 smu8_reset_acp_boot_level(hwmgr); in smu8_enable_dpm_tasks()
1048 smu8_populate_umdpstate_clocks(hwmgr); in smu8_enable_dpm_tasks()
1053 static int smu8_disable_dpm_tasks(struct pp_hwmgr *hwmgr) in smu8_disable_dpm_tasks() argument
1055 smu8_disable_nb_dpm(hwmgr); in smu8_disable_dpm_tasks()
1057 smu8_clear_voting_clients(hwmgr); in smu8_disable_dpm_tasks()
1058 if (smu8_stop_dpm(hwmgr)) in smu8_disable_dpm_tasks()
1064 static int smu8_power_off_asic(struct pp_hwmgr *hwmgr) in smu8_power_off_asic() argument
1066 smu8_disable_dpm_tasks(hwmgr); in smu8_power_off_asic()
1067 smu8_power_up_display_clock_sys_pll(hwmgr); in smu8_power_off_asic()
1068 smu8_clear_nb_dpm_flag(hwmgr); in smu8_power_off_asic()
1069 smu8_reset_cc6_data(hwmgr); in smu8_power_off_asic()
1073 static int smu8_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, in smu8_apply_state_adjust_rules() argument
1079 struct smu8_hwmgr *data = hwmgr->backend; in smu8_apply_state_adjust_rules()
1093 clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ? in smu8_apply_state_adjust_rules()
1094 hwmgr->display_config->min_mem_set_clock : in smu8_apply_state_adjust_rules()
1098 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) in smu8_apply_state_adjust_rules()
1099 clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk; in smu8_apply_state_adjust_rules()
1102 || (hwmgr->display_config->num_display >= 3); in smu8_apply_state_adjust_rules()
1106 if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) in smu8_apply_state_adjust_rules()
1107 smu8_nbdpm_pstate_enable_disable(hwmgr, false, false); in smu8_apply_state_adjust_rules()
1108 else if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) in smu8_apply_state_adjust_rules()
1109 smu8_nbdpm_pstate_enable_disable(hwmgr, false, true); in smu8_apply_state_adjust_rules()
1120 static int smu8_hwmgr_backend_init(struct pp_hwmgr *hwmgr) in smu8_hwmgr_backend_init() argument
1129 hwmgr->backend = data; in smu8_hwmgr_backend_init()
1131 result = smu8_initialize_dpm_defaults(hwmgr); in smu8_hwmgr_backend_init()
1137 result = smu8_get_system_info_data(hwmgr); in smu8_hwmgr_backend_init()
1143 smu8_construct_boot_state(hwmgr); in smu8_hwmgr_backend_init()
1145 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = SMU8_MAX_HARDWARE_POWERLEVELS; in smu8_hwmgr_backend_init()
1150 static int smu8_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) in smu8_hwmgr_backend_fini() argument
1152 if (hwmgr != NULL) { in smu8_hwmgr_backend_fini()
1153 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); in smu8_hwmgr_backend_fini()
1154 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; in smu8_hwmgr_backend_fini()
1156 kfree(hwmgr->backend); in smu8_hwmgr_backend_fini()
1157 hwmgr->backend = NULL; in smu8_hwmgr_backend_fini()
1162 static int smu8_phm_force_dpm_highest(struct pp_hwmgr *hwmgr) in smu8_phm_force_dpm_highest() argument
1164 struct smu8_hwmgr *data = hwmgr->backend; in smu8_phm_force_dpm_highest()
1166 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_phm_force_dpm_highest()
1168 smu8_get_sclk_level(hwmgr, in smu8_phm_force_dpm_highest()
1173 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_phm_force_dpm_highest()
1175 smu8_get_sclk_level(hwmgr, in smu8_phm_force_dpm_highest()
1183 static int smu8_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr) in smu8_phm_unforce_dpm_levels() argument
1185 struct smu8_hwmgr *data = hwmgr->backend; in smu8_phm_unforce_dpm_levels()
1187 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_phm_unforce_dpm_levels()
1196 level = smu8_get_max_sclk_level(hwmgr) - 1; in smu8_phm_unforce_dpm_levels()
1206 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_phm_unforce_dpm_levels()
1208 smu8_get_sclk_level(hwmgr, in smu8_phm_unforce_dpm_levels()
1213 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_phm_unforce_dpm_levels()
1215 smu8_get_sclk_level(hwmgr, in smu8_phm_unforce_dpm_levels()
1223 static int smu8_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr) in smu8_phm_force_dpm_lowest() argument
1225 struct smu8_hwmgr *data = hwmgr->backend; in smu8_phm_force_dpm_lowest()
1227 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_phm_force_dpm_lowest()
1229 smu8_get_sclk_level(hwmgr, in smu8_phm_force_dpm_lowest()
1234 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_phm_force_dpm_lowest()
1236 smu8_get_sclk_level(hwmgr, in smu8_phm_force_dpm_lowest()
1244 static int smu8_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, in smu8_dpm_force_dpm_level() argument
1252 ret = smu8_phm_force_dpm_highest(hwmgr); in smu8_dpm_force_dpm_level()
1257 ret = smu8_phm_force_dpm_lowest(hwmgr); in smu8_dpm_force_dpm_level()
1260 ret = smu8_phm_unforce_dpm_levels(hwmgr); in smu8_dpm_force_dpm_level()
1271 static int smu8_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr) in smu8_dpm_powerdown_uvd() argument
1274 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UVDPowerOFF, NULL); in smu8_dpm_powerdown_uvd()
1278 static int smu8_dpm_powerup_uvd(struct pp_hwmgr *hwmgr) in smu8_dpm_powerup_uvd() argument
1282 hwmgr, in smu8_dpm_powerup_uvd()
1291 static int smu8_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr) in smu8_dpm_update_vce_dpm() argument
1293 struct smu8_hwmgr *data = hwmgr->backend; in smu8_dpm_update_vce_dpm()
1295 hwmgr->dyn_state.vce_clock_voltage_dependency_table; in smu8_dpm_update_vce_dpm()
1299 hwmgr->en_umd_pstate) { in smu8_dpm_update_vce_dpm()
1303 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_dpm_update_vce_dpm()
1305 smu8_get_eclk_level(hwmgr, in smu8_dpm_update_vce_dpm()
1311 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_dpm_update_vce_dpm()
1317 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_dpm_update_vce_dpm()
1325 static int smu8_dpm_powerdown_vce(struct pp_hwmgr *hwmgr) in smu8_dpm_powerdown_vce() argument
1328 return smum_send_msg_to_smc(hwmgr, in smu8_dpm_powerdown_vce()
1334 static int smu8_dpm_powerup_vce(struct pp_hwmgr *hwmgr) in smu8_dpm_powerup_vce() argument
1337 return smum_send_msg_to_smc(hwmgr, in smu8_dpm_powerup_vce()
1343 static uint32_t smu8_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) in smu8_dpm_get_mclk() argument
1345 struct smu8_hwmgr *data = hwmgr->backend; in smu8_dpm_get_mclk()
1350 static uint32_t smu8_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) in smu8_dpm_get_sclk() argument
1355 if (hwmgr == NULL) in smu8_dpm_get_sclk()
1358 ps = hwmgr->request_ps; in smu8_dpm_get_sclk()
1371 static int smu8_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, in smu8_dpm_patch_boot_state() argument
1374 struct smu8_hwmgr *data = hwmgr->backend; in smu8_dpm_patch_boot_state()
1386 struct pp_hwmgr *hwmgr, in smu8_dpm_get_pp_table_entry_callback() argument
1396 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_dpm_get_pp_table_entry_callback()
1399 if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1)) in smu8_dpm_get_pp_table_entry_callback()
1400 clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1); in smu8_dpm_get_pp_table_entry_callback()
1407 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { in smu8_dpm_get_pp_table_entry_callback()
1415 static int smu8_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr) in smu8_dpm_get_num_of_pp_table_entries() argument
1420 result = pp_tables_get_num_of_entries(hwmgr, &ret); in smu8_dpm_get_num_of_pp_table_entries()
1425 static int smu8_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr, in smu8_dpm_get_pp_table_entry() argument
1435 result = pp_tables_get_entry(hwmgr, entry, ps, in smu8_dpm_get_pp_table_entry()
1444 static int smu8_get_power_state_size(struct pp_hwmgr *hwmgr) in smu8_get_power_state_size() argument
1464 static int smu8_set_cpu_power_state(struct pp_hwmgr *hwmgr) in smu8_set_cpu_power_state() argument
1466 struct smu8_hwmgr *hw_data = hwmgr->backend; in smu8_set_cpu_power_state()
1488 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_set_cpu_power_state()
1498 static int smu8_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time, in smu8_store_cc6_data() argument
1501 struct smu8_hwmgr *hw_data = hwmgr->backend; in smu8_store_cc6_data()
1525 static int smu8_get_dal_power_level(struct pp_hwmgr *hwmgr, in smu8_get_dal_power_level() argument
1530 hwmgr->dyn_state.vddc_dep_on_dal_pwrl; in smu8_get_dal_power_level()
1532 &hwmgr->dyn_state.max_clock_voltage_on_ac; in smu8_get_dal_power_level()
1546 static int smu8_force_clock_level(struct pp_hwmgr *hwmgr, in smu8_force_clock_level() argument
1551 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_force_clock_level()
1555 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_force_clock_level()
1567 static int smu8_print_clock_levels(struct pp_hwmgr *hwmgr, in smu8_print_clock_levels() argument
1570 struct smu8_hwmgr *data = hwmgr->backend; in smu8_print_clock_levels()
1572 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_print_clock_levels()
1578 now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, in smu8_print_clock_levels()
1590 now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, in smu8_print_clock_levels()
1607 static int smu8_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, in smu8_get_performance_level() argument
1616 if (level == NULL || hwmgr == NULL || state == NULL) in smu8_get_performance_level()
1619 data = hwmgr->backend; in smu8_get_performance_level()
1639 …level->vddc = (smu8_convert_8Bit_index_to_voltage(hwmgr, ps->levels[level_index].vddcIndex) + 2) /… in smu8_get_performance_level()
1646 static int smu8_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, in smu8_get_current_shallow_sleep_clocks() argument
1657 static int smu8_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, in smu8_get_clock_by_type() argument
1660 struct smu8_hwmgr *data = hwmgr->backend; in smu8_get_clock_by_type()
1664 clocks->count = smu8_get_max_sclk_level(hwmgr); in smu8_get_clock_by_type()
1671 table = hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_clock_by_type()
1687 static int smu8_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks) in smu8_get_max_high_clocks() argument
1690 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_max_high_clocks()
1693 &hwmgr->dyn_state.max_clock_voltage_on_ac; in smu8_get_max_high_clocks()
1698 level = smu8_get_max_sclk_level(hwmgr) - 1; in smu8_get_max_high_clocks()
1710 static int smu8_thermal_get_temperature(struct pp_hwmgr *hwmgr) in smu8_thermal_get_temperature() argument
1713 uint32_t val = cgs_read_ind_register(hwmgr->device, in smu8_thermal_get_temperature()
1725 static int smu8_read_sensor(struct pp_hwmgr *hwmgr, int idx, in smu8_read_sensor() argument
1728 struct smu8_hwmgr *data = hwmgr->backend; in smu8_read_sensor()
1731 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_read_sensor()
1734 hwmgr->dyn_state.vce_clock_voltage_dependency_table; in smu8_read_sensor()
1737 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; in smu8_read_sensor()
1739 …uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGE… in smu8_read_sensor()
1741 …uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET… in smu8_read_sensor()
1743 …uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET… in smu8_read_sensor()
1764 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) & in smu8_read_sensor()
1766 vddnb = smu8_convert_8Bit_index_to_voltage(hwmgr, tmp) / 4; in smu8_read_sensor()
1770 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) & in smu8_read_sensor()
1772 vddgfx = smu8_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp) / 4; in smu8_read_sensor()
1812 result = smum_send_msg_to_smc(hwmgr, in smu8_read_sensor()
1828 *((uint32_t *)value) = smu8_thermal_get_temperature(hwmgr); in smu8_read_sensor()
1835 static int smu8_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, in smu8_notify_cac_buffer_info() argument
1842 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_notify_cac_buffer_info()
1846 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_notify_cac_buffer_info()
1850 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_notify_cac_buffer_info()
1854 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_notify_cac_buffer_info()
1859 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_notify_cac_buffer_info()
1866 static int smu8_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, in smu8_get_thermal_temperature_range() argument
1869 struct smu8_hwmgr *data = hwmgr->backend; in smu8_get_thermal_temperature_range()
1880 static int smu8_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) in smu8_enable_disable_uvd_dpm() argument
1882 struct smu8_hwmgr *data = hwmgr->backend; in smu8_enable_disable_uvd_dpm()
1886 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu8_enable_disable_uvd_dpm()
1890 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_enable_disable_uvd_dpm()
1897 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_enable_disable_uvd_dpm()
1905 static int smu8_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) in smu8_dpm_update_uvd_dpm() argument
1907 struct smu8_hwmgr *data = hwmgr->backend; in smu8_dpm_update_uvd_dpm()
1909 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; in smu8_dpm_update_uvd_dpm()
1914 hwmgr->en_umd_pstate) { in smu8_dpm_update_uvd_dpm()
1918 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_dpm_update_uvd_dpm()
1920 smu8_get_uvd_level(hwmgr, in smu8_dpm_update_uvd_dpm()
1925 smu8_enable_disable_uvd_dpm(hwmgr, true); in smu8_dpm_update_uvd_dpm()
1927 smu8_enable_disable_uvd_dpm(hwmgr, true); in smu8_dpm_update_uvd_dpm()
1930 smu8_enable_disable_uvd_dpm(hwmgr, false); in smu8_dpm_update_uvd_dpm()
1936 static int smu8_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) in smu8_enable_disable_vce_dpm() argument
1938 struct smu8_hwmgr *data = hwmgr->backend; in smu8_enable_disable_vce_dpm()
1942 hwmgr->platform_descriptor.platformCaps, in smu8_enable_disable_vce_dpm()
1946 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_enable_disable_vce_dpm()
1953 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_enable_disable_vce_dpm()
1963 static void smu8_dpm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate) in smu8_dpm_powergate_acp() argument
1965 struct smu8_hwmgr *data = hwmgr->backend; in smu8_dpm_powergate_acp()
1971 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ACPPowerOFF, NULL); in smu8_dpm_powergate_acp()
1973 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ACPPowerON, NULL); in smu8_dpm_powergate_acp()
1978 static void smu8_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) in smu8_dpm_powergate_uvd() argument
1980 struct smu8_hwmgr *data = hwmgr->backend; in smu8_dpm_powergate_uvd()
1981 struct amdgpu_device *adev = hwmgr->adev; in smu8_dpm_powergate_uvd()
1986 amdgpu_device_ip_set_powergating_state(hwmgr->adev, in smu8_dpm_powergate_uvd()
1989 amdgpu_device_ip_set_clockgating_state(hwmgr->adev, in smu8_dpm_powergate_uvd()
1992 smu8_dpm_update_uvd_dpm(hwmgr, true); in smu8_dpm_powergate_uvd()
1993 smu8_dpm_powerdown_uvd(hwmgr); in smu8_dpm_powergate_uvd()
1995 smu8_dpm_powerup_uvd(hwmgr); in smu8_dpm_powergate_uvd()
1996 amdgpu_device_ip_set_clockgating_state(hwmgr->adev, in smu8_dpm_powergate_uvd()
1999 amdgpu_device_ip_set_powergating_state(hwmgr->adev, in smu8_dpm_powergate_uvd()
2002 smu8_dpm_update_uvd_dpm(hwmgr, false); in smu8_dpm_powergate_uvd()
2008 smu8_nbdpm_pstate_enable_disable(hwmgr, in smu8_dpm_powergate_uvd()
2013 static void smu8_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) in smu8_dpm_powergate_vce() argument
2015 struct smu8_hwmgr *data = hwmgr->backend; in smu8_dpm_powergate_vce()
2018 amdgpu_device_ip_set_powergating_state(hwmgr->adev, in smu8_dpm_powergate_vce()
2021 amdgpu_device_ip_set_clockgating_state(hwmgr->adev, in smu8_dpm_powergate_vce()
2024 smu8_enable_disable_vce_dpm(hwmgr, false); in smu8_dpm_powergate_vce()
2025 smu8_dpm_powerdown_vce(hwmgr); in smu8_dpm_powergate_vce()
2028 smu8_dpm_powerup_vce(hwmgr); in smu8_dpm_powergate_vce()
2030 amdgpu_device_ip_set_clockgating_state(hwmgr->adev, in smu8_dpm_powergate_vce()
2033 amdgpu_device_ip_set_powergating_state(hwmgr->adev, in smu8_dpm_powergate_vce()
2036 smu8_dpm_update_vce_dpm(hwmgr); in smu8_dpm_powergate_vce()
2037 smu8_enable_disable_vce_dpm(hwmgr, true); in smu8_dpm_powergate_vce()
2075 int smu8_init_function_pointers(struct pp_hwmgr *hwmgr) in smu8_init_function_pointers() argument
2077 hwmgr->hwmgr_func = &smu8_hwmgr_funcs; in smu8_init_function_pointers()
2078 hwmgr->pptable_func = &pptable_funcs; in smu8_init_function_pointers()