28 static int smu7_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)  in smu7_enable_disable_uvd_dpm()  argument
30 	return smum_send_msg_to_smc(hwmgr, enable ?  in smu7_enable_disable_uvd_dpm()
36 static int smu7_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)  in smu7_enable_disable_vce_dpm()  argument
38 	return smum_send_msg_to_smc(hwmgr, enable ?  in smu7_enable_disable_vce_dpm()
44 static int smu7_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)  in smu7_update_uvd_dpm()  argument
47 		smum_update_smc_table(hwmgr, SMU_UVD_TABLE);  in smu7_update_uvd_dpm()
48 	return smu7_enable_disable_uvd_dpm(hwmgr, !bgate);  in smu7_update_uvd_dpm()
51 static int smu7_update_vce_dpm(struct pp_hwmgr *hwmgr, bool bgate)  in smu7_update_vce_dpm()  argument
54 		smum_update_smc_table(hwmgr, SMU_VCE_TABLE);  in smu7_update_vce_dpm()
55 	return smu7_enable_disable_vce_dpm(hwmgr, !bgate);  in smu7_update_vce_dpm()
58 int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr)  in smu7_powerdown_uvd()  argument
60 	if (phm_cf_want_uvd_power_gating(hwmgr))  in smu7_powerdown_uvd()
61 		return smum_send_msg_to_smc(hwmgr,  in smu7_powerdown_uvd()
67 static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)  in smu7_powerup_uvd()  argument
69 	if (phm_cf_want_uvd_power_gating(hwmgr)) {  in smu7_powerup_uvd()
70 		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,  in smu7_powerup_uvd()
72 			return smum_send_msg_to_smc_with_parameter(hwmgr,  in smu7_powerup_uvd()
75 			return smum_send_msg_to_smc_with_parameter(hwmgr,  in smu7_powerup_uvd()
83 static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)  in smu7_powerdown_vce()  argument
85 	if (phm_cf_want_vce_power_gating(hwmgr))  in smu7_powerdown_vce()
86 		return smum_send_msg_to_smc(hwmgr,  in smu7_powerdown_vce()
92 static int smu7_powerup_vce(struct pp_hwmgr *hwmgr)  in smu7_powerup_vce()  argument
94 	if (phm_cf_want_vce_power_gating(hwmgr))  in smu7_powerup_vce()
95 		return smum_send_msg_to_smc(hwmgr,  in smu7_powerup_vce()
101 int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr)  in smu7_disable_clock_power_gating()  argument
103 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);  in smu7_disable_clock_power_gating()
108 	smu7_powerup_uvd(hwmgr);  in smu7_disable_clock_power_gating()
109 	smu7_powerup_vce(hwmgr);  in smu7_disable_clock_power_gating()
114 void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)  in smu7_powergate_uvd()  argument
116 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);  in smu7_powergate_uvd()
121 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,  in smu7_powergate_uvd()
124 		amdgpu_device_ip_set_clockgating_state(hwmgr->adev,  in smu7_powergate_uvd()
127 		smu7_update_uvd_dpm(hwmgr, true);  in smu7_powergate_uvd()
128 		smu7_powerdown_uvd(hwmgr);  in smu7_powergate_uvd()
130 		smu7_powerup_uvd(hwmgr);  in smu7_powergate_uvd()
131 		amdgpu_device_ip_set_clockgating_state(hwmgr->adev,  in smu7_powergate_uvd()
134 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,  in smu7_powergate_uvd()
137 		smu7_update_uvd_dpm(hwmgr, false);  in smu7_powergate_uvd()
142 void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)  in smu7_powergate_vce()  argument
144 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);  in smu7_powergate_vce()
149 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,  in smu7_powergate_vce()
152 		amdgpu_device_ip_set_clockgating_state(hwmgr->adev,  in smu7_powergate_vce()
155 		smu7_update_vce_dpm(hwmgr, true);  in smu7_powergate_vce()
156 		smu7_powerdown_vce(hwmgr);  in smu7_powergate_vce()
158 		smu7_powerup_vce(hwmgr);  in smu7_powergate_vce()
159 		amdgpu_device_ip_set_clockgating_state(hwmgr->adev,  in smu7_powergate_vce()
162 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,  in smu7_powergate_vce()
165 		smu7_update_vce_dpm(hwmgr, false);  in smu7_powergate_vce()
169 int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,  in smu7_update_clock_gatings()  argument
175 	if (!(hwmgr->feature_mask & PP_ENABLE_GFX_CG_THRU_SMU))  in smu7_update_clock_gatings()
189 						hwmgr, msg, value, NULL))  in smu7_update_clock_gatings()
199 						hwmgr, msg, value, NULL))  in smu7_update_clock_gatings()
212 						hwmgr, msg, value, NULL))  in smu7_update_clock_gatings()
223 						hwmgr, msg, value, NULL))  in smu7_update_clock_gatings()
236 						hwmgr, msg, value, NULL))  in smu7_update_clock_gatings()
249 						hwmgr, msg, value, NULL))  in smu7_update_clock_gatings()
263 						hwmgr, msg, value, NULL))  in smu7_update_clock_gatings()
283 						hwmgr, msg, value, NULL))  in smu7_update_clock_gatings()
293 						hwmgr, msg, value, NULL))  in smu7_update_clock_gatings()
306 						hwmgr, msg, value, NULL))  in smu7_update_clock_gatings()
317 						hwmgr, msg, value, NULL))  in smu7_update_clock_gatings()
330 						hwmgr, msg, value, NULL))  in smu7_update_clock_gatings()
340 						hwmgr, msg, value, NULL))  in smu7_update_clock_gatings()
353 						hwmgr, msg, value, NULL))  in smu7_update_clock_gatings()
364 						hwmgr, msg, value, NULL))  in smu7_update_clock_gatings()
377 						hwmgr, msg, value, NULL))  in smu7_update_clock_gatings()
388 						hwmgr, msg, value, NULL))  in smu7_update_clock_gatings()
401 						hwmgr, msg, value, NULL))  in smu7_update_clock_gatings()
424 int smu7_powergate_gfx(struct pp_hwmgr *hwmgr, bool enable)  in smu7_powergate_gfx()  argument
426 	struct amdgpu_device *adev = hwmgr->adev;  in smu7_powergate_gfx()
429 		return smum_send_msg_to_smc_with_parameter(hwmgr,  in smu7_powergate_gfx()
434 		return smum_send_msg_to_smc(hwmgr,  in smu7_powergate_gfx()