Lines Matching refs:hwmgr
51 static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr, in smu10_display_clock_voltage_request() argument
54 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_display_clock_voltage_request()
79 smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq, NULL); in smu10_display_clock_voltage_request()
101 static int smu10_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) in smu10_initialize_dpm_defaults() argument
103 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_initialize_dpm_defaults()
113 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in smu10_initialize_dpm_defaults()
116 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in smu10_initialize_dpm_defaults()
119 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in smu10_initialize_dpm_defaults()
124 static int smu10_construct_max_power_limits_table(struct pp_hwmgr *hwmgr, in smu10_construct_max_power_limits_table() argument
131 struct pp_hwmgr *hwmgr) in smu10_init_dynamic_state_adjustment_rule_settings() argument
161 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; in smu10_init_dynamic_state_adjustment_rule_settings()
166 static int smu10_get_system_info_data(struct pp_hwmgr *hwmgr) in smu10_get_system_info_data() argument
168 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)hwmgr->backend; in smu10_get_system_info_data()
176 smu10_construct_max_power_limits_table (hwmgr, in smu10_get_system_info_data()
177 &hwmgr->dyn_state.max_clock_voltage_on_ac); in smu10_get_system_info_data()
179 smu10_init_dynamic_state_adjustment_rule_settings(hwmgr); in smu10_get_system_info_data()
184 static int smu10_construct_boot_state(struct pp_hwmgr *hwmgr) in smu10_construct_boot_state() argument
189 static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input) in smu10_set_clock_limit() argument
194 clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in smu10_set_clock_limit()
198 PP_ASSERT_WITH_CODE(!smu10_display_clock_voltage_request(hwmgr, &clock_req), in smu10_set_clock_limit()
204 static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock) in smu10_set_min_deep_sleep_dcefclk() argument
206 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_set_min_deep_sleep_dcefclk()
210 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_set_min_deep_sleep_dcefclk()
218 static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock) in smu10_set_hard_min_dcefclk_by_freq() argument
220 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_set_hard_min_dcefclk_by_freq()
224 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_set_hard_min_dcefclk_by_freq()
232 static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock) in smu10_set_hard_min_fclk_by_freq() argument
234 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_set_hard_min_fclk_by_freq()
238 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_set_hard_min_fclk_by_freq()
246 static int smu10_set_hard_min_gfxclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock) in smu10_set_hard_min_gfxclk_by_freq() argument
248 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_set_hard_min_gfxclk_by_freq()
252 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_set_hard_min_gfxclk_by_freq()
260 static int smu10_set_soft_max_gfxclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock) in smu10_set_soft_max_gfxclk_by_freq() argument
262 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_set_soft_max_gfxclk_by_freq()
266 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_set_soft_max_gfxclk_by_freq()
274 static int smu10_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count) in smu10_set_active_display_count() argument
276 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_set_active_display_count()
280 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_set_active_display_count()
289 static int smu10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) in smu10_set_power_state_tasks() argument
291 return smu10_set_clock_limit(hwmgr, input); in smu10_set_power_state_tasks()
294 static int smu10_init_power_gate_state(struct pp_hwmgr *hwmgr) in smu10_init_power_gate_state() argument
296 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_init_power_gate_state()
297 struct amdgpu_device *adev = hwmgr->adev; in smu10_init_power_gate_state()
304 return smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_init_power_gate_state()
313 static int smu10_setup_asic_task(struct pp_hwmgr *hwmgr) in smu10_setup_asic_task() argument
315 return smu10_init_power_gate_state(hwmgr); in smu10_setup_asic_task()
318 static int smu10_reset_cc6_data(struct pp_hwmgr *hwmgr) in smu10_reset_cc6_data() argument
320 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_reset_cc6_data()
330 static int smu10_power_off_asic(struct pp_hwmgr *hwmgr) in smu10_power_off_asic() argument
332 return smu10_reset_cc6_data(hwmgr); in smu10_power_off_asic()
335 static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr) in smu10_is_gfx_on() argument
338 struct amdgpu_device *adev = hwmgr->adev; in smu10_is_gfx_on()
348 static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr) in smu10_disable_gfx_off() argument
350 struct amdgpu_device *adev = hwmgr->adev; in smu10_disable_gfx_off()
353 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff, NULL); in smu10_disable_gfx_off()
356 while (!smu10_is_gfx_on(hwmgr)) in smu10_disable_gfx_off()
363 static int smu10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) in smu10_disable_dpm_tasks() argument
368 static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr) in smu10_enable_gfx_off() argument
370 struct amdgpu_device *adev = hwmgr->adev; in smu10_enable_gfx_off()
373 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableGfxOff, NULL); in smu10_enable_gfx_off()
378 static void smu10_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) in smu10_populate_umdpstate_clocks() argument
380 hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK; in smu10_populate_umdpstate_clocks()
381 hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK; in smu10_populate_umdpstate_clocks()
383 smum_send_msg_to_smc(hwmgr, in smu10_populate_umdpstate_clocks()
385 &hwmgr->pstate_sclk_peak); in smu10_populate_umdpstate_clocks()
386 hwmgr->pstate_mclk_peak = SMU10_UMD_PSTATE_PEAK_FCLK; in smu10_populate_umdpstate_clocks()
389 static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) in smu10_enable_dpm_tasks() argument
391 struct amdgpu_device *adev = hwmgr->adev; in smu10_enable_dpm_tasks()
392 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_enable_dpm_tasks()
398 ret = smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_enable_dpm_tasks()
404 ret = smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_enable_dpm_tasks()
412 smu10_populate_umdpstate_clocks(hwmgr); in smu10_enable_dpm_tasks()
417 static int smu10_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable) in smu10_gfx_off_control() argument
420 return smu10_enable_gfx_off(hwmgr); in smu10_gfx_off_control()
422 return smu10_disable_gfx_off(hwmgr); in smu10_gfx_off_control()
425 static int smu10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, in smu10_apply_state_adjust_rules() argument
469 static int smu10_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr, in smu10_get_clock_voltage_dependency_table() argument
494 static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr) in smu10_populate_clock_table() argument
498 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_populate_clock_table()
502 result = smum_smc_table_manager(hwmgr, (uint8_t *)table, SMU10_CLOCKTABLE, true); in smu10_populate_clock_table()
509 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk, in smu10_populate_clock_table()
512 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk, in smu10_populate_clock_table()
515 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk, in smu10_populate_clock_table()
518 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk, in smu10_populate_clock_table()
522 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk, in smu10_populate_clock_table()
525 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk, in smu10_populate_clock_table()
528 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk, in smu10_populate_clock_table()
532 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dispclk, in smu10_populate_clock_table()
535 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dppclk, in smu10_populate_clock_table()
537 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk, in smu10_populate_clock_table()
540 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &result); in smu10_populate_clock_table()
543 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &result); in smu10_populate_clock_table()
549 static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) in smu10_hwmgr_backend_init() argument
558 hwmgr->backend = data; in smu10_hwmgr_backend_init()
560 result = smu10_initialize_dpm_defaults(hwmgr); in smu10_hwmgr_backend_init()
566 smu10_populate_clock_table(hwmgr); in smu10_hwmgr_backend_init()
568 result = smu10_get_system_info_data(hwmgr); in smu10_hwmgr_backend_init()
574 smu10_construct_boot_state(hwmgr); in smu10_hwmgr_backend_init()
576 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = in smu10_hwmgr_backend_init()
579 hwmgr->platform_descriptor.hardwarePerformanceLevels = in smu10_hwmgr_backend_init()
582 hwmgr->platform_descriptor.vbiosInterruptId = 0; in smu10_hwmgr_backend_init()
584 hwmgr->platform_descriptor.clockStep.engineClock = 500; in smu10_hwmgr_backend_init()
586 hwmgr->platform_descriptor.clockStep.memoryClock = 500; in smu10_hwmgr_backend_init()
588 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; in smu10_hwmgr_backend_init()
591 hwmgr->od_enabled = 1; in smu10_hwmgr_backend_init()
597 static int smu10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) in smu10_hwmgr_backend_fini() argument
599 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_hwmgr_backend_fini()
615 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); in smu10_hwmgr_backend_fini()
616 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; in smu10_hwmgr_backend_fini()
618 kfree(hwmgr->backend); in smu10_hwmgr_backend_fini()
619 hwmgr->backend = NULL; in smu10_hwmgr_backend_fini()
624 static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, in smu10_dpm_force_dpm_level() argument
627 struct smu10_hwmgr *data = hwmgr->backend; in smu10_dpm_force_dpm_level()
628 uint32_t min_sclk = hwmgr->display_config->min_core_set_clock; in smu10_dpm_force_dpm_level()
629 uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100; in smu10_dpm_force_dpm_level()
634 if (hwmgr->smu_version < 0x1E3700) { in smu10_dpm_force_dpm_level()
651 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq); in smu10_dpm_force_dpm_level()
652 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq); in smu10_dpm_force_dpm_level()
657 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
661 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
665 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
669 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
674 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
678 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
682 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
686 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
694 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq); in smu10_dpm_force_dpm_level()
695 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq); in smu10_dpm_force_dpm_level()
700 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
704 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
712 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq); in smu10_dpm_force_dpm_level()
713 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq); in smu10_dpm_force_dpm_level()
718 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
722 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
730 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq); in smu10_dpm_force_dpm_level()
731 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq); in smu10_dpm_force_dpm_level()
736 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
740 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
744 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
748 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
753 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
757 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
761 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
765 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
773 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq); in smu10_dpm_force_dpm_level()
774 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq); in smu10_dpm_force_dpm_level()
779 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
783 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
785 hwmgr->display_config->num_display > 3 ? in smu10_dpm_force_dpm_level()
790 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
794 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
799 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
803 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
807 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
811 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
819 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq); in smu10_dpm_force_dpm_level()
820 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq); in smu10_dpm_force_dpm_level()
825 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
829 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
833 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
837 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_dpm_force_dpm_level()
852 static uint32_t smu10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) in smu10_dpm_get_mclk() argument
856 if (hwmgr == NULL) in smu10_dpm_get_mclk()
859 data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_dpm_get_mclk()
868 static uint32_t smu10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) in smu10_dpm_get_sclk() argument
872 if (hwmgr == NULL) in smu10_dpm_get_sclk()
875 data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_dpm_get_sclk()
883 static int smu10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, in smu10_dpm_patch_boot_state() argument
890 struct pp_hwmgr *hwmgr, in smu10_dpm_get_pp_table_entry_callback() argument
902 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { in smu10_dpm_get_pp_table_entry_callback()
910 static int smu10_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr) in smu10_dpm_get_num_of_pp_table_entries() argument
915 result = pp_tables_get_num_of_entries(hwmgr, &ret); in smu10_dpm_get_num_of_pp_table_entries()
920 static int smu10_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr, in smu10_dpm_get_pp_table_entry() argument
930 result = pp_tables_get_entry(hwmgr, entry, ps, in smu10_dpm_get_pp_table_entry()
939 static int smu10_get_power_state_size(struct pp_hwmgr *hwmgr) in smu10_get_power_state_size() argument
944 static int smu10_set_cpu_power_state(struct pp_hwmgr *hwmgr) in smu10_set_cpu_power_state() argument
950 static int smu10_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time, in smu10_store_cc6_data() argument
953 struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_store_cc6_data()
966 static int smu10_get_dal_power_level(struct pp_hwmgr *hwmgr, in smu10_get_dal_power_level() argument
972 static int smu10_force_clock_level(struct pp_hwmgr *hwmgr, in smu10_force_clock_level() argument
975 struct smu10_hwmgr *data = hwmgr->backend; in smu10_force_clock_level()
990 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_force_clock_level()
997 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_force_clock_level()
1009 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_force_clock_level()
1014 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_force_clock_level()
1027 static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr, in smu10_print_clock_levels() argument
1030 struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_print_clock_levels()
1039 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &now); in smu10_print_clock_levels()
1062 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &now); in smu10_print_clock_levels()
1074 if (hwmgr->od_enabled) { in smu10_print_clock_levels()
1075 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq); in smu10_print_clock_levels()
1078 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq); in smu10_print_clock_levels()
1090 if (hwmgr->od_enabled) { in smu10_print_clock_levels()
1091 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq); in smu10_print_clock_levels()
1094 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq); in smu10_print_clock_levels()
1110 static int smu10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *stat… in smu10_get_performance_level() argument
1116 if (level == NULL || hwmgr == NULL || state == NULL) in smu10_get_performance_level()
1119 data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_get_performance_level()
1136 static int smu10_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, in smu10_get_current_shallow_sleep_clocks() argument
1154 static uint32_t smu10_get_mem_latency(struct pp_hwmgr *hwmgr, in smu10_get_mem_latency() argument
1166 static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, in smu10_get_clock_by_type_with_latency() argument
1171 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_get_clock_by_type_with_latency()
1213 smu10_get_mem_latency(hwmgr, in smu10_get_clock_by_type_with_latency()
1223 static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, in smu10_get_clock_by_type_with_voltage() argument
1228 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_get_clock_by_type_with_voltage()
1275 static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clock… in smu10_get_max_high_clocks() argument
1281 static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr) in smu10_thermal_get_temperature() argument
1283 struct amdgpu_device *adev = hwmgr->adev; in smu10_thermal_get_temperature()
1296 static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx, in smu10_read_sensor() argument
1299 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_read_sensor()
1300 struct amdgpu_device *adev = hwmgr->adev; in smu10_read_sensor()
1307 (hwmgr->smu_version >= 0x41e3b)) in smu10_read_sensor()
1310 (hwmgr->smu_version >= 0x1e5500)) in smu10_read_sensor()
1317 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &sclk); in smu10_read_sensor()
1325 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &mclk); in smu10_read_sensor()
1333 *((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr); in smu10_read_sensor()
1343 ret = smum_send_msg_to_smc(hwmgr, in smu10_read_sensor()
1360 static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, in smu10_set_watermarks_for_clocks_ranges() argument
1363 struct smu10_hwmgr *data = hwmgr->backend; in smu10_set_watermarks_for_clocks_ranges()
1366 struct amdgpu_device *adev = hwmgr->adev; in smu10_set_watermarks_for_clocks_ranges()
1379 smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false); in smu10_set_watermarks_for_clocks_ranges()
1384 static int smu10_smus_notify_pwe(struct pp_hwmgr *hwmgr) in smu10_smus_notify_pwe() argument
1387 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SetRccPfcPmeRestoreRegister, NULL); in smu10_smus_notify_pwe()
1390 static int smu10_powergate_mmhub(struct pp_hwmgr *hwmgr) in smu10_powergate_mmhub() argument
1392 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub, NULL); in smu10_powergate_mmhub()
1395 static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate) in smu10_powergate_sdma() argument
1398 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerDownSdma, NULL); in smu10_powergate_sdma()
1400 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerUpSdma, NULL); in smu10_powergate_sdma()
1403 static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate) in smu10_powergate_vcn() argument
1405 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_powergate_vcn()
1408 amdgpu_device_ip_set_powergating_state(hwmgr->adev, in smu10_powergate_vcn()
1411 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_powergate_vcn()
1415 smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_powergate_vcn()
1417 amdgpu_device_ip_set_powergating_state(hwmgr->adev, in smu10_powergate_vcn()
1449 static int smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) in smu10_get_power_profile_mode() argument
1477 i, amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ", in smu10_get_power_profile_mode()
1484 static bool smu10_is_raven1_refresh(struct pp_hwmgr *hwmgr) in smu10_is_raven1_refresh() argument
1486 struct amdgpu_device *adev = hwmgr->adev; in smu10_is_raven1_refresh()
1488 (hwmgr->smu_version >= 0x41e2b)) in smu10_is_raven1_refresh()
1494 static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) in smu10_set_power_profile_mode() argument
1503 if (hwmgr->power_profile_mode == input[size]) in smu10_set_power_profile_mode()
1510 smu10_is_raven1_refresh(hwmgr) && in smu10_set_power_profile_mode()
1511 !hwmgr->gfxoff_state_changed_by_workload) { in smu10_set_power_profile_mode()
1512 smu10_gfx_off_control(hwmgr, false); in smu10_set_power_profile_mode()
1513 hwmgr->gfxoff_state_changed_by_workload = true; in smu10_set_power_profile_mode()
1515 result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ActiveProcessNotify, in smu10_set_power_profile_mode()
1519 hwmgr->power_profile_mode = input[size]; in smu10_set_power_profile_mode()
1520 if (workload_type && hwmgr->gfxoff_state_changed_by_workload) { in smu10_set_power_profile_mode()
1521 smu10_gfx_off_control(hwmgr, true); in smu10_set_power_profile_mode()
1522 hwmgr->gfxoff_state_changed_by_workload = false; in smu10_set_power_profile_mode()
1528 static int smu10_asic_reset(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode) in smu10_asic_reset() argument
1530 return smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_asic_reset()
1536 static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr, in smu10_set_fine_grain_clk_vol() argument
1541 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_set_fine_grain_clk_vol()
1544 if (!hwmgr->od_enabled) { in smu10_set_fine_grain_clk_vol()
1561 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq); in smu10_set_fine_grain_clk_vol()
1572 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq); in smu10_set_fine_grain_clk_vol()
1590 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq); in smu10_set_fine_grain_clk_vol()
1595 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq); in smu10_set_fine_grain_clk_vol()
1612 ret = smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_set_fine_grain_clk_vol()
1619 ret = smum_send_msg_to_smc_with_parameter(hwmgr, in smu10_set_fine_grain_clk_vol()
1632 static int smu10_gfx_state_change(struct pp_hwmgr *hwmgr, uint32_t state) in smu10_gfx_state_change() argument
1634 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GpuChangeState, state, NULL); in smu10_gfx_state_change()
1688 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr) in smu10_init_function_pointers() argument
1690 hwmgr->hwmgr_func = &smu10_hwmgr_funcs; in smu10_init_function_pointers()
1691 hwmgr->pptable_func = &pptable_funcs; in smu10_init_function_pointers()