Lines Matching refs:hwmgr
42 struct pp_hwmgr *hwmgr; in amd_powerplay_create() local
47 hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL); in amd_powerplay_create()
48 if (hwmgr == NULL) in amd_powerplay_create()
51 hwmgr->adev = adev; in amd_powerplay_create()
52 hwmgr->not_vf = !amdgpu_sriov_vf(adev); in amd_powerplay_create()
53 hwmgr->device = amdgpu_cgs_create_device(adev); in amd_powerplay_create()
54 mutex_init(&hwmgr->msg_lock); in amd_powerplay_create()
55 hwmgr->chip_family = adev->family; in amd_powerplay_create()
56 hwmgr->chip_id = adev->asic_type; in amd_powerplay_create()
57 hwmgr->feature_mask = adev->pm.pp_feature; in amd_powerplay_create()
58 hwmgr->display_config = &adev->pm.pm_display_cfg; in amd_powerplay_create()
59 adev->powerplay.pp_handle = hwmgr; in amd_powerplay_create()
67 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in amd_powerplay_destroy() local
69 mutex_destroy(&hwmgr->msg_lock); in amd_powerplay_destroy()
71 kfree(hwmgr->hardcode_pp_table); in amd_powerplay_destroy()
72 hwmgr->hardcode_pp_table = NULL; in amd_powerplay_destroy()
74 kfree(hwmgr); in amd_powerplay_destroy()
75 hwmgr = NULL; in amd_powerplay_destroy()
97 struct pp_hwmgr *hwmgr = in pp_swctf_delayed_work_handler() local
99 struct amdgpu_device *adev = hwmgr->adev; in pp_swctf_delayed_work_handler()
111 hwmgr->hwmgr_func->read_sensor) { in pp_swctf_delayed_work_handler()
112 ret = hwmgr->hwmgr_func->read_sensor(hwmgr, in pp_swctf_delayed_work_handler()
121 ret = hwmgr->hwmgr_func->read_sensor(hwmgr, in pp_swctf_delayed_work_handler()
137 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_sw_init() local
140 ret = hwmgr_sw_init(hwmgr); in pp_sw_init()
145 INIT_DELAYED_WORK(&hwmgr->swctf_delayed_work, in pp_sw_init()
154 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_sw_fini() local
156 hwmgr_sw_fini(hwmgr); in pp_sw_fini()
167 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_hw_init() local
169 ret = hwmgr_hw_init(hwmgr); in pp_hw_init()
180 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_hw_fini() local
182 cancel_delayed_work_sync(&hwmgr->swctf_delayed_work); in pp_hw_fini()
184 hwmgr_hw_fini(hwmgr); in pp_hw_fini()
194 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_reserve_vram_for_smu() local
205 if (hwmgr->hwmgr_func->notify_cac_buffer_info) in pp_reserve_vram_for_smu()
206 r = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr, in pp_reserve_vram_for_smu()
223 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_late_init() local
225 if (hwmgr && hwmgr->pm_en) in pp_late_init()
226 hwmgr_handle_task(hwmgr, in pp_late_init()
268 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_suspend() local
270 cancel_delayed_work_sync(&hwmgr->swctf_delayed_work); in pp_suspend()
272 return hwmgr_suspend(hwmgr); in pp_suspend()
278 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_resume() local
280 return hwmgr_resume(hwmgr); in pp_resume()
325 struct pp_hwmgr *hwmgr = handle; in pp_dpm_load_fw() local
327 if (!hwmgr || !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->start_smu) in pp_dpm_load_fw()
330 if (hwmgr->smumgr_funcs->start_smu(hwmgr)) { in pp_dpm_load_fw()
345 struct pp_hwmgr *hwmgr = handle; in pp_set_clockgating_by_smu() local
347 if (!hwmgr || !hwmgr->pm_en) in pp_set_clockgating_by_smu()
350 if (hwmgr->hwmgr_func->update_clock_gatings == NULL) { in pp_set_clockgating_by_smu()
355 return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); in pp_set_clockgating_by_smu()
358 static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr, in pp_dpm_en_umd_pstate() argument
366 if (!(hwmgr->dpm_level & profile_mode_mask)) { in pp_dpm_en_umd_pstate()
369 hwmgr->saved_dpm_level = hwmgr->dpm_level; in pp_dpm_en_umd_pstate()
370 hwmgr->en_umd_pstate = true; in pp_dpm_en_umd_pstate()
376 *level = hwmgr->saved_dpm_level; in pp_dpm_en_umd_pstate()
377 hwmgr->en_umd_pstate = false; in pp_dpm_en_umd_pstate()
385 struct pp_hwmgr *hwmgr = handle; in pp_dpm_force_performance_level() local
387 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_force_performance_level()
390 if (level == hwmgr->dpm_level) in pp_dpm_force_performance_level()
393 pp_dpm_en_umd_pstate(hwmgr, &level); in pp_dpm_force_performance_level()
394 hwmgr->request_dpm_level = level; in pp_dpm_force_performance_level()
395 hwmgr_handle_task(hwmgr, AMD_PP_TASK_READJUST_POWER_STATE, NULL); in pp_dpm_force_performance_level()
403 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_performance_level() local
405 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_performance_level()
408 return hwmgr->dpm_level; in pp_dpm_get_performance_level()
413 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_sclk() local
415 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_sclk()
418 if (hwmgr->hwmgr_func->get_sclk == NULL) { in pp_dpm_get_sclk()
422 return hwmgr->hwmgr_func->get_sclk(hwmgr, low); in pp_dpm_get_sclk()
427 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_mclk() local
429 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_mclk()
432 if (hwmgr->hwmgr_func->get_mclk == NULL) { in pp_dpm_get_mclk()
436 return hwmgr->hwmgr_func->get_mclk(hwmgr, low); in pp_dpm_get_mclk()
441 struct pp_hwmgr *hwmgr = handle; in pp_dpm_powergate_vce() local
443 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_powergate_vce()
446 if (hwmgr->hwmgr_func->powergate_vce == NULL) { in pp_dpm_powergate_vce()
450 hwmgr->hwmgr_func->powergate_vce(hwmgr, gate); in pp_dpm_powergate_vce()
455 struct pp_hwmgr *hwmgr = handle; in pp_dpm_powergate_uvd() local
457 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_powergate_uvd()
460 if (hwmgr->hwmgr_func->powergate_uvd == NULL) { in pp_dpm_powergate_uvd()
464 hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate); in pp_dpm_powergate_uvd()
470 struct pp_hwmgr *hwmgr = handle; in pp_dpm_dispatch_tasks() local
472 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_dispatch_tasks()
475 return hwmgr_handle_task(hwmgr, task_id, user_state); in pp_dpm_dispatch_tasks()
480 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_current_power_state() local
484 if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps) in pp_dpm_get_current_power_state()
487 state = hwmgr->current_ps; in pp_dpm_get_current_power_state()
512 struct pp_hwmgr *hwmgr = handle; in pp_dpm_set_fan_control_mode() local
514 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_set_fan_control_mode()
517 if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) in pp_dpm_set_fan_control_mode()
523 hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode); in pp_dpm_set_fan_control_mode()
530 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_fan_control_mode() local
532 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_fan_control_mode()
535 if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) in pp_dpm_get_fan_control_mode()
541 *fan_mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr); in pp_dpm_get_fan_control_mode()
547 struct pp_hwmgr *hwmgr = handle; in pp_dpm_set_fan_speed_pwm() local
549 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_set_fan_speed_pwm()
552 if (hwmgr->hwmgr_func->set_fan_speed_pwm == NULL) in pp_dpm_set_fan_speed_pwm()
558 return hwmgr->hwmgr_func->set_fan_speed_pwm(hwmgr, speed); in pp_dpm_set_fan_speed_pwm()
563 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_fan_speed_pwm() local
565 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_fan_speed_pwm()
568 if (hwmgr->hwmgr_func->get_fan_speed_pwm == NULL) in pp_dpm_get_fan_speed_pwm()
574 return hwmgr->hwmgr_func->get_fan_speed_pwm(hwmgr, speed); in pp_dpm_get_fan_speed_pwm()
579 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_fan_speed_rpm() local
581 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_fan_speed_rpm()
584 if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL) in pp_dpm_get_fan_speed_rpm()
590 return hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm); in pp_dpm_get_fan_speed_rpm()
595 struct pp_hwmgr *hwmgr = handle; in pp_dpm_set_fan_speed_rpm() local
597 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_set_fan_speed_rpm()
600 if (hwmgr->hwmgr_func->set_fan_speed_rpm == NULL) in pp_dpm_set_fan_speed_rpm()
606 return hwmgr->hwmgr_func->set_fan_speed_rpm(hwmgr, rpm); in pp_dpm_set_fan_speed_rpm()
612 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_pp_num_states() local
617 if (!hwmgr || !hwmgr->pm_en || !hwmgr->ps) in pp_dpm_get_pp_num_states()
620 data->nums = hwmgr->num_ps; in pp_dpm_get_pp_num_states()
622 for (i = 0; i < hwmgr->num_ps; i++) { in pp_dpm_get_pp_num_states()
624 ((unsigned long)hwmgr->ps + i * hwmgr->ps_size); in pp_dpm_get_pp_num_states()
647 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_pp_table() local
649 if (!hwmgr || !hwmgr->pm_en || !hwmgr->soft_pp_table) in pp_dpm_get_pp_table()
652 *table = (char *)hwmgr->soft_pp_table; in pp_dpm_get_pp_table()
653 return hwmgr->soft_pp_table_size; in pp_dpm_get_pp_table()
658 struct pp_hwmgr *hwmgr = handle; in amd_powerplay_reset() local
661 ret = hwmgr_hw_fini(hwmgr); in amd_powerplay_reset()
665 ret = hwmgr_hw_init(hwmgr); in amd_powerplay_reset()
669 return hwmgr_handle_task(hwmgr, AMD_PP_TASK_COMPLETE_INIT, NULL); in amd_powerplay_reset()
674 struct pp_hwmgr *hwmgr = handle; in pp_dpm_set_pp_table() local
677 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_set_pp_table()
680 if (!hwmgr->hardcode_pp_table) { in pp_dpm_set_pp_table()
681 hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table, in pp_dpm_set_pp_table()
682 hwmgr->soft_pp_table_size, in pp_dpm_set_pp_table()
684 if (!hwmgr->hardcode_pp_table) in pp_dpm_set_pp_table()
688 memcpy(hwmgr->hardcode_pp_table, buf, size); in pp_dpm_set_pp_table()
690 hwmgr->soft_pp_table = hwmgr->hardcode_pp_table; in pp_dpm_set_pp_table()
696 if (hwmgr->hwmgr_func->avfs_control) in pp_dpm_set_pp_table()
697 ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false); in pp_dpm_set_pp_table()
705 struct pp_hwmgr *hwmgr = handle; in pp_dpm_force_clock_level() local
707 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_force_clock_level()
710 if (hwmgr->hwmgr_func->force_clock_level == NULL) { in pp_dpm_force_clock_level()
715 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { in pp_dpm_force_clock_level()
720 return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask); in pp_dpm_force_clock_level()
728 struct pp_hwmgr *hwmgr = handle; in pp_dpm_emit_clock_levels() local
730 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_emit_clock_levels()
733 if (!hwmgr->hwmgr_func->emit_clock_levels) in pp_dpm_emit_clock_levels()
736 return hwmgr->hwmgr_func->emit_clock_levels(hwmgr, type, buf, offset); in pp_dpm_emit_clock_levels()
742 struct pp_hwmgr *hwmgr = handle; in pp_dpm_print_clock_levels() local
744 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_print_clock_levels()
747 if (hwmgr->hwmgr_func->print_clock_levels == NULL) { in pp_dpm_print_clock_levels()
751 return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf); in pp_dpm_print_clock_levels()
756 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_sclk_od() local
758 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_sclk_od()
761 if (hwmgr->hwmgr_func->get_sclk_od == NULL) { in pp_dpm_get_sclk_od()
765 return hwmgr->hwmgr_func->get_sclk_od(hwmgr); in pp_dpm_get_sclk_od()
770 struct pp_hwmgr *hwmgr = handle; in pp_dpm_set_sclk_od() local
772 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_set_sclk_od()
775 if (hwmgr->hwmgr_func->set_sclk_od == NULL) { in pp_dpm_set_sclk_od()
780 return hwmgr->hwmgr_func->set_sclk_od(hwmgr, value); in pp_dpm_set_sclk_od()
785 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_mclk_od() local
787 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_mclk_od()
790 if (hwmgr->hwmgr_func->get_mclk_od == NULL) { in pp_dpm_get_mclk_od()
794 return hwmgr->hwmgr_func->get_mclk_od(hwmgr); in pp_dpm_get_mclk_od()
799 struct pp_hwmgr *hwmgr = handle; in pp_dpm_set_mclk_od() local
801 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_set_mclk_od()
804 if (hwmgr->hwmgr_func->set_mclk_od == NULL) { in pp_dpm_set_mclk_od()
808 return hwmgr->hwmgr_func->set_mclk_od(hwmgr, value); in pp_dpm_set_mclk_od()
814 struct pp_hwmgr *hwmgr = handle; in pp_dpm_read_sensor() local
816 if (!hwmgr || !hwmgr->pm_en || !value) in pp_dpm_read_sensor()
821 *((uint32_t *)value) = hwmgr->pstate_sclk * 100; in pp_dpm_read_sensor()
824 *((uint32_t *)value) = hwmgr->pstate_mclk * 100; in pp_dpm_read_sensor()
827 *((uint32_t *)value) = hwmgr->pstate_sclk_peak * 100; in pp_dpm_read_sensor()
830 *((uint32_t *)value) = hwmgr->pstate_mclk_peak * 100; in pp_dpm_read_sensor()
833 *((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMinRPM; in pp_dpm_read_sensor()
836 *((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMaxRPM; in pp_dpm_read_sensor()
839 return hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size); in pp_dpm_read_sensor()
846 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_vce_clock_state() local
848 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_vce_clock_state()
851 if (idx < hwmgr->num_vce_state_tables) in pp_dpm_get_vce_clock_state()
852 return &hwmgr->vce_states[idx]; in pp_dpm_get_vce_clock_state()
858 struct pp_hwmgr *hwmgr = handle; in pp_get_power_profile_mode() local
860 if (!hwmgr || !hwmgr->pm_en || !hwmgr->hwmgr_func->get_power_profile_mode) in pp_get_power_profile_mode()
865 return hwmgr->hwmgr_func->get_power_profile_mode(hwmgr, buf); in pp_get_power_profile_mode()
870 struct pp_hwmgr *hwmgr = handle; in pp_set_power_profile_mode() local
872 if (!hwmgr || !hwmgr->pm_en || !hwmgr->hwmgr_func->set_power_profile_mode) in pp_set_power_profile_mode()
875 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { in pp_set_power_profile_mode()
880 return hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size); in pp_set_power_profile_mode()
885 struct pp_hwmgr *hwmgr = handle; in pp_set_fine_grain_clk_vol() local
887 if (!hwmgr || !hwmgr->pm_en) in pp_set_fine_grain_clk_vol()
890 if (hwmgr->hwmgr_func->set_fine_grain_clk_vol == NULL) in pp_set_fine_grain_clk_vol()
893 return hwmgr->hwmgr_func->set_fine_grain_clk_vol(hwmgr, type, input, size); in pp_set_fine_grain_clk_vol()
899 struct pp_hwmgr *hwmgr = handle; in pp_odn_edit_dpm_table() local
901 if (!hwmgr || !hwmgr->pm_en) in pp_odn_edit_dpm_table()
904 if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) { in pp_odn_edit_dpm_table()
909 return hwmgr->hwmgr_func->odn_edit_dpm_table(hwmgr, type, input, size); in pp_odn_edit_dpm_table()
914 struct pp_hwmgr *hwmgr = handle; in pp_dpm_set_mp1_state() local
916 if (!hwmgr) in pp_dpm_set_mp1_state()
919 if (!hwmgr->pm_en) in pp_dpm_set_mp1_state()
922 if (hwmgr->hwmgr_func->set_mp1_state) in pp_dpm_set_mp1_state()
923 return hwmgr->hwmgr_func->set_mp1_state(hwmgr, mp1_state); in pp_dpm_set_mp1_state()
931 struct pp_hwmgr *hwmgr = handle; in pp_dpm_switch_power_profile() local
935 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_switch_power_profile()
938 if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) { in pp_dpm_switch_power_profile()
947 hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]); in pp_dpm_switch_power_profile()
948 index = fls(hwmgr->workload_mask); in pp_dpm_switch_power_profile()
950 workload[0] = hwmgr->workload_setting[index]; in pp_dpm_switch_power_profile()
952 hwmgr->workload_mask |= (1 << hwmgr->workload_prority[type]); in pp_dpm_switch_power_profile()
953 index = fls(hwmgr->workload_mask); in pp_dpm_switch_power_profile()
955 workload[0] = hwmgr->workload_setting[index]; in pp_dpm_switch_power_profile()
959 hwmgr->hwmgr_func->disable_power_features_for_compute_performance) { in pp_dpm_switch_power_profile()
960 if (hwmgr->hwmgr_func->disable_power_features_for_compute_performance(hwmgr, en)) in pp_dpm_switch_power_profile()
964 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) in pp_dpm_switch_power_profile()
965 hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, workload, 0); in pp_dpm_switch_power_profile()
972 struct pp_hwmgr *hwmgr = handle; in pp_set_power_limit() local
975 if (!hwmgr || !hwmgr->pm_en) in pp_set_power_limit()
978 if (hwmgr->hwmgr_func->set_power_limit == NULL) { in pp_set_power_limit()
984 limit = hwmgr->default_power_limit; in pp_set_power_limit()
986 max_power_limit = hwmgr->default_power_limit; in pp_set_power_limit()
987 if (hwmgr->od_enabled) { in pp_set_power_limit()
988 max_power_limit *= (100 + hwmgr->platform_descriptor.TDPODLimit); in pp_set_power_limit()
995 hwmgr->hwmgr_func->set_power_limit(hwmgr, limit); in pp_set_power_limit()
996 hwmgr->power_limit = limit; in pp_set_power_limit()
1004 struct pp_hwmgr *hwmgr = handle; in pp_get_power_limit() local
1007 if (!hwmgr || !hwmgr->pm_en || !limit) in pp_get_power_limit()
1015 *limit = hwmgr->power_limit; in pp_get_power_limit()
1018 *limit = hwmgr->default_power_limit; in pp_get_power_limit()
1021 *limit = hwmgr->default_power_limit; in pp_get_power_limit()
1022 if (hwmgr->od_enabled) { in pp_get_power_limit()
1023 *limit *= (100 + hwmgr->platform_descriptor.TDPODLimit); in pp_get_power_limit()
1041 struct pp_hwmgr *hwmgr = handle; in pp_display_configuration_change() local
1043 if (!hwmgr || !hwmgr->pm_en) in pp_display_configuration_change()
1046 phm_store_dal_configuration_data(hwmgr, display_config); in pp_display_configuration_change()
1053 struct pp_hwmgr *hwmgr = handle; in pp_get_display_power_level() local
1055 if (!hwmgr || !hwmgr->pm_en || !output) in pp_get_display_power_level()
1058 return phm_get_dal_power_level(hwmgr, output); in pp_get_display_power_level()
1066 struct pp_hwmgr *hwmgr = handle; in pp_get_current_clocks() local
1069 if (!hwmgr || !hwmgr->pm_en) in pp_get_current_clocks()
1072 phm_get_dal_power_level(hwmgr, &simple_clocks); in pp_get_current_clocks()
1074 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in pp_get_current_clocks()
1076 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, in pp_get_current_clocks()
1079 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, in pp_get_current_clocks()
1102 if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) { in pp_get_current_clocks()
1111 struct pp_hwmgr *hwmgr = handle; in pp_get_clock_by_type() local
1113 if (!hwmgr || !hwmgr->pm_en) in pp_get_clock_by_type()
1119 return phm_get_clock_by_type(hwmgr, type, clocks); in pp_get_clock_by_type()
1126 struct pp_hwmgr *hwmgr = handle; in pp_get_clock_by_type_with_latency() local
1128 if (!hwmgr || !hwmgr->pm_en || !clocks) in pp_get_clock_by_type_with_latency()
1131 return phm_get_clock_by_type_with_latency(hwmgr, type, clocks); in pp_get_clock_by_type_with_latency()
1138 struct pp_hwmgr *hwmgr = handle; in pp_get_clock_by_type_with_voltage() local
1140 if (!hwmgr || !hwmgr->pm_en || !clocks) in pp_get_clock_by_type_with_voltage()
1143 return phm_get_clock_by_type_with_voltage(hwmgr, type, clocks); in pp_get_clock_by_type_with_voltage()
1149 struct pp_hwmgr *hwmgr = handle; in pp_set_watermarks_for_clocks_ranges() local
1151 if (!hwmgr || !hwmgr->pm_en || !clock_ranges) in pp_set_watermarks_for_clocks_ranges()
1154 return phm_set_watermarks_for_clocks_ranges(hwmgr, in pp_set_watermarks_for_clocks_ranges()
1161 struct pp_hwmgr *hwmgr = handle; in pp_display_clock_voltage_request() local
1163 if (!hwmgr || !hwmgr->pm_en || !clock) in pp_display_clock_voltage_request()
1166 return phm_display_clock_voltage_request(hwmgr, clock); in pp_display_clock_voltage_request()
1172 struct pp_hwmgr *hwmgr = handle; in pp_get_display_mode_validation_clocks() local
1175 if (!hwmgr || !hwmgr->pm_en || !clocks) in pp_get_display_mode_validation_clocks()
1180 …if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerSta… in pp_get_display_mode_validation_clocks()
1181 ret = phm_get_max_high_clocks(hwmgr, clocks); in pp_get_display_mode_validation_clocks()
1188 struct pp_hwmgr *hwmgr = handle; in pp_dpm_powergate_mmhub() local
1190 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_powergate_mmhub()
1193 if (hwmgr->hwmgr_func->powergate_mmhub == NULL) { in pp_dpm_powergate_mmhub()
1198 return hwmgr->hwmgr_func->powergate_mmhub(hwmgr); in pp_dpm_powergate_mmhub()
1203 struct pp_hwmgr *hwmgr = handle; in pp_dpm_powergate_gfx() local
1205 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_powergate_gfx()
1208 if (hwmgr->hwmgr_func->powergate_gfx == NULL) { in pp_dpm_powergate_gfx()
1213 return hwmgr->hwmgr_func->powergate_gfx(hwmgr, gate); in pp_dpm_powergate_gfx()
1218 struct pp_hwmgr *hwmgr = handle; in pp_dpm_powergate_acp() local
1220 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_powergate_acp()
1223 if (hwmgr->hwmgr_func->powergate_acp == NULL) { in pp_dpm_powergate_acp()
1228 hwmgr->hwmgr_func->powergate_acp(hwmgr, gate); in pp_dpm_powergate_acp()
1233 struct pp_hwmgr *hwmgr = handle; in pp_dpm_powergate_sdma() local
1235 if (!hwmgr) in pp_dpm_powergate_sdma()
1238 if (hwmgr->hwmgr_func->powergate_sdma == NULL) { in pp_dpm_powergate_sdma()
1243 hwmgr->hwmgr_func->powergate_sdma(hwmgr, gate); in pp_dpm_powergate_sdma()
1284 struct pp_hwmgr *hwmgr = handle; in pp_notify_smu_enable_pwe() local
1286 if (!hwmgr || !hwmgr->pm_en) in pp_notify_smu_enable_pwe()
1289 if (hwmgr->hwmgr_func->smus_notify_pwe == NULL) { in pp_notify_smu_enable_pwe()
1294 hwmgr->hwmgr_func->smus_notify_pwe(hwmgr); in pp_notify_smu_enable_pwe()
1301 struct pp_hwmgr *hwmgr = handle; in pp_enable_mgpu_fan_boost() local
1303 if (!hwmgr) in pp_enable_mgpu_fan_boost()
1306 if (!hwmgr->pm_en || in pp_enable_mgpu_fan_boost()
1307 hwmgr->hwmgr_func->enable_mgpu_fan_boost == NULL) in pp_enable_mgpu_fan_boost()
1310 hwmgr->hwmgr_func->enable_mgpu_fan_boost(hwmgr); in pp_enable_mgpu_fan_boost()
1317 struct pp_hwmgr *hwmgr = handle; in pp_set_min_deep_sleep_dcefclk() local
1319 if (!hwmgr || !hwmgr->pm_en) in pp_set_min_deep_sleep_dcefclk()
1322 if (hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk == NULL) { in pp_set_min_deep_sleep_dcefclk()
1327 hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, clock); in pp_set_min_deep_sleep_dcefclk()
1334 struct pp_hwmgr *hwmgr = handle; in pp_set_hard_min_dcefclk_by_freq() local
1336 if (!hwmgr || !hwmgr->pm_en) in pp_set_hard_min_dcefclk_by_freq()
1339 if (hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq == NULL) { in pp_set_hard_min_dcefclk_by_freq()
1344 hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq(hwmgr, clock); in pp_set_hard_min_dcefclk_by_freq()
1351 struct pp_hwmgr *hwmgr = handle; in pp_set_hard_min_fclk_by_freq() local
1353 if (!hwmgr || !hwmgr->pm_en) in pp_set_hard_min_fclk_by_freq()
1356 if (hwmgr->hwmgr_func->set_hard_min_fclk_by_freq == NULL) { in pp_set_hard_min_fclk_by_freq()
1361 hwmgr->hwmgr_func->set_hard_min_fclk_by_freq(hwmgr, clock); in pp_set_hard_min_fclk_by_freq()
1368 struct pp_hwmgr *hwmgr = handle; in pp_set_active_display_count() local
1370 if (!hwmgr || !hwmgr->pm_en) in pp_set_active_display_count()
1373 return phm_set_active_display_count(hwmgr, count); in pp_set_active_display_count()
1378 struct pp_hwmgr *hwmgr = handle; in pp_get_asic_baco_capability() local
1380 if (!hwmgr) in pp_get_asic_baco_capability()
1383 if (!(hwmgr->not_vf && amdgpu_dpm) || in pp_get_asic_baco_capability()
1384 !hwmgr->hwmgr_func->get_bamaco_support) in pp_get_asic_baco_capability()
1387 return hwmgr->hwmgr_func->get_bamaco_support(hwmgr); in pp_get_asic_baco_capability()
1392 struct pp_hwmgr *hwmgr = handle; in pp_get_asic_baco_state() local
1394 if (!hwmgr) in pp_get_asic_baco_state()
1397 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_asic_baco_state) in pp_get_asic_baco_state()
1400 hwmgr->hwmgr_func->get_asic_baco_state(hwmgr, (enum BACO_STATE *)state); in pp_get_asic_baco_state()
1407 struct pp_hwmgr *hwmgr = handle; in pp_set_asic_baco_state() local
1409 if (!hwmgr) in pp_set_asic_baco_state()
1412 if (!(hwmgr->not_vf && amdgpu_dpm) || in pp_set_asic_baco_state()
1413 !hwmgr->hwmgr_func->set_asic_baco_state) in pp_set_asic_baco_state()
1416 hwmgr->hwmgr_func->set_asic_baco_state(hwmgr, (enum BACO_STATE)state); in pp_set_asic_baco_state()
1423 struct pp_hwmgr *hwmgr = handle; in pp_get_ppfeature_status() local
1425 if (!hwmgr || !hwmgr->pm_en || !buf) in pp_get_ppfeature_status()
1428 if (hwmgr->hwmgr_func->get_ppfeature_status == NULL) { in pp_get_ppfeature_status()
1433 return hwmgr->hwmgr_func->get_ppfeature_status(hwmgr, buf); in pp_get_ppfeature_status()
1438 struct pp_hwmgr *hwmgr = handle; in pp_set_ppfeature_status() local
1440 if (!hwmgr || !hwmgr->pm_en) in pp_set_ppfeature_status()
1443 if (hwmgr->hwmgr_func->set_ppfeature_status == NULL) { in pp_set_ppfeature_status()
1448 return hwmgr->hwmgr_func->set_ppfeature_status(hwmgr, ppfeature_masks); in pp_set_ppfeature_status()
1453 struct pp_hwmgr *hwmgr = handle; in pp_asic_reset_mode_2() local
1455 if (!hwmgr || !hwmgr->pm_en) in pp_asic_reset_mode_2()
1458 if (hwmgr->hwmgr_func->asic_reset == NULL) { in pp_asic_reset_mode_2()
1463 return hwmgr->hwmgr_func->asic_reset(hwmgr, SMU_ASIC_RESET_MODE_2); in pp_asic_reset_mode_2()
1468 struct pp_hwmgr *hwmgr = handle; in pp_smu_i2c_bus_access() local
1470 if (!hwmgr || !hwmgr->pm_en) in pp_smu_i2c_bus_access()
1473 if (hwmgr->hwmgr_func->smu_i2c_bus_access == NULL) { in pp_smu_i2c_bus_access()
1478 return hwmgr->hwmgr_func->smu_i2c_bus_access(hwmgr, acquire); in pp_smu_i2c_bus_access()
1483 struct pp_hwmgr *hwmgr = handle; in pp_set_df_cstate() local
1485 if (!hwmgr) in pp_set_df_cstate()
1488 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_df_cstate) in pp_set_df_cstate()
1491 hwmgr->hwmgr_func->set_df_cstate(hwmgr, state); in pp_set_df_cstate()
1498 struct pp_hwmgr *hwmgr = handle; in pp_set_xgmi_pstate() local
1500 if (!hwmgr) in pp_set_xgmi_pstate()
1503 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_xgmi_pstate) in pp_set_xgmi_pstate()
1506 hwmgr->hwmgr_func->set_xgmi_pstate(hwmgr, pstate); in pp_set_xgmi_pstate()
1513 struct pp_hwmgr *hwmgr = handle; in pp_get_gpu_metrics() local
1515 if (!hwmgr) in pp_get_gpu_metrics()
1518 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_gpu_metrics) in pp_get_gpu_metrics()
1521 return hwmgr->hwmgr_func->get_gpu_metrics(hwmgr, table); in pp_get_gpu_metrics()
1526 struct pp_hwmgr *hwmgr = handle; in pp_gfx_state_change_set() local
1528 if (!hwmgr || !hwmgr->pm_en) in pp_gfx_state_change_set()
1531 if (hwmgr->hwmgr_func->gfx_state_change == NULL) { in pp_gfx_state_change_set()
1536 hwmgr->hwmgr_func->gfx_state_change(hwmgr, state); in pp_gfx_state_change_set()
1542 struct pp_hwmgr *hwmgr = handle; in pp_get_prv_buffer_details() local
1543 struct amdgpu_device *adev = hwmgr->adev; in pp_get_prv_buffer_details()
1563 struct pp_hwmgr *hwmgr = handle; in pp_pm_compute_clocks() local
1564 struct amdgpu_device *adev = hwmgr->adev; in pp_pm_compute_clocks()