Lines Matching +full:low +full:- +full:leakage
326 -1270850L,
608 -1270850L,
1100 -1270850L,
1627 -1270850L,
1658 -1270850L,
1809 -1270850L,
1854 struct si_power_info *pi = adev->pm.dpm.priv; in si_get_pi()
1859 u16 v, s32 t, u32 ileakage, u32 *leakage) in si_calculate_leakage_for_v_and_t_formula() argument
1869 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); in si_calculate_leakage_for_v_and_t_formula()
1870 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); in si_calculate_leakage_for_v_and_t_formula()
1871 av = div64_s64(drm_int2fixp(coeff->av), 100000000); in si_calculate_leakage_for_v_and_t_formula()
1872 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); in si_calculate_leakage_for_v_and_t_formula()
1873 t_ref = drm_int2fixp(coeff->t_ref); in si_calculate_leakage_for_v_and_t_formula()
1882 *leakage = drm_fixp2int(leakage_w * 1000); in si_calculate_leakage_for_v_and_t_formula()
1890 u32 *leakage) in si_calculate_leakage_for_v_and_t() argument
1892 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); in si_calculate_leakage_for_v_and_t()
1897 u32 ileakage, u32 *leakage) in si_calculate_leakage_for_v_formula() argument
1905 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), in si_calculate_leakage_for_v_formula()
1906 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); in si_calculate_leakage_for_v_formula()
1910 *leakage = drm_fixp2int(leakage_w * 1000); in si_calculate_leakage_for_v_formula()
1918 u32 *leakage) in si_calculate_leakage_for_v() argument
1920 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); in si_calculate_leakage_for_v()
1927 u32 p_limit1 = adev->pm.dpm.tdp_limit; in si_update_dte_from_pl2()
1928 u32 p_limit2 = adev->pm.dpm.near_tdp_limit; in si_update_dte_from_pl2()
1929 u32 k = dte_data->k; in si_update_dte_from_pl2()
1930 u32 t_max = dte_data->max_t; in si_update_dte_from_pl2()
1932 u32 t_0 = dte_data->t0; in si_update_dte_from_pl2()
1936 dte_data->tdep_count = 3; in si_update_dte_from_pl2()
1939 dte_data->r[i] = in si_update_dte_from_pl2()
1940 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / in si_update_dte_from_pl2()
1944 dte_data->tdep_r[1] = dte_data->r[4] * 2; in si_update_dte_from_pl2()
1947 dte_data->tdep_r[i] = dte_data->r[4]; in si_update_dte_from_pl2()
1956 struct rv7xx_power_info *pi = adev->pm.dpm.priv; in rv770_get_pi()
1963 struct ni_power_info *pi = adev->pm.dpm.priv; in ni_get_pi()
1970 struct si_ps *ps = aps->ps_priv; in si_get_ps()
1981 if (adev->asic_type == CHIP_TAHITI) { in si_initialize_powertune_defaults()
1982 si_pi->cac_weights = cac_weights_tahiti; in si_initialize_powertune_defaults()
1983 si_pi->lcac_config = lcac_tahiti; in si_initialize_powertune_defaults()
1984 si_pi->cac_override = cac_override_tahiti; in si_initialize_powertune_defaults()
1985 si_pi->powertune_data = &powertune_data_tahiti; in si_initialize_powertune_defaults()
1986 si_pi->dte_data = dte_data_tahiti; in si_initialize_powertune_defaults()
1988 switch (adev->pdev->device) { in si_initialize_powertune_defaults()
1990 si_pi->dte_data.enable_dte_by_default = true; in si_initialize_powertune_defaults()
1993 si_pi->dte_data = dte_data_new_zealand; in si_initialize_powertune_defaults()
1999 si_pi->dte_data = dte_data_aruba_pro; in si_initialize_powertune_defaults()
2003 si_pi->dte_data = dte_data_malta; in si_initialize_powertune_defaults()
2007 si_pi->dte_data = dte_data_tahiti_pro; in si_initialize_powertune_defaults()
2011 if (si_pi->dte_data.enable_dte_by_default == true) in si_initialize_powertune_defaults()
2015 } else if (adev->asic_type == CHIP_PITCAIRN) { in si_initialize_powertune_defaults()
2016 si_pi->cac_weights = cac_weights_pitcairn; in si_initialize_powertune_defaults()
2017 si_pi->lcac_config = lcac_pitcairn; in si_initialize_powertune_defaults()
2018 si_pi->cac_override = cac_override_pitcairn; in si_initialize_powertune_defaults()
2019 si_pi->powertune_data = &powertune_data_pitcairn; in si_initialize_powertune_defaults()
2021 switch (adev->pdev->device) { in si_initialize_powertune_defaults()
2024 si_pi->dte_data = dte_data_curacao_xt; in si_initialize_powertune_defaults()
2029 si_pi->dte_data = dte_data_curacao_pro; in si_initialize_powertune_defaults()
2034 si_pi->dte_data = dte_data_neptune_xt; in si_initialize_powertune_defaults()
2038 si_pi->dte_data = dte_data_pitcairn; in si_initialize_powertune_defaults()
2041 } else if (adev->asic_type == CHIP_VERDE) { in si_initialize_powertune_defaults()
2042 si_pi->lcac_config = lcac_cape_verde; in si_initialize_powertune_defaults()
2043 si_pi->cac_override = cac_override_cape_verde; in si_initialize_powertune_defaults()
2044 si_pi->powertune_data = &powertune_data_cape_verde; in si_initialize_powertune_defaults()
2046 switch (adev->pdev->device) { in si_initialize_powertune_defaults()
2051 si_pi->cac_weights = cac_weights_cape_verde_pro; in si_initialize_powertune_defaults()
2052 si_pi->dte_data = dte_data_cape_verde; in si_initialize_powertune_defaults()
2055 si_pi->cac_weights = cac_weights_cape_verde_pro; in si_initialize_powertune_defaults()
2056 si_pi->dte_data = dte_data_sun_xt; in si_initialize_powertune_defaults()
2061 si_pi->cac_weights = cac_weights_heathrow; in si_initialize_powertune_defaults()
2062 si_pi->dte_data = dte_data_cape_verde; in si_initialize_powertune_defaults()
2066 si_pi->cac_weights = cac_weights_chelsea_xt; in si_initialize_powertune_defaults()
2067 si_pi->dte_data = dte_data_cape_verde; in si_initialize_powertune_defaults()
2070 si_pi->cac_weights = cac_weights_chelsea_pro; in si_initialize_powertune_defaults()
2071 si_pi->dte_data = dte_data_cape_verde; in si_initialize_powertune_defaults()
2074 si_pi->cac_weights = cac_weights_heathrow; in si_initialize_powertune_defaults()
2075 si_pi->dte_data = dte_data_venus_xtx; in si_initialize_powertune_defaults()
2078 si_pi->cac_weights = cac_weights_heathrow; in si_initialize_powertune_defaults()
2079 si_pi->dte_data = dte_data_venus_xt; in si_initialize_powertune_defaults()
2085 si_pi->cac_weights = cac_weights_chelsea_pro; in si_initialize_powertune_defaults()
2086 si_pi->dte_data = dte_data_venus_pro; in si_initialize_powertune_defaults()
2089 si_pi->cac_weights = cac_weights_cape_verde; in si_initialize_powertune_defaults()
2090 si_pi->dte_data = dte_data_cape_verde; in si_initialize_powertune_defaults()
2093 } else if (adev->asic_type == CHIP_OLAND) { in si_initialize_powertune_defaults()
2094 si_pi->lcac_config = lcac_mars_pro; in si_initialize_powertune_defaults()
2095 si_pi->cac_override = cac_override_oland; in si_initialize_powertune_defaults()
2096 si_pi->powertune_data = &powertune_data_mars_pro; in si_initialize_powertune_defaults()
2097 si_pi->dte_data = dte_data_mars_pro; in si_initialize_powertune_defaults()
2099 switch (adev->pdev->device) { in si_initialize_powertune_defaults()
2104 si_pi->cac_weights = cac_weights_mars_pro; in si_initialize_powertune_defaults()
2111 si_pi->cac_weights = cac_weights_mars_xt; in si_initialize_powertune_defaults()
2117 si_pi->cac_weights = cac_weights_oland_pro; in si_initialize_powertune_defaults()
2121 si_pi->cac_weights = cac_weights_oland_xt; in si_initialize_powertune_defaults()
2125 si_pi->cac_weights = cac_weights_oland; in si_initialize_powertune_defaults()
2126 si_pi->lcac_config = lcac_oland; in si_initialize_powertune_defaults()
2127 si_pi->cac_override = cac_override_oland; in si_initialize_powertune_defaults()
2128 si_pi->powertune_data = &powertune_data_oland; in si_initialize_powertune_defaults()
2129 si_pi->dte_data = dte_data_oland; in si_initialize_powertune_defaults()
2132 } else if (adev->asic_type == CHIP_HAINAN) { in si_initialize_powertune_defaults()
2133 si_pi->cac_weights = cac_weights_hainan; in si_initialize_powertune_defaults()
2134 si_pi->lcac_config = lcac_oland; in si_initialize_powertune_defaults()
2135 si_pi->cac_override = cac_override_oland; in si_initialize_powertune_defaults()
2136 si_pi->powertune_data = &powertune_data_hainan; in si_initialize_powertune_defaults()
2137 si_pi->dte_data = dte_data_sun_xt; in si_initialize_powertune_defaults()
2144 ni_pi->enable_power_containment = false; in si_initialize_powertune_defaults()
2145 ni_pi->enable_cac = false; in si_initialize_powertune_defaults()
2146 ni_pi->enable_sq_ramping = false; in si_initialize_powertune_defaults()
2147 si_pi->enable_dte = false; in si_initialize_powertune_defaults()
2149 if (si_pi->powertune_data->enable_powertune_by_default) { in si_initialize_powertune_defaults()
2150 ni_pi->enable_power_containment = true; in si_initialize_powertune_defaults()
2151 ni_pi->enable_cac = true; in si_initialize_powertune_defaults()
2152 if (si_pi->dte_data.enable_dte_by_default) { in si_initialize_powertune_defaults()
2153 si_pi->enable_dte = true; in si_initialize_powertune_defaults()
2155 si_update_dte_from_pl2(adev, &si_pi->dte_data); in si_initialize_powertune_defaults()
2158 ni_pi->enable_sq_ramping = true; in si_initialize_powertune_defaults()
2161 ni_pi->driver_calculate_cac_leakage = true; in si_initialize_powertune_defaults()
2162 ni_pi->cac_configuration_required = true; in si_initialize_powertune_defaults()
2164 if (ni_pi->cac_configuration_required) { in si_initialize_powertune_defaults()
2165 ni_pi->support_cac_long_term_average = true; in si_initialize_powertune_defaults()
2166 si_pi->dyn_powertune_data.l2_lta_window_size = in si_initialize_powertune_defaults()
2167 si_pi->powertune_data->l2_lta_window_size_default; in si_initialize_powertune_defaults()
2168 si_pi->dyn_powertune_data.lts_truncate = in si_initialize_powertune_defaults()
2169 si_pi->powertune_data->lts_truncate_default; in si_initialize_powertune_defaults()
2171 ni_pi->support_cac_long_term_average = false; in si_initialize_powertune_defaults()
2172 si_pi->dyn_powertune_data.l2_lta_window_size = 0; in si_initialize_powertune_defaults()
2173 si_pi->dyn_powertune_data.lts_truncate = 0; in si_initialize_powertune_defaults()
2176 si_pi->dyn_powertune_data.disable_uvd_powertune = false; in si_initialize_powertune_defaults()
2217 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit) in si_calculate_adjusted_tdp_limits()
2218 return -EINVAL; in si_calculate_adjusted_tdp_limits()
2220 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2223 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2224 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit); in si_calculate_adjusted_tdp_limits()
2226 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2227 adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit; in si_calculate_adjusted_tdp_limits()
2228 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted) in si_calculate_adjusted_tdp_limits()
2229 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; in si_calculate_adjusted_tdp_limits()
2235 return -EINVAL; in si_calculate_adjusted_tdp_limits()
2237 return -EINVAL; in si_calculate_adjusted_tdp_limits()
2248 if (ni_pi->enable_power_containment) { in si_populate_smc_tdp_limits()
2249 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; in si_populate_smc_tdp_limits()
2251 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table; in si_populate_smc_tdp_limits()
2258 return -EINVAL; in si_populate_smc_tdp_limits()
2264 adev->pm.dpm.tdp_adjustment, in si_populate_smc_tdp_limits()
2270 smc_table->dpm2Params.TDPLimit = in si_populate_smc_tdp_limits()
2272 smc_table->dpm2Params.NearTDPLimit = in si_populate_smc_tdp_limits()
2274 smc_table->dpm2Params.SafePowerLimit = in si_populate_smc_tdp_limits()
2278 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + in si_populate_smc_tdp_limits()
2280 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), in si_populate_smc_tdp_limits()
2282 si_pi->sram_end); in si_populate_smc_tdp_limits()
2286 if (si_pi->enable_ppm) { in si_populate_smc_tdp_limits()
2287 papm_parm = &si_pi->papm_parm; in si_populate_smc_tdp_limits()
2289 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); in si_populate_smc_tdp_limits()
2290 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); in si_populate_smc_tdp_limits()
2291 papm_parm->dGPU_T_Warning = cpu_to_be32(95); in si_populate_smc_tdp_limits()
2292 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); in si_populate_smc_tdp_limits()
2293 papm_parm->PlatformPowerLimit = 0xffffffff; in si_populate_smc_tdp_limits()
2294 papm_parm->NearTDPLimitPAPM = 0xffffffff; in si_populate_smc_tdp_limits()
2296 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start, in si_populate_smc_tdp_limits()
2299 si_pi->sram_end); in si_populate_smc_tdp_limits()
2313 if (ni_pi->enable_power_containment) { in si_populate_smc_tdp_limits_2()
2314 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; in si_populate_smc_tdp_limits_2()
2320 smc_table->dpm2Params.NearTDPLimit = in si_populate_smc_tdp_limits_2()
2321 cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); in si_populate_smc_tdp_limits_2()
2322 smc_table->dpm2Params.SafePowerLimit = in si_populate_smc_tdp_limits_2()
2323 …cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_… in si_populate_smc_tdp_limits_2()
2326 (si_pi->state_table_start + in si_populate_smc_tdp_limits_2()
2329 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), in si_populate_smc_tdp_limits_2()
2331 si_pi->sram_end); in si_populate_smc_tdp_limits_2()
2366 if (si_pi->dyn_powertune_data.disable_uvd_powertune && in si_should_disable_uvd_powertune()
2367 amdgpu_state->vclk && amdgpu_state->dclk) in si_should_disable_uvd_powertune()
2375 struct evergreen_power_info *pi = adev->pm.dpm.priv; in evergreen_get_pi()
2399 if (ni_pi->enable_power_containment == false) in si_populate_power_containment_values()
2402 if (state->performance_level_count == 0) in si_populate_power_containment_values()
2403 return -EINVAL; in si_populate_power_containment_values()
2405 if (smc_state->levelCount != state->performance_level_count) in si_populate_power_containment_values()
2406 return -EINVAL; in si_populate_power_containment_values()
2410 smc_state->levels[0].dpm2.MaxPS = 0; in si_populate_power_containment_values()
2411 smc_state->levels[0].dpm2.NearTDPDec = 0; in si_populate_power_containment_values()
2412 smc_state->levels[0].dpm2.AboveSafeInc = 0; in si_populate_power_containment_values()
2413 smc_state->levels[0].dpm2.BelowSafeInc = 0; in si_populate_power_containment_values()
2414 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; in si_populate_power_containment_values()
2416 for (i = 1; i < state->performance_level_count; i++) { in si_populate_power_containment_values()
2417 prev_sclk = state->performance_levels[i-1].sclk; in si_populate_power_containment_values()
2418 max_sclk = state->performance_levels[i].sclk; in si_populate_power_containment_values()
2425 return -EINVAL; in si_populate_power_containment_values()
2436 if (min_sclk < state->performance_levels[0].sclk) in si_populate_power_containment_values()
2437 min_sclk = state->performance_levels[0].sclk; in si_populate_power_containment_values()
2440 return -EINVAL; in si_populate_power_containment_values()
2442 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, in si_populate_power_containment_values()
2443 state->performance_levels[i-1].vddc, &vddc); in si_populate_power_containment_values()
2451 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, in si_populate_power_containment_values()
2452 state->performance_levels[i].vddc, &vddc); in si_populate_power_containment_values()
2463 …smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / ma… in si_populate_power_containment_values()
2464 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; in si_populate_power_containment_values()
2465 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; in si_populate_power_containment_values()
2466 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; in si_populate_power_containment_values()
2467 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); in si_populate_power_containment_values()
2480 bool enable_sq_ramping = ni_pi->enable_sq_ramping; in si_populate_sq_ramping_values()
2483 if (state->performance_level_count == 0) in si_populate_sq_ramping_values()
2484 return -EINVAL; in si_populate_sq_ramping_values()
2486 if (smc_state->levelCount != state->performance_level_count) in si_populate_sq_ramping_values()
2487 return -EINVAL; in si_populate_sq_ramping_values()
2489 if (adev->pm.dpm.sq_ramping_threshold == 0) in si_populate_sq_ramping_values()
2490 return -EINVAL; in si_populate_sq_ramping_values()
2507 for (i = 0; i < state->performance_level_count; i++) { in si_populate_sq_ramping_values()
2511 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) && in si_populate_sq_ramping_values()
2523 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); in si_populate_sq_ramping_values()
2524 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); in si_populate_sq_ramping_values()
2538 if (ni_pi->enable_power_containment) { in si_enable_power_containment()
2543 ret = -EINVAL; in si_enable_power_containment()
2544 ni_pi->pc_enabled = false; in si_enable_power_containment()
2546 ni_pi->pc_enabled = true; in si_enable_power_containment()
2552 ret = -EINVAL; in si_enable_power_containment()
2553 ni_pi->pc_enabled = false; in si_enable_power_containment()
2564 struct si_dte_data *dte_data = &si_pi->dte_data; in si_initialize_smc_dte_tables()
2571 si_pi->enable_dte = false; in si_initialize_smc_dte_tables()
2573 if (si_pi->enable_dte == false) in si_initialize_smc_dte_tables()
2576 if (dte_data->k <= 0) in si_initialize_smc_dte_tables()
2577 return -EINVAL; in si_initialize_smc_dte_tables()
2581 si_pi->enable_dte = false; in si_initialize_smc_dte_tables()
2582 return -ENOMEM; in si_initialize_smc_dte_tables()
2585 table_size = dte_data->k; in si_initialize_smc_dte_tables()
2590 tdep_count = dte_data->tdep_count; in si_initialize_smc_dte_tables()
2594 dte_tables->K = cpu_to_be32(table_size); in si_initialize_smc_dte_tables()
2595 dte_tables->T0 = cpu_to_be32(dte_data->t0); in si_initialize_smc_dte_tables()
2596 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); in si_initialize_smc_dte_tables()
2597 dte_tables->WindowSize = dte_data->window_size; in si_initialize_smc_dte_tables()
2598 dte_tables->temp_select = dte_data->temp_select; in si_initialize_smc_dte_tables()
2599 dte_tables->DTE_mode = dte_data->dte_mode; in si_initialize_smc_dte_tables()
2600 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); in si_initialize_smc_dte_tables()
2603 table_size--; in si_initialize_smc_dte_tables()
2606 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); in si_initialize_smc_dte_tables()
2607 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); in si_initialize_smc_dte_tables()
2610 dte_tables->Tdep_count = tdep_count; in si_initialize_smc_dte_tables()
2613 dte_tables->T_limits[i] = dte_data->t_limits[i]; in si_initialize_smc_dte_tables()
2614 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); in si_initialize_smc_dte_tables()
2615 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); in si_initialize_smc_dte_tables()
2618 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start, in si_initialize_smc_dte_tables()
2621 si_pi->sram_end); in si_initialize_smc_dte_tables()
2632 &adev->pm.dpm.dyn_state.cac_leakage_table; in si_get_cac_std_voltage_max_min()
2637 return -EINVAL; in si_get_cac_std_voltage_max_min()
2642 for (i = 0; i < table->count; i++) { in si_get_cac_std_voltage_max_min()
2643 if (table->entries[i].vddc > *max) in si_get_cac_std_voltage_max_min()
2644 *max = table->entries[i].vddc; in si_get_cac_std_voltage_max_min()
2645 if (table->entries[i].vddc < *min) in si_get_cac_std_voltage_max_min()
2646 *min = table->entries[i].vddc; in si_get_cac_std_voltage_max_min()
2649 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) in si_get_cac_std_voltage_max_min()
2650 return -EINVAL; in si_get_cac_std_voltage_max_min()
2652 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; in si_get_cac_std_voltage_max_min()
2655 return -EINVAL; in si_get_cac_std_voltage_max_min()
2660 return -EINVAL; in si_get_cac_std_voltage_max_min()
2667 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / in si_get_cac_std_voltage_step()
2677 u32 leakage; in si_init_dte_leakage_table() local
2690 voltage = vddc_max - (vddc_step * j); in si_init_dte_leakage_table()
2693 &si_pi->powertune_data->leakage_coefficients, in si_init_dte_leakage_table()
2696 si_pi->dyn_powertune_data.cac_leakage, in si_init_dte_leakage_table()
2697 &leakage); in si_init_dte_leakage_table()
2699 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; in si_init_dte_leakage_table()
2704 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = in si_init_dte_leakage_table()
2716 u32 leakage; in si_init_simplified_leakage_table() local
2725 voltage = vddc_max - (vddc_step * j); in si_init_simplified_leakage_table()
2728 &si_pi->powertune_data->leakage_coefficients, in si_init_simplified_leakage_table()
2729 si_pi->powertune_data->fixed_kt, in si_init_simplified_leakage_table()
2731 si_pi->dyn_powertune_data.cac_leakage, in si_init_simplified_leakage_table()
2732 &leakage); in si_init_simplified_leakage_table()
2734 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; in si_init_simplified_leakage_table()
2740 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = in si_init_simplified_leakage_table()
2757 if (ni_pi->enable_cac == false) in si_initialize_smc_cac_tables()
2762 return -ENOMEM; in si_initialize_smc_cac_tables()
2765 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); in si_initialize_smc_cac_tables()
2768 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage; in si_initialize_smc_cac_tables()
2769 si_pi->dyn_powertune_data.dc_pwr_value = in si_initialize_smc_cac_tables()
2770 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; in si_initialize_smc_cac_tables()
2771 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev); in si_initialize_smc_cac_tables()
2772 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; in si_initialize_smc_cac_tables()
2774 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; in si_initialize_smc_cac_tables()
2781 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); in si_initialize_smc_cac_tables()
2785 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) in si_initialize_smc_cac_tables()
2795 load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; in si_initialize_smc_cac_tables()
2797 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); in si_initialize_smc_cac_tables()
2798 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; in si_initialize_smc_cac_tables()
2799 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; in si_initialize_smc_cac_tables()
2800 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); in si_initialize_smc_cac_tables()
2801 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); in si_initialize_smc_cac_tables()
2802 cac_tables->R_LL = cpu_to_be32(load_line_slope); in si_initialize_smc_cac_tables()
2803 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); in si_initialize_smc_cac_tables()
2804 cac_tables->calculation_repeats = cpu_to_be32(2); in si_initialize_smc_cac_tables()
2805 cac_tables->dc_cac = cpu_to_be32(0); in si_initialize_smc_cac_tables()
2806 cac_tables->log2_PG_LKG_SCALE = 12; in si_initialize_smc_cac_tables()
2807 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; in si_initialize_smc_cac_tables()
2808 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); in si_initialize_smc_cac_tables()
2809 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); in si_initialize_smc_cac_tables()
2811 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start, in si_initialize_smc_cac_tables()
2814 si_pi->sram_end); in si_initialize_smc_cac_tables()
2823 ni_pi->enable_cac = false; in si_initialize_smc_cac_tables()
2824 ni_pi->enable_power_containment = false; in si_initialize_smc_cac_tables()
2839 return -EINVAL; in si_program_cac_config_registers()
2841 while (config_regs->offset != 0xFFFFFFFF) { in si_program_cac_config_registers()
2842 switch (config_regs->type) { in si_program_cac_config_registers()
2844 offset = SMC_CG_IND_START + config_regs->offset; in si_program_cac_config_registers()
2849 data = RREG32(config_regs->offset); in si_program_cac_config_registers()
2853 data &= ~config_regs->mask; in si_program_cac_config_registers()
2854 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); in si_program_cac_config_registers()
2856 switch (config_regs->type) { in si_program_cac_config_registers()
2858 offset = SMC_CG_IND_START + config_regs->offset; in si_program_cac_config_registers()
2863 WREG32(config_regs->offset, data); in si_program_cac_config_registers()
2877 if ((ni_pi->enable_cac == false) || in si_initialize_hardware_cac_manager()
2878 (ni_pi->cac_configuration_required == false)) in si_initialize_hardware_cac_manager()
2881 ret = si_program_cac_config_registers(adev, si_pi->lcac_config); in si_initialize_hardware_cac_manager()
2884 ret = si_program_cac_config_registers(adev, si_pi->cac_override); in si_initialize_hardware_cac_manager()
2887 ret = si_program_cac_config_registers(adev, si_pi->cac_weights); in si_initialize_hardware_cac_manager()
2903 if (ni_pi->enable_cac) { in si_enable_smc_cac()
2906 if (ni_pi->support_cac_long_term_average) { in si_enable_smc_cac()
2909 ni_pi->support_cac_long_term_average = false; in si_enable_smc_cac()
2914 ret = -EINVAL; in si_enable_smc_cac()
2915 ni_pi->cac_enabled = false; in si_enable_smc_cac()
2917 ni_pi->cac_enabled = true; in si_enable_smc_cac()
2920 if (si_pi->enable_dte) { in si_enable_smc_cac()
2923 ret = -EINVAL; in si_enable_smc_cac()
2926 } else if (ni_pi->cac_enabled) { in si_enable_smc_cac()
2927 if (si_pi->enable_dte) in si_enable_smc_cac()
2932 ni_pi->cac_enabled = false; in si_enable_smc_cac()
2934 if (ni_pi->support_cac_long_term_average) in si_enable_smc_cac()
2954 if (si_pi->spll_table_start == 0) in si_init_smc_spll_table()
2955 return -EINVAL; in si_init_smc_spll_table()
2959 return -ENOMEM; in si_init_smc_spll_table()
2975 ret = -EINVAL; in si_init_smc_spll_table()
2977 ret = -EINVAL; in si_init_smc_spll_table()
2979 ret = -EINVAL; in si_init_smc_spll_table()
2981 ret = -EINVAL; in si_init_smc_spll_table()
2988 spll_table->freq[i] = cpu_to_be32(tmp); in si_init_smc_spll_table()
2992 spll_table->ss[i] = cpu_to_be32(tmp); in si_init_smc_spll_table()
2999 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start, in si_init_smc_spll_table()
3002 si_pi->sram_end); in si_init_smc_spll_table()
3005 ni_pi->enable_power_containment = false; in si_init_smc_spll_table()
3019 for (i = 0; i < si_pi->leakage_voltage.count; i++){ in si_get_lower_of_leakage_and_vce_voltage()
3020 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) in si_get_lower_of_leakage_and_vce_voltage()
3021 highest_leakage = si_pi->leakage_voltage.entries[i].voltage; in si_get_lower_of_leakage_and_vce_voltage()
3024 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) in si_get_lower_of_leakage_and_vce_voltage()
3034 int ret = -EINVAL; in si_get_vce_clock_voltage()
3036 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in si_get_vce_clock_voltage()
3039 (table && (table->count == 0))) { in si_get_vce_clock_voltage()
3044 for (i = 0; i < table->count; i++) { in si_get_vce_clock_voltage()
3045 if ((evclk <= table->entries[i].evclk) && in si_get_vce_clock_voltage()
3046 (ecclk <= table->entries[i].ecclk)) { in si_get_vce_clock_voltage()
3047 *voltage = table->entries[i].v; in si_get_vce_clock_voltage()
3055 *voltage = table->entries[table->count - 1].v; in si_get_vce_clock_voltage()
3066 /* we never hit the non-gddr5 limit so disable it */ in si_dpm_vblank_too_short()
3067 u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0; in si_dpm_vblank_too_short()
3106 return -EINVAL; in ni_copy_and_switch_arb_sets()
3131 return -EINVAL; in ni_copy_and_switch_arb_sets()
3148 eg_pi->current_rps = *rps; in ni_update_current_ps()
3149 ni_pi->current_ps = *new_ps; in ni_update_current_ps()
3150 eg_pi->current_rps.ps_priv = &ni_pi->current_ps; in ni_update_current_ps()
3151 adev->pm.dpm.current_ps = &eg_pi->current_rps; in ni_update_current_ps()
3161 eg_pi->requested_rps = *rps; in ni_update_requested_ps()
3162 ni_pi->requested_ps = *new_ps; in ni_update_requested_ps()
3163 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps; in ni_update_requested_ps()
3164 adev->pm.dpm.requested_ps = &eg_pi->requested_rps; in ni_update_requested_ps()
3174 if ((new_ps->vclk == old_ps->vclk) && in ni_set_uvd_clock_before_set_eng_clock()
3175 (new_ps->dclk == old_ps->dclk)) in ni_set_uvd_clock_before_set_eng_clock()
3178 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= in ni_set_uvd_clock_before_set_eng_clock()
3179 current_state->performance_levels[current_state->performance_level_count - 1].sclk) in ni_set_uvd_clock_before_set_eng_clock()
3182 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_before_set_eng_clock()
3192 if ((new_ps->vclk == old_ps->vclk) && in ni_set_uvd_clock_after_set_eng_clock()
3193 (new_ps->dclk == old_ps->dclk)) in ni_set_uvd_clock_after_set_eng_clock()
3196 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk < in ni_set_uvd_clock_after_set_eng_clock()
3197 current_state->performance_levels[current_state->performance_level_count - 1].sclk) in ni_set_uvd_clock_after_set_eng_clock()
3200 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_after_set_eng_clock()
3207 for (i = 0; i < table->count; i++) in btc_find_voltage()
3208 if (voltage <= table->entries[i].value) in btc_find_voltage()
3209 return table->entries[i].value; in btc_find_voltage()
3211 return table->entries[table->count - 1].value; in btc_find_voltage()
3219 if ((clocks == NULL) || (clocks->count == 0)) in btc_find_valid_clock()
3222 for (i = 0; i < clocks->count; i++) { in btc_find_valid_clock()
3223 if (clocks->values[i] >= requested_clock) in btc_find_valid_clock()
3224 return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock; in btc_find_valid_clock()
3227 return (clocks->values[clocks->count - 1] < max_clock) ? in btc_find_valid_clock()
3228 clocks->values[clocks->count - 1] : max_clock; in btc_find_valid_clock()
3234 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values, in btc_get_valid_mclk()
3241 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values, in btc_get_valid_sclk()
3250 if ((table == NULL) || (table->count == 0)) { in btc_get_max_clock_from_voltage_dependency_table()
3255 for (i = 0; i < table->count; i++) { in btc_get_max_clock_from_voltage_dependency_table()
3256 if (clock < table->entries[i].clk) in btc_get_max_clock_from_voltage_dependency_table()
3257 clock = table->entries[i].clk; in btc_get_max_clock_from_voltage_dependency_table()
3267 if ((table == NULL) || (table->count == 0)) in btc_apply_voltage_dependency_rules()
3270 for (i= 0; i < table->count; i++) { in btc_apply_voltage_dependency_rules()
3271 if (clock <= table->entries[i].clk) { in btc_apply_voltage_dependency_rules()
3272 if (*voltage < table->entries[i].v) in btc_apply_voltage_dependency_rules()
3273 *voltage = (u16)((table->entries[i].v < max_voltage) ? in btc_apply_voltage_dependency_rules()
3274 table->entries[i].v : max_voltage); in btc_apply_voltage_dependency_rules()
3287 if ((pl->mclk == 0) || (pl->sclk == 0)) in btc_adjust_clock_combinations()
3290 if (pl->mclk == pl->sclk) in btc_adjust_clock_combinations()
3293 if (pl->mclk > pl->sclk) { in btc_adjust_clock_combinations()
3294 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
3295 pl->sclk = btc_get_valid_sclk(adev, in btc_adjust_clock_combinations()
3296 max_limits->sclk, in btc_adjust_clock_combinations()
3297 (pl->mclk + in btc_adjust_clock_combinations()
3298 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) / in btc_adjust_clock_combinations()
3299 adev->pm.dpm.dyn_state.mclk_sclk_ratio); in btc_adjust_clock_combinations()
3301 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta) in btc_adjust_clock_combinations()
3302 pl->mclk = btc_get_valid_mclk(adev, in btc_adjust_clock_combinations()
3303 max_limits->mclk, in btc_adjust_clock_combinations()
3304 pl->sclk - in btc_adjust_clock_combinations()
3305 adev->pm.dpm.dyn_state.sclk_mclk_delta); in btc_adjust_clock_combinations()
3320 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { in btc_apply_voltage_delta_rules()
3321 new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table, in btc_apply_voltage_delta_rules()
3322 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta)); in btc_apply_voltage_delta_rules()
3326 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { in btc_apply_voltage_delta_rules()
3327 new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table, in btc_apply_voltage_delta_rules()
3328 (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta)); in btc_apply_voltage_delta_rules()
3359 return -EINVAL; in r600_calculate_at()
3362 t1 = (t * (k - 100)); in r600_calculate_at()
3366 al = a - ah; in r600_calculate_at()
3368 *th = t - ah; in r600_calculate_at()
3400 pi->max_vddc = 0; in rv770_get_max_vddc()
3402 pi->max_vddc = vddc; in rv770_get_max_vddc()
3410 pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss, in rv770_get_engine_memory_ss()
3412 pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss, in rv770_get_engine_memory_ss()
3415 if (pi->sclk_ss || pi->mclk_ss) in rv770_get_engine_memory_ss()
3416 pi->dynamic_ss = true; in rv770_get_engine_memory_ss()
3418 pi->dynamic_ss = false; in rv770_get_engine_memory_ss()
3435 if (adev->asic_type == CHIP_HAINAN) { in si_apply_state_adjust_rules()
3436 if ((adev->pdev->revision == 0x81) || in si_apply_state_adjust_rules()
3437 (adev->pdev->revision == 0xC3) || in si_apply_state_adjust_rules()
3438 (adev->pdev->device == 0x6664) || in si_apply_state_adjust_rules()
3439 (adev->pdev->device == 0x6665) || in si_apply_state_adjust_rules()
3440 (adev->pdev->device == 0x6667)) { in si_apply_state_adjust_rules()
3443 if ((adev->pdev->revision == 0xC3) || in si_apply_state_adjust_rules()
3444 (adev->pdev->device == 0x6665)) { in si_apply_state_adjust_rules()
3448 } else if (adev->asic_type == CHIP_OLAND) { in si_apply_state_adjust_rules()
3449 if ((adev->pdev->revision == 0xC7) || in si_apply_state_adjust_rules()
3450 (adev->pdev->revision == 0x80) || in si_apply_state_adjust_rules()
3451 (adev->pdev->revision == 0x81) || in si_apply_state_adjust_rules()
3452 (adev->pdev->revision == 0x83) || in si_apply_state_adjust_rules()
3453 (adev->pdev->revision == 0x87) || in si_apply_state_adjust_rules()
3454 (adev->pdev->device == 0x6604) || in si_apply_state_adjust_rules()
3455 (adev->pdev->device == 0x6605)) { in si_apply_state_adjust_rules()
3460 if (rps->vce_active) { in si_apply_state_adjust_rules()
3461 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; in si_apply_state_adjust_rules()
3462 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; in si_apply_state_adjust_rules()
3463 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk, in si_apply_state_adjust_rules()
3466 rps->evclk = 0; in si_apply_state_adjust_rules()
3467 rps->ecclk = 0; in si_apply_state_adjust_rules()
3470 if ((adev->pm.dpm.new_active_crtc_count > 1) || in si_apply_state_adjust_rules()
3474 if (rps->vclk || rps->dclk) { in si_apply_state_adjust_rules()
3479 if (adev->pm.ac_power) in si_apply_state_adjust_rules()
3480 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in si_apply_state_adjust_rules()
3482 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in si_apply_state_adjust_rules()
3484 for (i = ps->performance_level_count - 2; i >= 0; i--) { in si_apply_state_adjust_rules()
3485 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) in si_apply_state_adjust_rules()
3486 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; in si_apply_state_adjust_rules()
3488 if (adev->pm.ac_power == false) { in si_apply_state_adjust_rules()
3489 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3490 if (ps->performance_levels[i].mclk > max_limits->mclk) in si_apply_state_adjust_rules()
3491 ps->performance_levels[i].mclk = max_limits->mclk; in si_apply_state_adjust_rules()
3492 if (ps->performance_levels[i].sclk > max_limits->sclk) in si_apply_state_adjust_rules()
3493 ps->performance_levels[i].sclk = max_limits->sclk; in si_apply_state_adjust_rules()
3494 if (ps->performance_levels[i].vddc > max_limits->vddc) in si_apply_state_adjust_rules()
3495 ps->performance_levels[i].vddc = max_limits->vddc; in si_apply_state_adjust_rules()
3496 if (ps->performance_levels[i].vddci > max_limits->vddci) in si_apply_state_adjust_rules()
3497 ps->performance_levels[i].vddci = max_limits->vddci; in si_apply_state_adjust_rules()
3502 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3504 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
3506 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
3509 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3511 if (ps->performance_levels[i].sclk > max_sclk_vddc) in si_apply_state_adjust_rules()
3512 ps->performance_levels[i].sclk = max_sclk_vddc; in si_apply_state_adjust_rules()
3515 if (ps->performance_levels[i].mclk > max_mclk_vddci) in si_apply_state_adjust_rules()
3516 ps->performance_levels[i].mclk = max_mclk_vddci; in si_apply_state_adjust_rules()
3519 if (ps->performance_levels[i].mclk > max_mclk_vddc) in si_apply_state_adjust_rules()
3520 ps->performance_levels[i].mclk = max_mclk_vddc; in si_apply_state_adjust_rules()
3523 if (ps->performance_levels[i].mclk > max_mclk) in si_apply_state_adjust_rules()
3524 ps->performance_levels[i].mclk = max_mclk; in si_apply_state_adjust_rules()
3527 if (ps->performance_levels[i].sclk > max_sclk) in si_apply_state_adjust_rules()
3528 ps->performance_levels[i].sclk = max_sclk; in si_apply_state_adjust_rules()
3535 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in si_apply_state_adjust_rules()
3536 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; in si_apply_state_adjust_rules()
3538 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3539 vddci = ps->performance_levels[0].vddci; in si_apply_state_adjust_rules()
3543 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; in si_apply_state_adjust_rules()
3544 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; in si_apply_state_adjust_rules()
3546 sclk = ps->performance_levels[0].sclk; in si_apply_state_adjust_rules()
3547 vddc = ps->performance_levels[0].vddc; in si_apply_state_adjust_rules()
3550 if (rps->vce_active) { in si_apply_state_adjust_rules()
3551 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) in si_apply_state_adjust_rules()
3552 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; in si_apply_state_adjust_rules()
3553 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk) in si_apply_state_adjust_rules()
3554 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk; in si_apply_state_adjust_rules()
3557 /* adjusted low state */ in si_apply_state_adjust_rules()
3558 ps->performance_levels[0].sclk = sclk; in si_apply_state_adjust_rules()
3559 ps->performance_levels[0].mclk = mclk; in si_apply_state_adjust_rules()
3560 ps->performance_levels[0].vddc = vddc; in si_apply_state_adjust_rules()
3561 ps->performance_levels[0].vddci = vddci; in si_apply_state_adjust_rules()
3564 sclk = ps->performance_levels[0].sclk; in si_apply_state_adjust_rules()
3565 for (i = 1; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3566 if (sclk < ps->performance_levels[i].sclk) in si_apply_state_adjust_rules()
3567 sclk = ps->performance_levels[i].sclk; in si_apply_state_adjust_rules()
3569 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3570 ps->performance_levels[i].sclk = sclk; in si_apply_state_adjust_rules()
3571 ps->performance_levels[i].vddc = vddc; in si_apply_state_adjust_rules()
3574 for (i = 1; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3575 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) in si_apply_state_adjust_rules()
3576 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; in si_apply_state_adjust_rules()
3577 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) in si_apply_state_adjust_rules()
3578 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; in si_apply_state_adjust_rules()
3583 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3584 for (i = 1; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3585 if (mclk < ps->performance_levels[i].mclk) in si_apply_state_adjust_rules()
3586 mclk = ps->performance_levels[i].mclk; in si_apply_state_adjust_rules()
3588 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3589 ps->performance_levels[i].mclk = mclk; in si_apply_state_adjust_rules()
3590 ps->performance_levels[i].vddci = vddci; in si_apply_state_adjust_rules()
3593 for (i = 1; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3594 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) in si_apply_state_adjust_rules()
3595 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; in si_apply_state_adjust_rules()
3596 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) in si_apply_state_adjust_rules()
3597 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; in si_apply_state_adjust_rules()
3601 for (i = 0; i < ps->performance_level_count; i++) in si_apply_state_adjust_rules()
3603 &ps->performance_levels[i]); in si_apply_state_adjust_rules()
3605 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3606 if (ps->performance_levels[i].vddc < min_vce_voltage) in si_apply_state_adjust_rules()
3607 ps->performance_levels[i].vddc = min_vce_voltage; in si_apply_state_adjust_rules()
3608 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3609 ps->performance_levels[i].sclk, in si_apply_state_adjust_rules()
3610 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3611 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
3612 ps->performance_levels[i].mclk, in si_apply_state_adjust_rules()
3613 max_limits->vddci, &ps->performance_levels[i].vddci); in si_apply_state_adjust_rules()
3614 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
3615 ps->performance_levels[i].mclk, in si_apply_state_adjust_rules()
3616 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3617 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, in si_apply_state_adjust_rules()
3618 adev->clock.current_dispclk, in si_apply_state_adjust_rules()
3619 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3622 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3624 max_limits->vddc, max_limits->vddci, in si_apply_state_adjust_rules()
3625 &ps->performance_levels[i].vddc, in si_apply_state_adjust_rules()
3626 &ps->performance_levels[i].vddci); in si_apply_state_adjust_rules()
3629 ps->dc_compatible = true; in si_apply_state_adjust_rules()
3630 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3631 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in si_apply_state_adjust_rules()
3632 ps->dc_compatible = false; in si_apply_state_adjust_rules()
3643 si_pi->soft_regs_start + reg_offset, value,
3644 si_pi->sram_end);
3654 si_pi->soft_regs_start + reg_offset, in si_write_smc_soft_register()
3655 value, si_pi->sram_end); in si_write_smc_soft_register()
3677 density = (1 << (row + column - 20 + bank)) * width; in si_is_special_1gb_platform()
3679 if ((adev->pdev->device == 0x6819) && in si_is_special_1gb_platform()
3696 si_pi->leakage_voltage.entries[count].voltage = vddc; in si_get_leakage_vddc()
3697 si_pi->leakage_voltage.entries[count].leakage_index = in si_get_leakage_vddc()
3702 si_pi->leakage_voltage.count = count; in si_get_leakage_vddc()
3712 return -EINVAL; in si_get_leakage_voltage_from_leakage_index()
3715 return -EINVAL; in si_get_leakage_voltage_from_leakage_index()
3718 return -EINVAL; in si_get_leakage_voltage_from_leakage_index()
3721 return -EINVAL; in si_get_leakage_voltage_from_leakage_index()
3723 for (i = 0; i < si_pi->leakage_voltage.count; i++) { in si_get_leakage_voltage_from_leakage_index()
3724 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { in si_get_leakage_voltage_from_leakage_index()
3725 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; in si_get_leakage_voltage_from_leakage_index()
3729 return -EAGAIN; in si_get_leakage_voltage_from_leakage_index()
3760 if (pi->thermal_protection) in si_set_dpm_event_sources()
3774 if (!(pi->active_auto_throttle_sources & (1 << source))) { in si_enable_auto_throttle_source()
3775 pi->active_auto_throttle_sources |= 1 << source; in si_enable_auto_throttle_source()
3776 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); in si_enable_auto_throttle_source()
3779 if (pi->active_auto_throttle_sources & (1 << source)) { in si_enable_auto_throttle_source()
3780 pi->active_auto_throttle_sources &= ~(1 << source); in si_enable_auto_throttle_source()
3781 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); in si_enable_auto_throttle_source()
3816 return -EINVAL;
3832 0 : -EINVAL;
3848 return -EINVAL; in si_restrict_performance_levels_before_switch()
3851 0 : -EINVAL; in si_restrict_performance_levels_before_switch()
3858 struct amdgpu_ps *rps = adev->pm.dpm.current_ps; in si_dpm_force_performance_level()
3860 u32 levels = ps->performance_level_count; in si_dpm_force_performance_level()
3864 return -EINVAL; in si_dpm_force_performance_level()
3867 return -EINVAL; in si_dpm_force_performance_level()
3870 return -EINVAL; in si_dpm_force_performance_level()
3873 return -EINVAL; in si_dpm_force_performance_level()
3876 return -EINVAL; in si_dpm_force_performance_level()
3879 return -EINVAL; in si_dpm_force_performance_level()
3882 adev->pm.dpm.forced_level = level; in si_dpm_force_performance_level()
3891 0 : -EINVAL;
3898 0 : -EINVAL; in si_set_sw_state()
3904 return -EINVAL; in si_halt_smc()
3907 0 : -EINVAL; in si_halt_smc()
3913 return -EINVAL; in si_resume_smc()
3916 0 : -EINVAL; in si_resume_smc()
3941 &tmp, si_pi->sram_end); in si_process_firmware_header()
3945 si_pi->state_table_start = tmp; in si_process_firmware_header()
3950 &tmp, si_pi->sram_end); in si_process_firmware_header()
3954 si_pi->soft_regs_start = tmp; in si_process_firmware_header()
3959 &tmp, si_pi->sram_end); in si_process_firmware_header()
3963 si_pi->mc_reg_table_start = tmp; in si_process_firmware_header()
3968 &tmp, si_pi->sram_end); in si_process_firmware_header()
3972 si_pi->fan_table_start = tmp; in si_process_firmware_header()
3977 &tmp, si_pi->sram_end); in si_process_firmware_header()
3981 si_pi->arb_table_start = tmp; in si_process_firmware_header()
3986 &tmp, si_pi->sram_end); in si_process_firmware_header()
3990 si_pi->cac_table_start = tmp; in si_process_firmware_header()
3995 &tmp, si_pi->sram_end); in si_process_firmware_header()
3999 si_pi->dte_table_start = tmp; in si_process_firmware_header()
4004 &tmp, si_pi->sram_end); in si_process_firmware_header()
4008 si_pi->spll_table_start = tmp; in si_process_firmware_header()
4013 &tmp, si_pi->sram_end); in si_process_firmware_header()
4017 si_pi->papm_cfg_table_start = tmp; in si_process_firmware_header()
4026 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in si_read_clock_registers()
4027 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); in si_read_clock_registers()
4028 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); in si_read_clock_registers()
4029 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); in si_read_clock_registers()
4030 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); in si_read_clock_registers()
4031 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); in si_read_clock_registers()
4032 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); in si_read_clock_registers()
4033 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); in si_read_clock_registers()
4034 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); in si_read_clock_registers()
4035 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in si_read_clock_registers()
4036 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); in si_read_clock_registers()
4037 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); in si_read_clock_registers()
4038 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); in si_read_clock_registers()
4039 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); in si_read_clock_registers()
4040 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); in si_read_clock_registers()
4075 for (i = 0; i < adev->usec_timeout; i++) {
4092 0 : -EINVAL; in si_notify_smc_display_change()
4103 voltage_response_time = (u32)adev->pm.dpm.voltage_response_time; in si_program_response_times()
4129 if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0) in si_program_ds_registers()
4134 if (eg_pi->sclk_deep_sleep) { in si_program_ds_registers()
4147 if (adev->pm.dpm.new_active_crtc_count > 0) in si_program_display_gap()
4152 if (adev->pm.dpm.new_active_crtc_count > 1) in si_program_display_gap()
4162 if ((adev->pm.dpm.new_active_crtc_count > 0) && in si_program_display_gap()
4163 (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) { in si_program_display_gap()
4165 for (i = 0; i < adev->mode_info.num_crtc; i++) { in si_program_display_gap()
4166 if (adev->pm.dpm.new_active_crtcs & (1 << i)) in si_program_display_gap()
4169 if (i == adev->mode_info.num_crtc) in si_program_display_gap()
4179 /* Setting this to false forces the performance state to low if the crtcs are disabled. in si_program_display_gap()
4183 si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0); in si_program_display_gap()
4191 if (pi->sclk_ss) in si_enable_spread_spectrum()
4204 r600_calculate_u_and_p(pi->asi, in si_setup_bsp()
4207 &pi->bsp, in si_setup_bsp()
4208 &pi->bsu); in si_setup_bsp()
4210 r600_calculate_u_and_p(pi->pasi, in si_setup_bsp()
4213 &pi->pbsp, in si_setup_bsp()
4214 &pi->pbsu); in si_setup_bsp()
4217 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); in si_setup_bsp()
4218 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); in si_setup_bsp()
4220 WREG32(CG_BSP, pi->dsp); in si_setup_bsp()
4276 WREG32(CG_FTV, pi->vrc); in si_program_vc()
4293 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); in si_get_ddr3_mclk_frequency_ratio()
4307 mc_para_index = (u8)((memory_clock - 10000) / 2500); in si_get_mclk_frequency_ratio()
4314 mc_para_index = (u8)((memory_clock - 60000) / 5000); in si_get_mclk_frequency_ratio()
4325 if (mclk <= pi->mclk_strobe_mode_threshold) in si_get_strobe_mode_settings()
4328 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) in si_get_strobe_mode_settings()
4346 return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end); in si_upload_firmware()
4358 data = table->mask_low; in si_validate_phase_shedding_tables()
4367 if (table->count != num_levels) in si_validate_phase_shedding_tables()
4370 if (limits->count != (num_levels - 1)) in si_validate_phase_shedding_tables()
4382 if (voltage_table->count <= max_voltage_steps) in si_trim_voltage_table_to_fit_state_table()
4385 diff = voltage_table->count - max_voltage_steps; in si_trim_voltage_table_to_fit_state_table()
4388 voltage_table->entries[i] = voltage_table->entries[i + diff]; in si_trim_voltage_table_to_fit_state_table()
4390 voltage_table->count = max_voltage_steps; in si_trim_voltage_table_to_fit_state_table()
4400 return -EINVAL; in si_get_svi2_voltage_table()
4402 voltage_table->mask_low = 0; in si_get_svi2_voltage_table()
4403 voltage_table->phase_delay = 0; in si_get_svi2_voltage_table()
4405 voltage_table->count = voltage_dependency_table->count; in si_get_svi2_voltage_table()
4406 for (i = 0; i < voltage_table->count; i++) { in si_get_svi2_voltage_table()
4407 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; in si_get_svi2_voltage_table()
4408 voltage_table->entries[i].smio_low = 0; in si_get_svi2_voltage_table()
4421 if (pi->voltage_control) { in si_construct_voltage_tables()
4423 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); in si_construct_voltage_tables()
4427 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) in si_construct_voltage_tables()
4430 &eg_pi->vddc_voltage_table); in si_construct_voltage_tables()
4431 } else if (si_pi->voltage_control_svi2) { in si_construct_voltage_tables()
4433 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_construct_voltage_tables()
4434 &eg_pi->vddc_voltage_table); in si_construct_voltage_tables()
4438 return -EINVAL; in si_construct_voltage_tables()
4441 if (eg_pi->vddci_control) { in si_construct_voltage_tables()
4443 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); in si_construct_voltage_tables()
4447 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) in si_construct_voltage_tables()
4450 &eg_pi->vddci_voltage_table); in si_construct_voltage_tables()
4452 if (si_pi->vddci_control_svi2) { in si_construct_voltage_tables()
4454 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_construct_voltage_tables()
4455 &eg_pi->vddci_voltage_table); in si_construct_voltage_tables()
4460 if (pi->mvdd_control) { in si_construct_voltage_tables()
4462 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); in si_construct_voltage_tables()
4465 pi->mvdd_control = false; in si_construct_voltage_tables()
4469 if (si_pi->mvdd_voltage_table.count == 0) { in si_construct_voltage_tables()
4470 pi->mvdd_control = false; in si_construct_voltage_tables()
4471 return -EINVAL; in si_construct_voltage_tables()
4474 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) in si_construct_voltage_tables()
4477 &si_pi->mvdd_voltage_table); in si_construct_voltage_tables()
4480 if (si_pi->vddc_phase_shed_control) { in si_construct_voltage_tables()
4482 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); in si_construct_voltage_tables()
4484 si_pi->vddc_phase_shed_control = false; in si_construct_voltage_tables()
4486 if ((si_pi->vddc_phase_shed_table.count == 0) || in si_construct_voltage_tables()
4487 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) in si_construct_voltage_tables()
4488 si_pi->vddc_phase_shed_control = false; in si_construct_voltage_tables()
4500 for (i = 0; i < voltage_table->count; i++) in si_populate_smc_voltage_table()
4501 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); in si_populate_smc_voltage_table()
4512 if (si_pi->voltage_control_svi2) { in si_populate_smc_voltage_tables()
4514 si_pi->svc_gpio_id); in si_populate_smc_voltage_tables()
4516 si_pi->svd_gpio_id); in si_populate_smc_voltage_tables()
4520 if (eg_pi->vddc_voltage_table.count) { in si_populate_smc_voltage_tables()
4521 si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table); in si_populate_smc_voltage_tables()
4522 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = in si_populate_smc_voltage_tables()
4523 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); in si_populate_smc_voltage_tables()
4525 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { in si_populate_smc_voltage_tables()
4526 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { in si_populate_smc_voltage_tables()
4527 table->maxVDDCIndexInPPTable = i; in si_populate_smc_voltage_tables()
4533 if (eg_pi->vddci_voltage_table.count) { in si_populate_smc_voltage_tables()
4534 si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table); in si_populate_smc_voltage_tables()
4536 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = in si_populate_smc_voltage_tables()
4537 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); in si_populate_smc_voltage_tables()
4541 if (si_pi->mvdd_voltage_table.count) { in si_populate_smc_voltage_tables()
4542 si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table); in si_populate_smc_voltage_tables()
4544 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = in si_populate_smc_voltage_tables()
4545 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); in si_populate_smc_voltage_tables()
4548 if (si_pi->vddc_phase_shed_control) { in si_populate_smc_voltage_tables()
4549 if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table, in si_populate_smc_voltage_tables()
4550 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) { in si_populate_smc_voltage_tables()
4551 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table); in si_populate_smc_voltage_tables()
4553 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] = in si_populate_smc_voltage_tables()
4554 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); in si_populate_smc_voltage_tables()
4557 (u32)si_pi->vddc_phase_shed_table.phase_delay); in si_populate_smc_voltage_tables()
4559 si_pi->vddc_phase_shed_control = false; in si_populate_smc_voltage_tables()
4573 for (i = 0; i < table->count; i++) { in si_populate_voltage_value()
4574 if (value <= table->entries[i].value) { in si_populate_voltage_value()
4575 voltage->index = (u8)i; in si_populate_voltage_value()
4576 voltage->value = cpu_to_be16(table->entries[i].value); in si_populate_voltage_value()
4581 if (i >= table->count) in si_populate_voltage_value()
4582 return -EINVAL; in si_populate_voltage_value()
4593 if (pi->mvdd_control) { in si_populate_mvdd_value()
4594 if (mclk <= pi->mvdd_split_frequency) in si_populate_mvdd_value()
4595 voltage->index = 0; in si_populate_mvdd_value()
4597 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; in si_populate_mvdd_value()
4599 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); in si_populate_mvdd_value()
4610 *std_voltage = be16_to_cpu(voltage->value); in si_get_std_voltage_value()
4612 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) { in si_get_std_voltage_value()
4613 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { in si_get_std_voltage_value()
4614 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in si_get_std_voltage_value()
4615 return -EINVAL; in si_get_std_voltage_value()
4617 …for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4618 if (be16_to_cpu(voltage->value) == in si_get_std_voltage_value()
4619 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4621 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4623 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4626 …adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
4632 …for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4633 if (be16_to_cpu(voltage->value) <= in si_get_std_voltage_value()
4634 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4636 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4638 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4641 …adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
4647 if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4648 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; in si_get_std_voltage_value()
4659 voltage->index = index; in si_populate_std_voltage_value()
4660 voltage->value = cpu_to_be16(value); in si_populate_std_voltage_value()
4672 for (i = 0; i < limits->count; i++) { in si_populate_phase_shedding_value()
4673 if ((voltage <= limits->entries[i].voltage) && in si_populate_phase_shedding_value()
4674 (sclk <= limits->entries[i].sclk) && in si_populate_phase_shedding_value()
4675 (mclk <= limits->entries[i].mclk)) in si_populate_phase_shedding_value()
4679 smc_voltage->phase_settings = (u8)i; in si_populate_phase_shedding_value()
4690 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start, in si_init_arb_table_index()
4691 &tmp, si_pi->sram_end); in si_init_arb_table_index()
4698 return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start, in si_init_arb_table_index()
4699 tmp, si_pi->sram_end); in si_init_arb_table_index()
4710 0 : -EINVAL; in si_reset_to_default()
4719 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start, in si_force_switch_to_arb_f0()
4720 &tmp, si_pi->sram_end); in si_force_switch_to_arb_f0()
4746 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; in si_calculate_memory_refresh_rate()
4759 arb_regs->mc_arb_rfsh_rate = in si_populate_memory_timing_parameters()
4760 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk); in si_populate_memory_timing_parameters()
4763 pl->sclk, in si_populate_memory_timing_parameters()
4764 pl->mclk); in si_populate_memory_timing_parameters()
4770 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); in si_populate_memory_timing_parameters()
4771 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); in si_populate_memory_timing_parameters()
4772 arb_regs->mc_arb_burst_time = (u8)burst_time; in si_populate_memory_timing_parameters()
4786 for (i = 0; i < state->performance_level_count; i++) { in si_do_program_memory_timing_parameters()
4787 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs); in si_do_program_memory_timing_parameters()
4791 si_pi->arb_table_start + in si_do_program_memory_timing_parameters()
4796 si_pi->sram_end); in si_do_program_memory_timing_parameters()
4817 if (pi->mvdd_control) in si_populate_initial_mvdd_value()
4818 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table, in si_populate_initial_mvdd_value()
4819 si_pi->mvdd_bootup_value, voltage); in si_populate_initial_mvdd_value()
4835 table->initialState.level.mclk.vDLL_CNTL = in si_populate_smc_initial_state()
4836 cpu_to_be32(si_pi->clock_registers.dll_cntl); in si_populate_smc_initial_state()
4837 table->initialState.level.mclk.vMCLK_PWRMGT_CNTL = in si_populate_smc_initial_state()
4838 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); in si_populate_smc_initial_state()
4839 table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL = in si_populate_smc_initial_state()
4840 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); in si_populate_smc_initial_state()
4841 table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL = in si_populate_smc_initial_state()
4842 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); in si_populate_smc_initial_state()
4843 table->initialState.level.mclk.vMPLL_FUNC_CNTL = in si_populate_smc_initial_state()
4844 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); in si_populate_smc_initial_state()
4845 table->initialState.level.mclk.vMPLL_FUNC_CNTL_1 = in si_populate_smc_initial_state()
4846 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); in si_populate_smc_initial_state()
4847 table->initialState.level.mclk.vMPLL_FUNC_CNTL_2 = in si_populate_smc_initial_state()
4848 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); in si_populate_smc_initial_state()
4849 table->initialState.level.mclk.vMPLL_SS = in si_populate_smc_initial_state()
4850 cpu_to_be32(si_pi->clock_registers.mpll_ss1); in si_populate_smc_initial_state()
4851 table->initialState.level.mclk.vMPLL_SS2 = in si_populate_smc_initial_state()
4852 cpu_to_be32(si_pi->clock_registers.mpll_ss2); in si_populate_smc_initial_state()
4854 table->initialState.level.mclk.mclk_value = in si_populate_smc_initial_state()
4855 cpu_to_be32(initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4857 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL = in si_populate_smc_initial_state()
4858 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); in si_populate_smc_initial_state()
4859 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = in si_populate_smc_initial_state()
4860 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); in si_populate_smc_initial_state()
4861 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = in si_populate_smc_initial_state()
4862 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); in si_populate_smc_initial_state()
4863 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = in si_populate_smc_initial_state()
4864 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); in si_populate_smc_initial_state()
4865 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM = in si_populate_smc_initial_state()
4866 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); in si_populate_smc_initial_state()
4867 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = in si_populate_smc_initial_state()
4868 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); in si_populate_smc_initial_state()
4870 table->initialState.level.sclk.sclk_value = in si_populate_smc_initial_state()
4871 cpu_to_be32(initial_state->performance_levels[0].sclk); in si_populate_smc_initial_state()
4873 table->initialState.level.arbRefreshState = in si_populate_smc_initial_state()
4876 table->initialState.level.ACIndex = 0; in si_populate_smc_initial_state()
4878 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, in si_populate_smc_initial_state()
4879 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4880 &table->initialState.level.vddc); in si_populate_smc_initial_state()
4886 &table->initialState.level.vddc, in si_populate_smc_initial_state()
4890 table->initialState.level.vddc.index, in si_populate_smc_initial_state()
4891 &table->initialState.level.std_vddc); in si_populate_smc_initial_state()
4894 if (eg_pi->vddci_control) in si_populate_smc_initial_state()
4896 &eg_pi->vddci_voltage_table, in si_populate_smc_initial_state()
4897 initial_state->performance_levels[0].vddci, in si_populate_smc_initial_state()
4898 &table->initialState.level.vddci); in si_populate_smc_initial_state()
4900 if (si_pi->vddc_phase_shed_control) in si_populate_smc_initial_state()
4902 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_initial_state()
4903 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4904 initial_state->performance_levels[0].sclk, in si_populate_smc_initial_state()
4905 initial_state->performance_levels[0].mclk, in si_populate_smc_initial_state()
4906 &table->initialState.level.vddc); in si_populate_smc_initial_state()
4908 si_populate_initial_mvdd_value(adev, &table->initialState.level.mvdd); in si_populate_smc_initial_state()
4911 table->initialState.level.aT = cpu_to_be32(reg); in si_populate_smc_initial_state()
4912 table->initialState.level.bSP = cpu_to_be32(pi->dsp); in si_populate_smc_initial_state()
4913 table->initialState.level.gen2PCIE = (u8)si_pi->boot_pcie_gen; in si_populate_smc_initial_state()
4915 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { in si_populate_smc_initial_state()
4916 table->initialState.level.strobeMode = in si_populate_smc_initial_state()
4918 initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4920 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in si_populate_smc_initial_state()
4921 table->initialState.level.mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; in si_populate_smc_initial_state()
4923 table->initialState.level.mcFlags = 0; in si_populate_smc_initial_state()
4926 table->initialState.levelCount = 1; in si_populate_smc_initial_state()
4928 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; in si_populate_smc_initial_state()
4930 table->initialState.level.dpm2.MaxPS = 0; in si_populate_smc_initial_state()
4931 table->initialState.level.dpm2.NearTDPDec = 0; in si_populate_smc_initial_state()
4932 table->initialState.level.dpm2.AboveSafeInc = 0; in si_populate_smc_initial_state()
4933 table->initialState.level.dpm2.BelowSafeInc = 0; in si_populate_smc_initial_state()
4934 table->initialState.level.dpm2.PwrEfficiencyRatio = 0; in si_populate_smc_initial_state()
4937 table->initialState.level.SQPowerThrottle = cpu_to_be32(reg); in si_populate_smc_initial_state()
4940 table->initialState.level.SQPowerThrottle_2 = cpu_to_be32(reg); in si_populate_smc_initial_state()
4976 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; in si_populate_smc_acpi_state()
4977 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; in si_populate_smc_acpi_state()
4978 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; in si_populate_smc_acpi_state()
4979 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; in si_populate_smc_acpi_state()
4980 u32 dll_cntl = si_pi->clock_registers.dll_cntl; in si_populate_smc_acpi_state()
4981 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; in si_populate_smc_acpi_state()
4982 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; in si_populate_smc_acpi_state()
4983 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; in si_populate_smc_acpi_state()
4984 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; in si_populate_smc_acpi_state()
4985 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; in si_populate_smc_acpi_state()
4986 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; in si_populate_smc_acpi_state()
4990 table->ACPIState = table->initialState; in si_populate_smc_acpi_state()
4992 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; in si_populate_smc_acpi_state()
4994 if (pi->acpi_vddc) { in si_populate_smc_acpi_state()
4995 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, in si_populate_smc_acpi_state()
4996 pi->acpi_vddc, &table->ACPIState.level.vddc); in si_populate_smc_acpi_state()
5001 &table->ACPIState.level.vddc, &std_vddc); in si_populate_smc_acpi_state()
5004 table->ACPIState.level.vddc.index, in si_populate_smc_acpi_state()
5005 &table->ACPIState.level.std_vddc); in si_populate_smc_acpi_state()
5007 table->ACPIState.level.gen2PCIE = si_pi->acpi_pcie_gen; in si_populate_smc_acpi_state()
5009 if (si_pi->vddc_phase_shed_control) { in si_populate_smc_acpi_state()
5011 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_acpi_state()
5012 pi->acpi_vddc, in si_populate_smc_acpi_state()
5015 &table->ACPIState.level.vddc); in si_populate_smc_acpi_state()
5018 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, in si_populate_smc_acpi_state()
5019 pi->min_vddc_in_table, &table->ACPIState.level.vddc); in si_populate_smc_acpi_state()
5024 &table->ACPIState.level.vddc, &std_vddc); in si_populate_smc_acpi_state()
5028 table->ACPIState.level.vddc.index, in si_populate_smc_acpi_state()
5029 &table->ACPIState.level.std_vddc); in si_populate_smc_acpi_state()
5031 table->ACPIState.level.gen2PCIE = in si_populate_smc_acpi_state()
5033 si_pi->sys_pcie_mask, in si_populate_smc_acpi_state()
5034 si_pi->boot_pcie_gen, in si_populate_smc_acpi_state()
5037 if (si_pi->vddc_phase_shed_control) in si_populate_smc_acpi_state()
5039 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_acpi_state()
5040 pi->min_vddc_in_table, in si_populate_smc_acpi_state()
5043 &table->ACPIState.level.vddc); in si_populate_smc_acpi_state()
5046 if (pi->acpi_vddc) { in si_populate_smc_acpi_state()
5047 if (eg_pi->acpi_vddci) in si_populate_smc_acpi_state()
5048 si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table, in si_populate_smc_acpi_state()
5049 eg_pi->acpi_vddci, in si_populate_smc_acpi_state()
5050 &table->ACPIState.level.vddci); in si_populate_smc_acpi_state()
5061 table->ACPIState.level.mclk.vDLL_CNTL = in si_populate_smc_acpi_state()
5063 table->ACPIState.level.mclk.vMCLK_PWRMGT_CNTL = in si_populate_smc_acpi_state()
5065 table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL = in si_populate_smc_acpi_state()
5067 table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL = in si_populate_smc_acpi_state()
5069 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL = in si_populate_smc_acpi_state()
5071 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_1 = in si_populate_smc_acpi_state()
5073 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_2 = in si_populate_smc_acpi_state()
5075 table->ACPIState.level.mclk.vMPLL_SS = in si_populate_smc_acpi_state()
5076 cpu_to_be32(si_pi->clock_registers.mpll_ss1); in si_populate_smc_acpi_state()
5077 table->ACPIState.level.mclk.vMPLL_SS2 = in si_populate_smc_acpi_state()
5078 cpu_to_be32(si_pi->clock_registers.mpll_ss2); in si_populate_smc_acpi_state()
5080 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL = in si_populate_smc_acpi_state()
5082 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = in si_populate_smc_acpi_state()
5084 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = in si_populate_smc_acpi_state()
5086 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = in si_populate_smc_acpi_state()
5089 table->ACPIState.level.mclk.mclk_value = 0; in si_populate_smc_acpi_state()
5090 table->ACPIState.level.sclk.sclk_value = 0; in si_populate_smc_acpi_state()
5092 si_populate_mvdd_value(adev, 0, &table->ACPIState.level.mvdd); in si_populate_smc_acpi_state()
5094 if (eg_pi->dynamic_ac_timing) in si_populate_smc_acpi_state()
5095 table->ACPIState.level.ACIndex = 0; in si_populate_smc_acpi_state()
5097 table->ACPIState.level.dpm2.MaxPS = 0; in si_populate_smc_acpi_state()
5098 table->ACPIState.level.dpm2.NearTDPDec = 0; in si_populate_smc_acpi_state()
5099 table->ACPIState.level.dpm2.AboveSafeInc = 0; in si_populate_smc_acpi_state()
5100 table->ACPIState.level.dpm2.BelowSafeInc = 0; in si_populate_smc_acpi_state()
5101 table->ACPIState.level.dpm2.PwrEfficiencyRatio = 0; in si_populate_smc_acpi_state()
5104 table->ACPIState.level.SQPowerThrottle = cpu_to_be32(reg); in si_populate_smc_acpi_state()
5107 table->ACPIState.level.SQPowerThrottle_2 = cpu_to_be32(reg); in si_populate_smc_acpi_state()
5117 struct si_ulv_param *ulv = &si_pi->ulv; in si_populate_ulv_state()
5121 ret = si_convert_power_level_to_smc(adev, &ulv->pl, in si_populate_ulv_state()
5122 &state->level); in si_populate_ulv_state()
5124 if (eg_pi->sclk_deep_sleep) { in si_populate_ulv_state()
5126 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; in si_populate_ulv_state()
5128 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; in si_populate_ulv_state()
5130 if (ulv->one_pcie_lane_in_ulv) in si_populate_ulv_state()
5131 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; in si_populate_ulv_state()
5132 state->level.arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); in si_populate_ulv_state()
5133 state->level.ACIndex = 1; in si_populate_ulv_state()
5134 state->level.std_vddc = state->level.vddc; in si_populate_ulv_state()
5135 state->levelCount = 1; in si_populate_ulv_state()
5137 state->flags |= PPSMC_SWSTATE_FLAG_DC; in si_populate_ulv_state()
5146 struct si_ulv_param *ulv = &si_pi->ulv; in si_program_ulv_memory_timing_parameters()
5150 ret = si_populate_memory_timing_parameters(adev, &ulv->pl, in si_program_ulv_memory_timing_parameters()
5156 ulv->volt_change_delay); in si_program_ulv_memory_timing_parameters()
5159 si_pi->arb_table_start + in si_program_ulv_memory_timing_parameters()
5164 si_pi->sram_end); in si_program_ulv_memory_timing_parameters()
5173 pi->mvdd_split_frequency = 30000; in si_get_mvdd_configuration()
5179 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps; in si_init_smc_table()
5180 const struct si_ulv_param *ulv = &si_pi->ulv; in si_init_smc_table()
5181 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; in si_init_smc_table()
5188 switch (adev->pm.int_thermal_type) { in si_init_smc_table()
5191 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; in si_init_smc_table()
5194 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; in si_init_smc_table()
5197 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; in si_init_smc_table()
5201 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) in si_init_smc_table()
5202 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; in si_init_smc_table()
5204 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { in si_init_smc_table()
5205 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819)) in si_init_smc_table()
5206 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; in si_init_smc_table()
5209 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in si_init_smc_table()
5210 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; in si_init_smc_table()
5212 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) in si_init_smc_table()
5213 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; in si_init_smc_table()
5215 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) in si_init_smc_table()
5216 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; in si_init_smc_table()
5218 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { in si_init_smc_table()
5219 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; in si_init_smc_table()
5220 vr_hot_gpio = adev->pm.dpm.backbias_response_time; in si_init_smc_table()
5233 table->driverState.flags = table->initialState.flags; in si_init_smc_table()
5234 table->driverState.levelCount = table->initialState.levelCount; in si_init_smc_table()
5235 table->driverState.levels[0] = table->initialState.level; in si_init_smc_table()
5242 if (ulv->supported && ulv->pl.vddc) { in si_init_smc_table()
5243 ret = si_populate_ulv_state(adev, &table->ULVState); in si_init_smc_table()
5251 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); in si_init_smc_table()
5252 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); in si_init_smc_table()
5257 table->ULVState = table->initialState; in si_init_smc_table()
5260 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start, in si_init_smc_table()
5262 si_pi->sram_end); in si_init_smc_table()
5272 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; in si_calculate_sclk_params()
5273 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; in si_calculate_sclk_params()
5274 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; in si_calculate_sclk_params()
5275 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; in si_calculate_sclk_params()
5276 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; in si_calculate_sclk_params()
5277 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; in si_calculate_sclk_params()
5279 u32 reference_clock = adev->clock.spll.reference_freq; in si_calculate_sclk_params()
5306 if (pi->sclk_ss) { in si_calculate_sclk_params()
5324 sclk->sclk_value = engine_clock; in si_calculate_sclk_params()
5325 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; in si_calculate_sclk_params()
5326 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; in si_calculate_sclk_params()
5327 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; in si_calculate_sclk_params()
5328 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; in si_calculate_sclk_params()
5329 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; in si_calculate_sclk_params()
5330 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; in si_calculate_sclk_params()
5344 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); in si_populate_sclk_value()
5345 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); in si_populate_sclk_value()
5346 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); in si_populate_sclk_value()
5347 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); in si_populate_sclk_value()
5348 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); in si_populate_sclk_value()
5349 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); in si_populate_sclk_value()
5350 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); in si_populate_sclk_value()
5365 u32 dll_cntl = si_pi->clock_registers.dll_cntl; in si_populate_mclk_value()
5366 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; in si_populate_mclk_value()
5367 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; in si_populate_mclk_value()
5368 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; in si_populate_mclk_value()
5369 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; in si_populate_mclk_value()
5370 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; in si_populate_mclk_value()
5371 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; in si_populate_mclk_value()
5372 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; in si_populate_mclk_value()
5373 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; in si_populate_mclk_value()
5391 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { in si_populate_mclk_value()
5397 if (pi->mclk_ss) { in si_populate_mclk_value()
5401 u32 reference_clock = adev->clock.mpll.reference_freq; in si_populate_mclk_value()
5403 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) in si_populate_mclk_value()
5431 mclk->mclk_value = cpu_to_be32(memory_clock); in si_populate_mclk_value()
5432 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); in si_populate_mclk_value()
5433 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); in si_populate_mclk_value()
5434 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); in si_populate_mclk_value()
5435 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in si_populate_mclk_value()
5436 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in si_populate_mclk_value()
5437 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in si_populate_mclk_value()
5438 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); in si_populate_mclk_value()
5439 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); in si_populate_mclk_value()
5440 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); in si_populate_mclk_value()
5453 for (i = 0; i < ps->performance_level_count - 1; i++) in si_populate_smc_sp()
5454 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); in si_populate_smc_sp()
5456 smc_state->levels[ps->performance_level_count - 1].bSP = in si_populate_smc_sp()
5457 cpu_to_be32(pi->psp); in si_populate_smc_sp()
5471 if (eg_pi->pcie_performance_request && in si_convert_power_level_to_smc()
5472 (si_pi->force_pcie_gen != SI_PCIE_GEN_INVALID)) in si_convert_power_level_to_smc()
5473 level->gen2PCIE = (u8)si_pi->force_pcie_gen; in si_convert_power_level_to_smc()
5475 level->gen2PCIE = (u8)pl->pcie_gen; in si_convert_power_level_to_smc()
5477 ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk); in si_convert_power_level_to_smc()
5481 level->mcFlags = 0; in si_convert_power_level_to_smc()
5483 if (pi->mclk_stutter_mode_threshold && in si_convert_power_level_to_smc()
5484 (pl->mclk <= pi->mclk_stutter_mode_threshold) && in si_convert_power_level_to_smc()
5485 !eg_pi->uvd_enabled && in si_convert_power_level_to_smc()
5487 (adev->pm.dpm.new_active_crtc_count <= 2)) { in si_convert_power_level_to_smc()
5488 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; in si_convert_power_level_to_smc()
5491 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { in si_convert_power_level_to_smc()
5492 if (pl->mclk > pi->mclk_edc_enable_threshold) in si_convert_power_level_to_smc()
5493 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; in si_convert_power_level_to_smc()
5495 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) in si_convert_power_level_to_smc()
5496 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; in si_convert_power_level_to_smc()
5498 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk); in si_convert_power_level_to_smc()
5500 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { in si_convert_power_level_to_smc()
5501 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= in si_convert_power_level_to_smc()
5510 level->strobeMode = si_get_strobe_mode_settings(adev, in si_convert_power_level_to_smc()
5511 pl->mclk); in si_convert_power_level_to_smc()
5517 pl->sclk, in si_convert_power_level_to_smc()
5518 pl->mclk, in si_convert_power_level_to_smc()
5519 &level->mclk, in si_convert_power_level_to_smc()
5520 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); in si_convert_power_level_to_smc()
5525 &eg_pi->vddc_voltage_table, in si_convert_power_level_to_smc()
5526 pl->vddc, &level->vddc); in si_convert_power_level_to_smc()
5531 ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc); in si_convert_power_level_to_smc()
5536 level->vddc.index, &level->std_vddc); in si_convert_power_level_to_smc()
5540 if (eg_pi->vddci_control) { in si_convert_power_level_to_smc()
5541 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table, in si_convert_power_level_to_smc()
5542 pl->vddci, &level->vddci); in si_convert_power_level_to_smc()
5547 if (si_pi->vddc_phase_shed_control) { in si_convert_power_level_to_smc()
5549 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_convert_power_level_to_smc()
5550 pl->vddc, in si_convert_power_level_to_smc()
5551 pl->sclk, in si_convert_power_level_to_smc()
5552 pl->mclk, in si_convert_power_level_to_smc()
5553 &level->vddc); in si_convert_power_level_to_smc()
5558 level->MaxPoweredUpCU = si_pi->max_cu; in si_convert_power_level_to_smc()
5560 ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd); in si_convert_power_level_to_smc()
5576 if (state->performance_level_count >= 9) in si_populate_smc_t()
5577 return -EINVAL; in si_populate_smc_t()
5579 if (state->performance_level_count < 2) { in si_populate_smc_t()
5581 smc_state->levels[0].aT = cpu_to_be32(a_t); in si_populate_smc_t()
5585 smc_state->levels[0].aT = cpu_to_be32(0); in si_populate_smc_t()
5587 for (i = 0; i <= state->performance_level_count - 2; i++) { in si_populate_smc_t()
5591 state->performance_levels[i + 1].sclk, in si_populate_smc_t()
5592 state->performance_levels[i].sclk, in si_populate_smc_t()
5597 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; in si_populate_smc_t()
5601 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; in si_populate_smc_t()
5602 a_t |= CG_R(t_l * pi->bsp / 20000); in si_populate_smc_t()
5603 smc_state->levels[i].aT = cpu_to_be32(a_t); in si_populate_smc_t()
5605 high_bsp = (i == state->performance_level_count - 2) ? in si_populate_smc_t()
5606 pi->pbsp : pi->bsp; in si_populate_smc_t()
5608 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); in si_populate_smc_t()
5617 struct si_ulv_param *ulv = &si_pi->ulv; in si_disable_ulv()
5619 if (ulv->supported) in si_disable_ulv()
5621 0 : -EINVAL; in si_disable_ulv()
5630 const struct si_ulv_param *ulv = &si_pi->ulv; in si_is_state_ulv_compatible()
5634 if (state->performance_levels[0].mclk != ulv->pl.mclk) in si_is_state_ulv_compatible()
5639 for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { in si_is_state_ulv_compatible()
5640 if (adev->clock.current_dispclk <= in si_is_state_ulv_compatible()
5641 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { in si_is_state_ulv_compatible()
5642 if (ulv->pl.vddc < in si_is_state_ulv_compatible()
5643 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) in si_is_state_ulv_compatible()
5648 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0)) in si_is_state_ulv_compatible()
5658 const struct si_ulv_param *ulv = &si_pi->ulv; in si_set_power_state_conditionally_enable_ulv()
5660 if (ulv->supported) { in si_set_power_state_conditionally_enable_ulv()
5663 0 : -EINVAL; in si_set_power_state_conditionally_enable_ulv()
5680 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) in si_convert_power_state_to_smc()
5681 return -EINVAL; in si_convert_power_state_to_smc()
5683 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; in si_convert_power_state_to_smc()
5685 if (amdgpu_state->vclk && amdgpu_state->dclk) { in si_convert_power_state_to_smc()
5686 eg_pi->uvd_enabled = true; in si_convert_power_state_to_smc()
5687 if (eg_pi->smu_uvd_hs) in si_convert_power_state_to_smc()
5688 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; in si_convert_power_state_to_smc()
5690 eg_pi->uvd_enabled = false; in si_convert_power_state_to_smc()
5693 if (state->dc_compatible) in si_convert_power_state_to_smc()
5694 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; in si_convert_power_state_to_smc()
5696 smc_state->levelCount = 0; in si_convert_power_state_to_smc()
5697 for (i = 0; i < state->performance_level_count; i++) { in si_convert_power_state_to_smc()
5698 if (eg_pi->sclk_deep_sleep) { in si_convert_power_state_to_smc()
5699 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { in si_convert_power_state_to_smc()
5701 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; in si_convert_power_state_to_smc()
5703 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; in si_convert_power_state_to_smc()
5707 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i], in si_convert_power_state_to_smc()
5708 &smc_state->levels[i]); in si_convert_power_state_to_smc()
5709 smc_state->levels[i].arbRefreshState = in si_convert_power_state_to_smc()
5715 if (ni_pi->enable_power_containment) in si_convert_power_state_to_smc()
5716 smc_state->levels[i].displayWatermark = in si_convert_power_state_to_smc()
5717 (state->performance_levels[i].sclk < threshold) ? in si_convert_power_state_to_smc()
5720 smc_state->levels[i].displayWatermark = (i < 2) ? in si_convert_power_state_to_smc()
5723 if (eg_pi->dynamic_ac_timing) in si_convert_power_state_to_smc()
5724 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; in si_convert_power_state_to_smc()
5726 smc_state->levels[i].ACIndex = 0; in si_convert_power_state_to_smc()
5728 smc_state->levelCount++; in si_convert_power_state_to_smc()
5739 ni_pi->enable_power_containment = false; in si_convert_power_state_to_smc()
5743 ni_pi->enable_sq_ramping = false; in si_convert_power_state_to_smc()
5754 u32 address = si_pi->state_table_start + in si_upload_sw_state()
5756 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; in si_upload_sw_state()
5758 new_state->performance_level_count); in si_upload_sw_state()
5766 state_size, si_pi->sram_end); in si_upload_sw_state()
5772 struct si_ulv_param *ulv = &si_pi->ulv; in si_upload_ulv_state()
5775 if (ulv->supported && ulv->pl.vddc) { in si_upload_ulv_state()
5776 u32 address = si_pi->state_table_start + in si_upload_ulv_state()
5778 struct SISLANDS_SMC_SWSTATE_SINGLE *smc_state = &si_pi->smc_statetable.ULVState; in si_upload_ulv_state()
5786 state_size, si_pi->sram_end); in si_upload_ulv_state()
5797 if (adev->pm.dpm.new_active_crtc_count == 0) in si_upload_smc_data()
5800 for (i = 0; i < adev->mode_info.num_crtc; i++) { in si_upload_smc_data()
5801 if (adev->pm.dpm.new_active_crtcs & (1 << i)) { in si_upload_smc_data()
5802 amdgpu_crtc = adev->mode_info.crtcs[i]; in si_upload_smc_data()
5810 if (amdgpu_crtc->line_time <= 0) in si_upload_smc_data()
5815 amdgpu_crtc->crtc_id) != PPSMC_Result_OK) in si_upload_smc_data()
5820 amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK) in si_upload_smc_data()
5825 amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK) in si_upload_smc_data()
5837 for (i = 0, j = table->last; i < table->last; i++) { in si_set_mc_special_registers()
5839 return -EINVAL; in si_set_mc_special_registers()
5840 switch (table->mc_reg_address[i].s1) { in si_set_mc_special_registers()
5843 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS; in si_set_mc_special_registers()
5844 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP; in si_set_mc_special_registers()
5845 for (k = 0; k < table->num_entries; k++) in si_set_mc_special_registers()
5846 table->mc_reg_table_entry[k].mc_data[j] = in si_set_mc_special_registers()
5848 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); in si_set_mc_special_registers()
5852 return -EINVAL; in si_set_mc_special_registers()
5854 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS; in si_set_mc_special_registers()
5855 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP; in si_set_mc_special_registers()
5856 for (k = 0; k < table->num_entries; k++) { in si_set_mc_special_registers()
5857 table->mc_reg_table_entry[k].mc_data[j] = in si_set_mc_special_registers()
5859 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in si_set_mc_special_registers()
5860 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) in si_set_mc_special_registers()
5861 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; in si_set_mc_special_registers()
5865 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) { in si_set_mc_special_registers()
5867 return -EINVAL; in si_set_mc_special_registers()
5868 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD; in si_set_mc_special_registers()
5869 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD; in si_set_mc_special_registers()
5870 for (k = 0; k < table->num_entries; k++) in si_set_mc_special_registers()
5871 table->mc_reg_table_entry[k].mc_data[j] = in si_set_mc_special_registers()
5872 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; in si_set_mc_special_registers()
5878 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1; in si_set_mc_special_registers()
5879 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP; in si_set_mc_special_registers()
5880 for(k = 0; k < table->num_entries; k++) in si_set_mc_special_registers()
5881 table->mc_reg_table_entry[k].mc_data[j] = in si_set_mc_special_registers()
5883 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in si_set_mc_special_registers()
5891 table->last = j; in si_set_mc_special_registers()
5954 for (i = 0; i < table->last; i++) { in si_set_valid_flag()
5955 for (j = 1; j < table->num_entries; j++) { in si_set_valid_flag()
5956 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { in si_set_valid_flag()
5957 table->valid_flag |= 1 << i; in si_set_valid_flag()
5969 for (i = 0; i < table->last; i++) in si_set_s0_mc_reg_index()
5970 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? in si_set_s0_mc_reg_index()
5971 address : table->mc_reg_address[i].s1; in si_set_s0_mc_reg_index()
5980 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) in si_copy_vbios_mc_reg_table()
5981 return -EINVAL; in si_copy_vbios_mc_reg_table()
5982 if (table->num_entries > MAX_AC_TIMING_ENTRIES) in si_copy_vbios_mc_reg_table()
5983 return -EINVAL; in si_copy_vbios_mc_reg_table()
5985 for (i = 0; i < table->last; i++) in si_copy_vbios_mc_reg_table()
5986 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; in si_copy_vbios_mc_reg_table()
5987 si_table->last = table->last; in si_copy_vbios_mc_reg_table()
5989 for (i = 0; i < table->num_entries; i++) { in si_copy_vbios_mc_reg_table()
5990 si_table->mc_reg_table_entry[i].mclk_max = in si_copy_vbios_mc_reg_table()
5991 table->mc_reg_table_entry[i].mclk_max; in si_copy_vbios_mc_reg_table()
5992 for (j = 0; j < table->last; j++) { in si_copy_vbios_mc_reg_table()
5993 si_table->mc_reg_table_entry[i].mc_data[j] = in si_copy_vbios_mc_reg_table()
5994 table->mc_reg_table_entry[i].mc_data[j]; in si_copy_vbios_mc_reg_table()
5997 si_table->num_entries = table->num_entries; in si_copy_vbios_mc_reg_table()
6006 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; in si_initialize_mc_reg_table()
6012 return -ENOMEM; in si_initialize_mc_reg_table()
6058 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { in si_populate_mc_reg_addresses()
6059 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { in si_populate_mc_reg_addresses()
6062 mc_reg_table->address[i].s0 = in si_populate_mc_reg_addresses()
6063 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); in si_populate_mc_reg_addresses()
6064 mc_reg_table->address[i].s1 = in si_populate_mc_reg_addresses()
6065 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); in si_populate_mc_reg_addresses()
6069 mc_reg_table->last = (u8)i; in si_populate_mc_reg_addresses()
6080 data->value[i] = cpu_to_be32(entry->mc_data[j]); in si_convert_mc_registers()
6093 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { in si_convert_mc_reg_table_entry_to_smc()
6094 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) in si_convert_mc_reg_table_entry_to_smc()
6098 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) in si_convert_mc_reg_table_entry_to_smc()
6099 --i; in si_convert_mc_reg_table_entry_to_smc()
6101 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], in si_convert_mc_reg_table_entry_to_smc()
6102 mc_reg_table_data, si_pi->mc_reg_table.last, in si_convert_mc_reg_table_entry_to_smc()
6103 si_pi->mc_reg_table.valid_flag); in si_convert_mc_reg_table_entry_to_smc()
6113 for (i = 0; i < state->performance_level_count; i++) { in si_convert_mc_reg_table_to_smc()
6115 &state->performance_levels[i], in si_convert_mc_reg_table_to_smc()
6116 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); in si_convert_mc_reg_table_to_smc()
6125 struct si_ulv_param *ulv = &si_pi->ulv; in si_populate_mc_reg_table()
6126 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; in si_populate_mc_reg_table()
6134 si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0], in si_populate_mc_reg_table()
6135 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); in si_populate_mc_reg_table()
6137 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], in si_populate_mc_reg_table()
6138 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], in si_populate_mc_reg_table()
6139 si_pi->mc_reg_table.last, in si_populate_mc_reg_table()
6140 si_pi->mc_reg_table.valid_flag); in si_populate_mc_reg_table()
6142 if (ulv->supported && ulv->pl.vddc != 0) in si_populate_mc_reg_table()
6143 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl, in si_populate_mc_reg_table()
6144 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); in si_populate_mc_reg_table()
6146 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], in si_populate_mc_reg_table()
6147 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], in si_populate_mc_reg_table()
6148 si_pi->mc_reg_table.last, in si_populate_mc_reg_table()
6149 si_pi->mc_reg_table.valid_flag); in si_populate_mc_reg_table()
6153 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start, in si_populate_mc_reg_table()
6155 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); in si_populate_mc_reg_table()
6163 u32 address = si_pi->mc_reg_table_start + in si_upload_mc_reg_table()
6166 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; in si_upload_mc_reg_table()
6173 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], in si_upload_mc_reg_table()
6174 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, in si_upload_mc_reg_table()
6175 si_pi->sram_end); in si_upload_mc_reg_table()
6193 for (i = 0; i < state->performance_level_count; i++) { in si_get_maximum_link_speed()
6194 pcie_speed = state->performance_levels[i].pcie_gen; in si_get_maximum_link_speed()
6219 if (si_pi->force_pcie_gen == SI_PCIE_GEN_INVALID) in si_request_link_speed_change_before_state_change()
6222 current_link_speed = si_pi->force_pcie_gen; in si_request_link_speed_change_before_state_change()
6224 si_pi->force_pcie_gen = SI_PCIE_GEN_INVALID; in si_request_link_speed_change_before_state_change()
6225 si_pi->pspp_notify_required = false; in si_request_link_speed_change_before_state_change()
6232 si_pi->force_pcie_gen = SI_PCIE_GEN2; in si_request_link_speed_change_before_state_change()
6242 si_pi->force_pcie_gen = si_get_current_pcie_speed(adev); in si_request_link_speed_change_before_state_change()
6247 si_pi->pspp_notify_required = true; in si_request_link_speed_change_before_state_change()
6259 if (si_pi->pspp_notify_required) { in si_notify_link_speed_change_after_state_change()
6283 if (eg_pi->sclk_deep_sleep) {
6287 0 : -EINVAL;
6290 PPSMC_Result_OK) ? 0 : -EINVAL;
6300 if (adev->asic_type == CHIP_VERDE) { in si_set_max_cu_value()
6301 switch (adev->pdev->device) { in si_set_max_cu_value()
6307 si_pi->max_cu = 10; in si_set_max_cu_value()
6313 si_pi->max_cu = 8; in si_set_max_cu_value()
6321 si_pi->max_cu = 10; in si_set_max_cu_value()
6326 si_pi->max_cu = 8; in si_set_max_cu_value()
6329 si_pi->max_cu = 0; in si_set_max_cu_value()
6333 si_pi->max_cu = 0; in si_set_max_cu_value()
6345 for (i = 0; i < table->count; i++) { in si_patch_single_dependency_table_based_on_leakage()
6347 table->entries[i].v, in si_patch_single_dependency_table_based_on_leakage()
6350 table->entries[i].v = leakage_voltage; in si_patch_single_dependency_table_based_on_leakage()
6352 case -EAGAIN: in si_patch_single_dependency_table_based_on_leakage()
6353 return -EINVAL; in si_patch_single_dependency_table_based_on_leakage()
6354 case -EINVAL: in si_patch_single_dependency_table_based_on_leakage()
6360 for (j = (table->count - 2); j >= 0; j--) { in si_patch_single_dependency_table_based_on_leakage()
6361 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? in si_patch_single_dependency_table_based_on_leakage()
6362 table->entries[j].v : table->entries[j + 1].v; in si_patch_single_dependency_table_based_on_leakage()
6373 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in si_patch_dependency_tables_based_on_leakage()
6375 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n"); in si_patch_dependency_tables_based_on_leakage()
6377 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in si_patch_dependency_tables_based_on_leakage()
6379 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n"); in si_patch_dependency_tables_based_on_leakage()
6381 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk); in si_patch_dependency_tables_based_on_leakage()
6383 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n"); in si_patch_dependency_tables_based_on_leakage()
6393 …((amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) +… in si_set_pcie_lane_width_in_smc()
6395 …((amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIF… in si_set_pcie_lane_width_in_smc()
6423 return -EINVAL; in si_thermal_enable_alert()
6444 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); in si_thermal_set_temperature_range()
6445 return -EINVAL; in si_thermal_set_temperature_range()
6452 adev->pm.dpm.thermal.min_temp = low_temp; in si_thermal_set_temperature_range()
6453 adev->pm.dpm.thermal.max_temp = high_temp; in si_thermal_set_temperature_range()
6463 if (si_pi->fan_ctrl_is_in_default_mode) { in si_fan_ctrl_set_static_mode()
6465 si_pi->fan_ctrl_default_mode = tmp; in si_fan_ctrl_set_static_mode()
6467 si_pi->t_min = tmp; in si_fan_ctrl_set_static_mode()
6468 si_pi->fan_ctrl_is_in_default_mode = false; in si_fan_ctrl_set_static_mode()
6491 if (!si_pi->fan_table_start) { in si_thermal_setup_fan_table()
6492 adev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
6499 adev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
6503 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100; in si_thermal_setup_fan_table()
6507 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min; in si_thermal_setup_fan_table()
6508 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med; in si_thermal_setup_fan_table()
6510 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min; in si_thermal_setup_fan_table()
6511 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med; in si_thermal_setup_fan_table()
6516 fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100); in si_thermal_setup_fan_table()
6517 fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100); in si_thermal_setup_fan_table()
6518 fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100); in si_thermal_setup_fan_table()
6522 fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst); in si_thermal_setup_fan_table()
6528 fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay * in si_thermal_setup_fan_table()
6536 si_pi->fan_table_start, in si_thermal_setup_fan_table()
6539 si_pi->sram_end); in si_thermal_setup_fan_table()
6543 adev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
6556 si_pi->fan_is_controlled_by_smc = true; in si_fan_ctrl_start_smc_fan_control()
6559 return -EINVAL; in si_fan_ctrl_start_smc_fan_control()
6571 si_pi->fan_is_controlled_by_smc = false; in si_fan_ctrl_stop_smc_fan_control()
6574 return -EINVAL; in si_fan_ctrl_stop_smc_fan_control()
6586 return -EINVAL; in si_dpm_get_fan_speed_pwm()
6588 if (adev->pm.no_fan) in si_dpm_get_fan_speed_pwm()
6589 return -ENOENT; in si_dpm_get_fan_speed_pwm()
6595 return -EINVAL; in si_dpm_get_fan_speed_pwm()
6613 if (adev->pm.no_fan) in si_dpm_set_fan_speed_pwm()
6614 return -ENOENT; in si_dpm_set_fan_speed_pwm()
6616 if (si_pi->fan_is_controlled_by_smc) in si_dpm_set_fan_speed_pwm()
6617 return -EINVAL; in si_dpm_set_fan_speed_pwm()
6620 return -EINVAL; in si_dpm_set_fan_speed_pwm()
6625 return -EINVAL; in si_dpm_set_fan_speed_pwm()
6643 return -EINVAL; in si_dpm_set_fan_control_mode()
6646 /* stop auto-manage */ in si_dpm_set_fan_control_mode()
6647 if (adev->pm.dpm.fan.ucode_fan_control) in si_dpm_set_fan_control_mode()
6651 /* restart auto-manage */ in si_dpm_set_fan_control_mode()
6652 if (adev->pm.dpm.fan.ucode_fan_control) in si_dpm_set_fan_control_mode()
6668 return -EINVAL; in si_dpm_get_fan_control_mode()
6670 if (si_pi->fan_is_controlled_by_smc) in si_dpm_get_fan_control_mode()
6686 if (adev->pm.no_fan)
6687 return -ENOENT;
6689 if (adev->pm.fan_pulses_per_revolution == 0)
6690 return -ENOENT;
6694 return -ENOENT;
6707 if (adev->pm.no_fan)
6708 return -ENOENT;
6710 if (adev->pm.fan_pulses_per_revolution == 0)
6711 return -ENOENT;
6713 if ((speed < adev->pm.fan_min_rpm) ||
6714 (speed > adev->pm.fan_max_rpm))
6715 return -EINVAL;
6717 if (adev->pm.dpm.fan.ucode_fan_control)
6736 if (!si_pi->fan_ctrl_is_in_default_mode) { in si_fan_ctrl_set_default_mode()
6738 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); in si_fan_ctrl_set_default_mode()
6742 tmp |= TMIN(si_pi->t_min); in si_fan_ctrl_set_default_mode()
6744 si_pi->fan_ctrl_is_in_default_mode = true; in si_fan_ctrl_set_default_mode()
6750 if (adev->pm.dpm.fan.ucode_fan_control) { in si_thermal_start_smc_fan_control()
6760 if (adev->pm.fan_pulses_per_revolution) { in si_thermal_initialize()
6762 tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1); in si_thermal_initialize()
6782 if (adev->pm.dpm.fan.ucode_fan_control) { in si_thermal_start_thermal_controller()
6800 if (!adev->pm.no_fan) { in si_thermal_stop_thermal_controller()
6811 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; in si_dpm_enable()
6815 return -EINVAL; in si_dpm_enable()
6816 if (pi->voltage_control || si_pi->voltage_control_svi2) in si_dpm_enable()
6818 if (pi->mvdd_control) in si_dpm_enable()
6820 if (pi->voltage_control || si_pi->voltage_control_svi2) { in si_dpm_enable()
6827 if (eg_pi->dynamic_ac_timing) { in si_dpm_enable()
6830 eg_pi->dynamic_ac_timing = false; in si_dpm_enable()
6832 if (pi->dynamic_ss) in si_dpm_enable()
6834 if (pi->thermal_protection) in si_dpm_enable()
6873 if (eg_pi->dynamic_ac_timing) { in si_dpm_enable()
6944 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; in si_dpm_disable()
6951 if (pi->thermal_protection) in si_dpm_disable()
6969 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; in si_dpm_pre_set_power_state()
6973 si_apply_state_adjust_rules(adev, &eg_pi->requested_rps); in si_dpm_pre_set_power_state()
6980 struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps; in si_power_control_set_level()
7005 if ((old_rps->evclk != new_rps->evclk) || in si_set_vce_clock()
7006 (old_rps->ecclk != new_rps->ecclk)) { in si_set_vce_clock()
7008 if (new_rps->evclk || new_rps->ecclk) { in si_set_vce_clock()
7014 amdgpu_asic_set_vce_clocks(adev, new_rps->evclk, new_rps->ecclk);*/ in si_set_vce_clock()
7023 struct amdgpu_ps *new_ps = &eg_pi->requested_rps; in si_dpm_set_power_state()
7024 struct amdgpu_ps *old_ps = &eg_pi->current_rps; in si_dpm_set_power_state()
7037 if (eg_pi->pcie_performance_request) in si_dpm_set_power_state()
7070 if (eg_pi->dynamic_ac_timing) { in si_dpm_set_power_state()
7096 if (eg_pi->pcie_performance_request) in si_dpm_set_power_state()
7127 struct amdgpu_ps *new_ps = &eg_pi->requested_rps; in si_dpm_post_set_power_state()
7154 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); in si_parse_pplib_non_clock_info()
7155 rps->class = le16_to_cpu(non_clock_info->usClassification); in si_parse_pplib_non_clock_info()
7156 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); in si_parse_pplib_non_clock_info()
7159 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in si_parse_pplib_non_clock_info()
7160 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in si_parse_pplib_non_clock_info()
7161 } else if (r600_is_uvd_state(rps->class, rps->class2)) { in si_parse_pplib_non_clock_info()
7162 rps->vclk = RV770_DEFAULT_VCLK_FREQ; in si_parse_pplib_non_clock_info()
7163 rps->dclk = RV770_DEFAULT_DCLK_FREQ; in si_parse_pplib_non_clock_info()
7165 rps->vclk = 0; in si_parse_pplib_non_clock_info()
7166 rps->dclk = 0; in si_parse_pplib_non_clock_info()
7169 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) in si_parse_pplib_non_clock_info()
7170 adev->pm.dpm.boot_ps = rps; in si_parse_pplib_non_clock_info()
7171 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) in si_parse_pplib_non_clock_info()
7172 adev->pm.dpm.uvd_ps = rps; in si_parse_pplib_non_clock_info()
7184 struct rv7xx_pl *pl = &ps->performance_levels[index]; in si_parse_pplib_clock_info()
7187 ps->performance_level_count = index + 1; in si_parse_pplib_clock_info()
7189 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); in si_parse_pplib_clock_info()
7190 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; in si_parse_pplib_clock_info()
7191 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); in si_parse_pplib_clock_info()
7192 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; in si_parse_pplib_clock_info()
7194 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); in si_parse_pplib_clock_info()
7195 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); in si_parse_pplib_clock_info()
7196 pl->flags = le32_to_cpu(clock_info->si.ulFlags); in si_parse_pplib_clock_info()
7197 pl->pcie_gen = si_gen_pcie_gen_support(adev, in si_parse_pplib_clock_info()
7198 si_pi->sys_pcie_mask, in si_parse_pplib_clock_info()
7199 si_pi->boot_pcie_gen, in si_parse_pplib_clock_info()
7200 clock_info->si.ucPCIEGen); in si_parse_pplib_clock_info()
7203 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc, in si_parse_pplib_clock_info()
7206 pl->vddc = leakage_voltage; in si_parse_pplib_clock_info()
7208 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { in si_parse_pplib_clock_info()
7209 pi->acpi_vddc = pl->vddc; in si_parse_pplib_clock_info()
7210 eg_pi->acpi_vddci = pl->vddci; in si_parse_pplib_clock_info()
7211 si_pi->acpi_pcie_gen = pl->pcie_gen; in si_parse_pplib_clock_info()
7214 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && in si_parse_pplib_clock_info()
7217 si_pi->ulv.supported = false; in si_parse_pplib_clock_info()
7218 si_pi->ulv.pl = *pl; in si_parse_pplib_clock_info()
7219 si_pi->ulv.one_pcie_lane_in_ulv = false; in si_parse_pplib_clock_info()
7220 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; in si_parse_pplib_clock_info()
7221 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; in si_parse_pplib_clock_info()
7222 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; in si_parse_pplib_clock_info()
7225 if (pi->min_vddc_in_table > pl->vddc) in si_parse_pplib_clock_info()
7226 pi->min_vddc_in_table = pl->vddc; in si_parse_pplib_clock_info()
7228 if (pi->max_vddc_in_table < pl->vddc) in si_parse_pplib_clock_info()
7229 pi->max_vddc_in_table = pl->vddc; in si_parse_pplib_clock_info()
7232 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { in si_parse_pplib_clock_info()
7235 pl->mclk = adev->clock.default_mclk; in si_parse_pplib_clock_info()
7236 pl->sclk = adev->clock.default_sclk; in si_parse_pplib_clock_info()
7237 pl->vddc = vddc; in si_parse_pplib_clock_info()
7238 pl->vddci = vddci; in si_parse_pplib_clock_info()
7239 si_pi->mvdd_bootup_value = mvdd; in si_parse_pplib_clock_info()
7242 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == in si_parse_pplib_clock_info()
7244 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; in si_parse_pplib_clock_info()
7245 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in si_parse_pplib_clock_info()
7246 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; in si_parse_pplib_clock_info()
7247 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; in si_parse_pplib_clock_info()
7258 struct amdgpu_mode_info *mode_info = &adev->mode_info; in si_parse_power_table()
7273 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, in si_parse_power_table()
7275 return -EINVAL; in si_parse_power_table()
7276 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); in si_parse_power_table()
7281 (mode_info->atom_context->bios + data_offset + in si_parse_power_table()
7282 le16_to_cpu(power_info->pplib.usStateArrayOffset)); in si_parse_power_table()
7284 (mode_info->atom_context->bios + data_offset + in si_parse_power_table()
7285 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); in si_parse_power_table()
7287 (mode_info->atom_context->bios + data_offset + in si_parse_power_table()
7288 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); in si_parse_power_table()
7290 adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in si_parse_power_table()
7293 if (!adev->pm.dpm.ps) in si_parse_power_table()
7294 return -ENOMEM; in si_parse_power_table()
7295 power_state_offset = (u8 *)state_array->states; in si_parse_power_table()
7296 for (adev->pm.dpm.num_ps = 0, i = 0; i < state_array->ucNumEntries; i++) { in si_parse_power_table()
7299 non_clock_array_index = power_state->v2.nonClockInfoIndex; in si_parse_power_table()
7301 &non_clock_info_array->nonClockInfo[non_clock_array_index]; in si_parse_power_table()
7304 return -ENOMEM; in si_parse_power_table()
7305 adev->pm.dpm.ps[i].ps_priv = ps; in si_parse_power_table()
7306 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], in si_parse_power_table()
7308 non_clock_info_array->ucEntrySize); in si_parse_power_table()
7310 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; in si_parse_power_table()
7311 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in si_parse_power_table()
7313 if (clock_array_index >= clock_info_array->ucNumEntries) in si_parse_power_table()
7318 ((u8 *)&clock_info_array->clockInfo[0] + in si_parse_power_table()
7319 (clock_array_index * clock_info_array->ucEntrySize)); in si_parse_power_table()
7321 &adev->pm.dpm.ps[i], k, in si_parse_power_table()
7325 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in si_parse_power_table()
7326 adev->pm.dpm.num_ps++; in si_parse_power_table()
7330 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { in si_parse_power_table()
7332 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; in si_parse_power_table()
7334 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; in si_parse_power_table()
7335 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); in si_parse_power_table()
7336 sclk |= clock_info->si.ucEngineClockHigh << 16; in si_parse_power_table()
7337 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); in si_parse_power_table()
7338 mclk |= clock_info->si.ucMemoryClockHigh << 16; in si_parse_power_table()
7339 adev->pm.dpm.vce_states[i].sclk = sclk; in si_parse_power_table()
7340 adev->pm.dpm.vce_states[i].mclk = mclk; in si_parse_power_table()
7357 return -ENOMEM; in si_dpm_init()
7358 adev->pm.dpm.priv = si_pi; in si_dpm_init()
7359 ni_pi = &si_pi->ni; in si_dpm_init()
7360 eg_pi = &ni_pi->eg; in si_dpm_init()
7361 pi = &eg_pi->rv7xx; in si_dpm_init()
7363 si_pi->sys_pcie_mask = in si_dpm_init()
7364 adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK; in si_dpm_init()
7365 si_pi->force_pcie_gen = SI_PCIE_GEN_INVALID; in si_dpm_init()
7366 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev); in si_dpm_init()
7374 pi->acpi_vddc = 0; in si_dpm_init()
7375 eg_pi->acpi_vddci = 0; in si_dpm_init()
7376 pi->min_vddc_in_table = 0; in si_dpm_init()
7377 pi->max_vddc_in_table = 0; in si_dpm_init()
7391 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = in si_dpm_init()
7395 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) in si_dpm_init()
7396 return -ENOMEM; in si_dpm_init()
7398 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; in si_dpm_init()
7399 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; in si_dpm_init()
7400 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; in si_dpm_init()
7401 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; in si_dpm_init()
7402 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; in si_dpm_init()
7403 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; in si_dpm_init()
7404 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; in si_dpm_init()
7405 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; in si_dpm_init()
7406 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; in si_dpm_init()
7408 if (adev->pm.dpm.voltage_response_time == 0) in si_dpm_init()
7409 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; in si_dpm_init()
7410 if (adev->pm.dpm.backbias_response_time == 0) in si_dpm_init()
7411 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; in si_dpm_init()
7416 pi->ref_div = dividers.ref_div + 1; in si_dpm_init()
7418 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; in si_dpm_init()
7420 eg_pi->smu_uvd_hs = false; in si_dpm_init()
7422 pi->mclk_strobe_mode_threshold = 40000; in si_dpm_init()
7424 pi->mclk_stutter_mode_threshold = 0; in si_dpm_init()
7426 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; in si_dpm_init()
7427 pi->mclk_edc_enable_threshold = 40000; in si_dpm_init()
7428 eg_pi->mclk_edc_wr_enable_threshold = 40000; in si_dpm_init()
7430 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; in si_dpm_init()
7432 pi->voltage_control = in si_dpm_init()
7435 if (!pi->voltage_control) { in si_dpm_init()
7436 si_pi->voltage_control_svi2 = in si_dpm_init()
7439 if (si_pi->voltage_control_svi2) in si_dpm_init()
7441 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); in si_dpm_init()
7444 pi->mvdd_control = in si_dpm_init()
7448 eg_pi->vddci_control = in si_dpm_init()
7451 if (!eg_pi->vddci_control) in si_dpm_init()
7452 si_pi->vddci_control_svi2 = in si_dpm_init()
7456 si_pi->vddc_phase_shed_control = in si_dpm_init()
7462 pi->asi = RV770_ASI_DFLT; in si_dpm_init()
7463 pi->pasi = CYPRESS_HASI_DFLT; in si_dpm_init()
7464 pi->vrc = SISLANDS_VRC_DFLT; in si_dpm_init()
7466 pi->gfx_clock_gating = true; in si_dpm_init()
7468 eg_pi->sclk_deep_sleep = true; in si_dpm_init()
7469 si_pi->sclk_deep_sleep_above_low = false; in si_dpm_init()
7471 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE) in si_dpm_init()
7472 pi->thermal_protection = true; in si_dpm_init()
7474 pi->thermal_protection = false; in si_dpm_init()
7476 eg_pi->dynamic_ac_timing = true; in si_dpm_init()
7478 eg_pi->light_sleep = true; in si_dpm_init()
7480 eg_pi->pcie_performance_request = in si_dpm_init()
7483 eg_pi->pcie_performance_request = false; in si_dpm_init()
7486 si_pi->sram_end = SMC_RAM_END; in si_dpm_init()
7488 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in si_dpm_init()
7489 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in si_dpm_init()
7490 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in si_dpm_init()
7491 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0; in si_dpm_init()
7492 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; in si_dpm_init()
7493 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in si_dpm_init()
7494 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; in si_dpm_init()
7499 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in si_dpm_init()
7500 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in si_dpm_init()
7501 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in si_dpm_init()
7502 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in si_dpm_init()
7504 si_pi->fan_ctrl_is_in_default_mode = true; in si_dpm_init()
7513 if (adev->pm.dpm.ps) in si_dpm_fini()
7514 for (i = 0; i < adev->pm.dpm.num_ps; i++) in si_dpm_fini()
7515 kfree(adev->pm.dpm.ps[i].ps_priv); in si_dpm_fini()
7516 kfree(adev->pm.dpm.ps); in si_dpm_fini()
7517 kfree(adev->pm.dpm.priv); in si_dpm_fini()
7518 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); in si_dpm_fini()
7527 struct amdgpu_ps *rps = &eg_pi->current_rps; in si_dpm_debugfs_print_current_performance_level()
7534 if (current_index >= ps->performance_level_count) { in si_dpm_debugfs_print_current_performance_level()
7537 pl = &ps->performance_levels[current_index]; in si_dpm_debugfs_print_current_performance_level()
7538 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in si_dpm_debugfs_print_current_performance_level()
7540 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); in si_dpm_debugfs_print_current_performance_level()
7599 return -EINVAL; in si_dpm_process_interrupt()
7601 switch (entry->src_id) { in si_dpm_process_interrupt()
7602 case 230: /* thermal low to high */ in si_dpm_process_interrupt()
7603 DRM_DEBUG("IH: thermal low to high\n"); in si_dpm_process_interrupt()
7604 adev->pm.dpm.thermal.high_to_low = false; in si_dpm_process_interrupt()
7607 case 231: /* thermal high to low */ in si_dpm_process_interrupt()
7608 DRM_DEBUG("IH: thermal high to low\n"); in si_dpm_process_interrupt()
7609 adev->pm.dpm.thermal.high_to_low = true; in si_dpm_process_interrupt()
7617 schedule_work(&adev->pm.dpm.thermal.work); in si_dpm_process_interrupt()
7627 if (!adev->pm.dpm_enabled) in si_dpm_late_init()
7640 * si_dpm_init_microcode - load ucode images from disk
7654 switch (adev->asic_type) { in si_dpm_init_microcode()
7659 if ((adev->pdev->revision == 0x81) && in si_dpm_init_microcode()
7660 ((adev->pdev->device == 0x6810) || in si_dpm_init_microcode()
7661 (adev->pdev->device == 0x6811))) in si_dpm_init_microcode()
7667 if (((adev->pdev->device == 0x6820) && in si_dpm_init_microcode()
7668 ((adev->pdev->revision == 0x81) || in si_dpm_init_microcode()
7669 (adev->pdev->revision == 0x83))) || in si_dpm_init_microcode()
7670 ((adev->pdev->device == 0x6821) && in si_dpm_init_microcode()
7671 ((adev->pdev->revision == 0x83) || in si_dpm_init_microcode()
7672 (adev->pdev->revision == 0x87))) || in si_dpm_init_microcode()
7673 ((adev->pdev->revision == 0x87) && in si_dpm_init_microcode()
7674 ((adev->pdev->device == 0x6823) || in si_dpm_init_microcode()
7675 (adev->pdev->device == 0x682b)))) in si_dpm_init_microcode()
7681 if (((adev->pdev->revision == 0x81) && in si_dpm_init_microcode()
7682 ((adev->pdev->device == 0x6600) || in si_dpm_init_microcode()
7683 (adev->pdev->device == 0x6604) || in si_dpm_init_microcode()
7684 (adev->pdev->device == 0x6605) || in si_dpm_init_microcode()
7685 (adev->pdev->device == 0x6610))) || in si_dpm_init_microcode()
7686 ((adev->pdev->revision == 0x83) && in si_dpm_init_microcode()
7687 (adev->pdev->device == 0x6610))) in si_dpm_init_microcode()
7693 if (((adev->pdev->revision == 0x81) && in si_dpm_init_microcode()
7694 (adev->pdev->device == 0x6660)) || in si_dpm_init_microcode()
7695 ((adev->pdev->revision == 0x83) && in si_dpm_init_microcode()
7696 ((adev->pdev->device == 0x6660) || in si_dpm_init_microcode()
7697 (adev->pdev->device == 0x6663) || in si_dpm_init_microcode()
7698 (adev->pdev->device == 0x6665) || in si_dpm_init_microcode()
7699 (adev->pdev->device == 0x6667)))) in si_dpm_init_microcode()
7701 else if ((adev->pdev->revision == 0xc3) && in si_dpm_init_microcode()
7702 (adev->pdev->device == 0x6665)) in si_dpm_init_microcode()
7710 err = amdgpu_ucode_request(adev, &adev->pm.fw, "amdgpu/%s_smc.bin", chip_name); in si_dpm_init_microcode()
7714 amdgpu_ucode_release(&adev->pm.fw); in si_dpm_init_microcode()
7724 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq); in si_dpm_sw_init()
7728 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq); in si_dpm_sw_init()
7733 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; in si_dpm_sw_init()
7734 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; in si_dpm_sw_init()
7735 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO; in si_dpm_sw_init()
7736 adev->pm.default_sclk = adev->clock.default_sclk; in si_dpm_sw_init()
7737 adev->pm.default_mclk = adev->clock.default_mclk; in si_dpm_sw_init()
7738 adev->pm.current_sclk = adev->clock.default_sclk; in si_dpm_sw_init()
7739 adev->pm.current_mclk = adev->clock.default_mclk; in si_dpm_sw_init()
7740 adev->pm.int_thermal_type = THERMAL_TYPE_NONE; in si_dpm_sw_init()
7749 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); in si_dpm_sw_init()
7753 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in si_dpm_sw_init()
7770 flush_work(&adev->pm.dpm.thermal.work); in si_dpm_sw_fini()
7789 adev->pm.dpm_enabled = false; in si_dpm_hw_init()
7791 adev->pm.dpm_enabled = true; in si_dpm_hw_init()
7800 if (adev->pm.dpm_enabled) in si_dpm_hw_fini()
7810 if (adev->pm.dpm_enabled) { in si_dpm_suspend()
7814 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in si_dpm_suspend()
7824 if (adev->pm.dpm_enabled) { in si_dpm_resume()
7829 adev->pm.dpm_enabled = false; in si_dpm_resume()
7831 adev->pm.dpm_enabled = true; in si_dpm_resume()
7832 if (adev->pm.dpm_enabled) in si_dpm_resume()
7887 static u32 si_dpm_get_sclk(void *handle, bool low) in si_dpm_get_sclk() argument
7891 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps); in si_dpm_get_sclk()
7893 if (low) in si_dpm_get_sclk()
7894 return requested_state->performance_levels[0].sclk; in si_dpm_get_sclk()
7896 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; in si_dpm_get_sclk()
7899 static u32 si_dpm_get_mclk(void *handle, bool low) in si_dpm_get_mclk() argument
7903 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps); in si_dpm_get_mclk()
7905 if (low) in si_dpm_get_mclk()
7906 return requested_state->performance_levels[0].mclk; in si_dpm_get_mclk()
7908 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; in si_dpm_get_mclk()
7920 amdgpu_dpm_print_class_info(rps->class, rps->class2); in si_dpm_print_power_state()
7921 amdgpu_dpm_print_cap_info(rps->caps); in si_dpm_print_power_state()
7922 DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in si_dpm_print_power_state()
7923 for (i = 0; i < ps->performance_level_count; i++) { in si_dpm_print_power_state()
7924 pl = &ps->performance_levels[i]; in si_dpm_print_power_state()
7926 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); in si_dpm_print_power_state()
7936 adev->powerplay.pp_funcs = &si_dpm_funcs; in si_dpm_early_init()
7937 adev->powerplay.pp_handle = adev; in si_dpm_early_init()
7945 return ((si_cpl1->mclk == si_cpl2->mclk) && in si_are_power_levels_equal()
7946 (si_cpl1->sclk == si_cpl2->sclk) && in si_are_power_levels_equal()
7947 (si_cpl1->pcie_gen == si_cpl2->pcie_gen) && in si_are_power_levels_equal()
7948 (si_cpl1->vddc == si_cpl2->vddc) && in si_are_power_levels_equal()
7949 (si_cpl1->vddci == si_cpl2->vddci)); in si_are_power_levels_equal()
7965 return -EINVAL; in si_check_state_equal()
7976 if (si_cps->performance_level_count != si_rps->performance_level_count) { in si_check_state_equal()
7981 for (i = 0; i < si_cps->performance_level_count; i++) { in si_check_state_equal()
7982 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]), in si_check_state_equal()
7983 &(si_rps->performance_levels[i]))) { in si_check_state_equal()
7990 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk)); in si_check_state_equal()
7991 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk)); in si_check_state_equal()
8001 struct amdgpu_ps *rps = &eg_pi->current_rps; in si_dpm_read_sensor()
8010 return -EINVAL; in si_dpm_read_sensor()
8014 if (pl_index < ps->performance_level_count) { in si_dpm_read_sensor()
8015 sclk = ps->performance_levels[pl_index].sclk; in si_dpm_read_sensor()
8020 return -EINVAL; in si_dpm_read_sensor()
8022 if (pl_index < ps->performance_level_count) { in si_dpm_read_sensor()
8023 mclk = ps->performance_levels[pl_index].mclk; in si_dpm_read_sensor()
8028 return -EINVAL; in si_dpm_read_sensor()
8034 return -EOPNOTSUPP; in si_dpm_read_sensor()
8094 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; in si_dpm_set_irq_funcs()
8095 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs; in si_dpm_set_irq_funcs()