Lines Matching full:enum

50 typedef enum GDS_PERFCOUNT_SELECT {
180  * MEM_PWR_FORCE_CTRL enum
183 typedef enum MEM_PWR_FORCE_CTRL {
191  * MEM_PWR_FORCE_CTRL2 enum
194 typedef enum MEM_PWR_FORCE_CTRL2 {
200  * MEM_PWR_DIS_CTRL enum
203 typedef enum MEM_PWR_DIS_CTRL {
209  * MEM_PWR_SEL_CTRL enum
212 typedef enum MEM_PWR_SEL_CTRL {
219  * MEM_PWR_SEL_CTRL2 enum
222 typedef enum MEM_PWR_SEL_CTRL2 {
228  * RowSize enum
231 typedef enum RowSize {
238  * SurfaceEndian enum
241 typedef enum SurfaceEndian {
249  * ArrayMode enum
252 typedef enum ArrayMode {
272  * NumPipes enum
275 typedef enum NumPipes {
285  * NumBanksConfig enum
288 typedef enum NumBanksConfig {
297  * PipeInterleaveSize enum
300 typedef enum PipeInterleaveSize {
308  * BankInterleaveSize enum
311 typedef enum BankInterleaveSize {
319  * NumShaderEngines enum
322 typedef enum NumShaderEngines {
330  * NumRbPerShaderEngine enum
333 typedef enum NumRbPerShaderEngine {
340  * NumGPUs enum
343 typedef enum NumGPUs {
351  * NumMaxCompressedFragments enum
354 typedef enum NumMaxCompressedFragments {
362  * ShaderEngineTileSize enum
365 typedef enum ShaderEngineTileSize {
371  * MultiGPUTileSize enum
374 typedef enum MultiGPUTileSize {
382  * NumLowerPipes enum
385 typedef enum NumLowerPipes {
391  * ColorTransform enum
394 typedef enum ColorTransform {
402  * CompareRef enum
405 typedef enum CompareRef {
417  * ReadSize enum
420 typedef enum ReadSize {
426  * DepthFormat enum
429 typedef enum DepthFormat {
441  * ZFormat enum
444 typedef enum ZFormat {
452  * StencilFormat enum
455 typedef enum StencilFormat {
461  * CmaskMode enum
464 typedef enum CmaskMode {
484  * QuadExportFormat enum
487 typedef enum QuadExportFormat {
503  * QuadExportFormatOld enum
506 typedef enum QuadExportFormatOld {
516  * ColorFormat enum
519 typedef enum ColorFormat {
555  * SurfaceFormat enum
558 typedef enum SurfaceFormat {
626  * BUF_DATA_FORMAT enum
629 typedef enum BUF_DATA_FORMAT {
649  * IMG_DATA_FORMAT enum
652 typedef enum IMG_DATA_FORMAT {
720  * BUF_NUM_FORMAT enum
723 typedef enum BUF_NUM_FORMAT {
735  * IMG_NUM_FORMAT enum
738 typedef enum IMG_NUM_FORMAT {
758  * IMG_NUM_FORMAT_FMASK enum
761 typedef enum IMG_NUM_FORMAT_FMASK {
781  * IMG_NUM_FORMAT_N_IN_16 enum
784 typedef enum IMG_NUM_FORMAT_N_IN_16 {
804  * IMG_NUM_FORMAT_ASTC_2D enum
807 typedef enum IMG_NUM_FORMAT_ASTC_2D {
827  * IMG_NUM_FORMAT_ASTC_3D enum
830 typedef enum IMG_NUM_FORMAT_ASTC_3D {
850  * TileType enum
853 typedef enum TileType {
859  * NonDispTilingOrder enum
862 typedef enum NonDispTilingOrder {
868  * MicroTileMode enum
871 typedef enum MicroTileMode {
880  * TileSplit enum
883 typedef enum TileSplit {
894  * SampleSplit enum
897 typedef enum SampleSplit {
905  * PipeConfig enum
908 typedef enum PipeConfig {
930  * SeEnable enum
933 typedef enum SeEnable {
939  * NumBanks enum
942 typedef enum NumBanks {
950  * BankWidth enum
953 typedef enum BankWidth {
961  * BankHeight enum
964 typedef enum BankHeight {
972  * BankWidthHeight enum
975 typedef enum BankWidthHeight {
983  * MacroTileAspect enum
986 typedef enum MacroTileAspect {
994  * GATCL1RequestType enum
997 typedef enum GATCL1RequestType {
1004  * UTCL1RequestType enum
1007 typedef enum UTCL1RequestType {
1014  * UTCL1FaultType enum
1017 typedef enum UTCL1FaultType {
1025  * TCC_CACHE_POLICIES enum
1028 typedef enum TCC_CACHE_POLICIES {
1034  * MTYPE enum
1037 typedef enum MTYPE {
1046  * RMI_CID enum
1049 typedef enum RMI_CID {
1061  * PERFMON_COUNTER_MODE enum
1064 typedef enum PERFMON_COUNTER_MODE {
1079  * PERFMON_SPM_MODE enum
1082 typedef enum PERFMON_SPM_MODE {
1097  * SurfaceTiling enum
1100 typedef enum SurfaceTiling {
1106  * SurfaceArray enum
1109 typedef enum SurfaceArray {
1117  * ColorArray enum
1120 typedef enum ColorArray {
1127  * DepthArray enum
1130 typedef enum DepthArray {
1136  * ENUM_NUM_SIMD_PER_CU enum
1139 typedef enum ENUM_NUM_SIMD_PER_CU {
1144  * DSM_ENABLE_ERROR_INJECT enum
1147 typedef enum DSM_ENABLE_ERROR_INJECT {
1155  * DSM_SELECT_INJECT_DELAY enum
1158 typedef enum DSM_SELECT_INJECT_DELAY {
1164  * SWIZZLE_TYPE_ENUM enum
1167 typedef enum SWIZZLE_TYPE_ENUM {
1176  * TC_MICRO_TILE_MODE enum
1179 typedef enum TC_MICRO_TILE_MODE {
1191  * SWIZZLE_MODE_ENUM enum
1194 typedef enum SWIZZLE_MODE_ENUM {
1234  * PipeTiling enum
1237 typedef enum PipeTiling {
1245  * BankTiling enum
1248 typedef enum BankTiling {
1254  * GroupInterleave enum
1257 typedef enum GroupInterleave {
1263  * RowTiling enum
1266 typedef enum RowTiling {
1278  * BankSwapBytes enum
1281 typedef enum BankSwapBytes {
1289  * SampleSplitBytes enum
1292 typedef enum SampleSplitBytes {
1304  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum
1307 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
1313  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum
1316 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
1322  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum
1325 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
1331  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum
1334 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
1340  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum
1343 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
1349  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum
1352 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
1358  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum
1361 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
1367  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum
1370 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
1376  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum
1379 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
1385  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum
1388 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
1394  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum
1397 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
1406  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum
1409 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
1421  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum
1424 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
1434  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum
1437 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
1461  * BLNDV_CONTROL_BLND_MODE enum
1464 typedef enum BLNDV_CONTROL_BLND_MODE {
1472  * BLNDV_CONTROL_BLND_STEREO_TYPE enum
1475 typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE {
1483  * BLNDV_CONTROL_BLND_STEREO_POLARITY enum
1486 typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY {
1492  * BLNDV_CONTROL_BLND_FEEDTHROUGH_EN enum
1495 typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN {
1501  * BLNDV_CONTROL_BLND_ALPHA_MODE enum
1504 typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE {
1512  * BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY enum
1515 typedef enum BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
1521  * BLNDV_CONTROL_BLND_MULTIPLIED_MODE enum
1524 typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE {
1530  * BLNDV_SM_CONTROL2_SM_MODE enum
1533 typedef enum BLNDV_SM_CONTROL2_SM_MODE {
1541  * BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE enum
1544 typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE {
1550  * BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE enum
1553 typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE {
1559  * BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL enum
1562 typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
1570  * BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL enum
1573 typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
1581  * BLNDV_CONTROL2_PTI_ENABLE enum
1584 typedef enum BLNDV_CONTROL2_PTI_ENABLE {
1590  * BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN enum
1593 typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
1599  * BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN enum
1602 typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
1608  * BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK enum
1611 typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
1617  * BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK enum
1620 typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
1626  * BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK enum
1629 typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
1635  * BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK enum
1638 typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
1644  * BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK enum
1647 typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
1653  * BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK enum
1656 typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
1662  * BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK enum
1665 typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
1671  * BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK enum
1674 typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
1680  * BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE enum
1683 typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
1689  * BLNDV_DEBUG_BLND_CNV_MUX_SELECT enum
1692 typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT {
1698  * BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN enum
1701 typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
1711  * LBV_PIXEL_DEPTH enum
1714 typedef enum LBV_PIXEL_DEPTH {
1722  * LBV_PIXEL_EXPAN_MODE enum
1725 typedef enum LBV_PIXEL_EXPAN_MODE {
1731  * LBV_INTERLEAVE_EN enum
1734 typedef enum LBV_INTERLEAVE_EN {
1740  * LBV_PIXEL_REDUCE_MODE enum
1743 typedef enum LBV_PIXEL_REDUCE_MODE {
1749  * LBV_DYNAMIC_PIXEL_DEPTH enum
1752 typedef enum LBV_DYNAMIC_PIXEL_DEPTH {
1758  * LBV_DITHER_EN enum
1761 typedef enum LBV_DITHER_EN {
1767  * LBV_DOWNSCALE_PREFETCH_EN enum
1770 typedef enum LBV_DOWNSCALE_PREFETCH_EN {
1776  * LBV_MEMORY_CONFIG enum
1779 typedef enum LBV_MEMORY_CONFIG {
1787  * LBV_SYNC_RESET_SEL2 enum
1790 typedef enum LBV_SYNC_RESET_SEL2 {
1796  * LBV_SYNC_DURATION enum
1799 typedef enum LBV_SYNC_DURATION {
1811  * CRTC_CONTROL_CRTC_START_POINT_CNTL enum
1814 typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL {
1820  * CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL enum
1823 typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL {
1829  * CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL enum
1832 typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL {
1840  * CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY enum
1843 typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY {
1849  * CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE enum
1852 typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE {
1858  * CRTC_CONTROL_CRTC_SOF_PULL_EN enum
1861 typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN {
1867  * CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL enum
1870 typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL {
1876  * CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL enum
1879 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL {
1885  * CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL enum
1888 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL {
1894  * CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN enum
1897 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN {
1903  * CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC enum
1906 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC {
1912  * CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT enum
1915 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT {
1921  * CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK enum
1924 typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
1930  * CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR enum
1933 typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR {
1939  * CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL enum
1942 typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL {
1948  * CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN enum
1951 typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN {
1957  * CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT enum
1960 typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT {
1984  * CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT enum
1987 typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT {
1998  * CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN enum
2001 typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN {
2007  * CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR enum
2010 typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR {
2016  * CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT enum
2019 typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT {
2043  * CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT enum
2046 typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT {
2057  * CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN enum
2060 typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN {
2066  * CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR enum
2069 typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR {
2075  * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE enum
2078 typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE {
2086  * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK enum
2089 typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK {
2095  * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL enum
2098 typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL {
2104  * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR enum
2107 typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR {
2113  * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT enum
2116 typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT {
2136  * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY enum
2139 typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY {
2145  * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY enum
2148 typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY {
2154  * CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE enum
2157 typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE {
2165  * CRTC_CONTROL_CRTC_MASTER_EN enum
2168 typedef enum CRTC_CONTROL_CRTC_MASTER_EN {
2174  * CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN enum
2177 typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN {
2183  * CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE enum
2186 typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE {
2192  * CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE enum
2195 typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE {
2201  * CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD enum
2204 typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD {
2212  * CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY enum
2215 typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY {
2221  * CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT enum
2224 typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT {
2230  * CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN enum
2233 typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN {
2239  * CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE enum
2242 typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE {
2248  * CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR enum
2251 typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR {
2257  * CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE enum
2260 typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE {
2268  * CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY enum
2271 typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY {
2277  * CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY enum
2280 typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY {
2286  * CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY enum
2289 typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY {
2295  * CRTC_STEREO_CONTROL_CRTC_STEREO_EN enum
2298 typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN {
2304  * CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR enum
2307 typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR {
2313  * CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL enum
2316 typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL {
2324  * CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY enum
2327 typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY {
2333  * CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY enum
2336 typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY {
2342  * CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN enum
2345 typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN {
2351  * CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN enum
2354 typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN {
2360  * CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK enum
2363 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK {
2369  * CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE enum
2372 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE {
2378  * CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK enum
2381 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK {
2387  * CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE enum
2390 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE {
2396  * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK enum
2399 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK {
2405  * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE enum
2408 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE {
2414  * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK enum
2417 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK {
2423  * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum
2426 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
2432  * CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK enum
2435 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK {
2441  * CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE enum
2444 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE {
2450  * CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK enum
2453 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK {
2459  * CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE enum
2462 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE {
2468  * CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK enum
2471 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK {
2477  * CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE enum
2480 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE {
2486  * CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK enum
2489 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK {
2495  * CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE enum
2498 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE {
2504  * CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK enum
2507 typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK {
2513  * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY enum
2516 typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY {
2522  * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN enum
2525 typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN {
2531  * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE enum
2534 typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE {
2540  * CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE enum
2543 typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE {
2549  * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN enum
2552 typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN {
2558  * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE enum
2561 typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE {
2573  * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE enum
2576 typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE {
2582  * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT enum
2585 typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT {
2593  * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum
2596 typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
2602  * MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK enum
2605 typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK {
2611  * MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK enum
2614 typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
2620  * MASTER_UPDATE_MODE_MASTER_UPDATE_MODE enum
2623 typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE {
2631  * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum
2634 typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
2642  * CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE enum
2645 typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE {
2652  * CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR enum
2655 typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR {
2661  * CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR enum
2664 typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {
2670  * CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR enum
2673 typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR {
2679  * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum
2682 typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
2688  * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE enum
2691 typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE {
2697  * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR enum
2700 typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR {
2706  * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE enum
2709 typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE {
2715  * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR enum
2718 typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR {
2724  * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE enum
2727 typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE {
2733  * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE enum
2736 typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE {
2742  * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR enum
2745 typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR {
2751  * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE enum
2754 typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE {
2760  * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE enum
2763 typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE {
2769  * CRTC_CRC_CNTL_CRTC_CRC_EN enum
2772 typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN {
2778  * CRTC_CRC_CNTL_CRTC_CRC_CONT_EN enum
2781 typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN {
2787  * CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE enum
2790 typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE {
2798  * CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE enum
2801 typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE {
2809  * CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS enum
2812 typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS {
2818  * CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT enum
2821 typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT {
2833  * CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT enum
2836 typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT {
2848  * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE enum
2851 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE {
2859  * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE enum
2862 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE {
2868  * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE enum
2871 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE {
2877  * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW enum
2880 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW {
2888  * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE enum
2891 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE {
2897  * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE enum
2900 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE {
2906  * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY enum
2909 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY {
2915  * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY enum
2918 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY {
2924  * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE enum
2927 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE {
2933  * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE enum
2936 typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE {
2942  * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR enum
2945 typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR {
2951  * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE enum
2954 typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE {
2960  * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT enum
2963 typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT {
2975  * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE enum
2978 typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE {
2984  * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR enum
2987 typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR {
2993  * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE enum
2996 typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE {
3002  * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE enum
3005 typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE {
3011  * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR enum
3014 typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR {
3020  * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE enum
3023 typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE {
3029  * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE enum
3032 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE {
3038  * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR enum
3041 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR {
3047  * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE enum
3050 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE {
3056  * CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE enum
3059 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE {
3065  * CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE enum
3068 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE {
3074  * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN enum
3077 typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN {
3083  * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB enum
3086 typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB {
3092  * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE enum
3095 typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE {
3103  * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR enum
3106 typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR {
3112  * CRTC_V_SYNC_A_POL enum
3115 typedef enum CRTC_V_SYNC_A_POL {
3121  * CRTC_H_SYNC_A_POL enum
3124 typedef enum CRTC_H_SYNC_A_POL {
3130  * CRTC_HORZ_REPETITION_COUNT enum
3133 typedef enum CRTC_HORZ_REPETITION_COUNT {
3153  * CRTC_DRR_MODE_DBUF_UPDATE_MODE enum
3156 typedef enum CRTC_DRR_MODE_DBUF_UPDATE_MODE {
3168  * FMT_CONTROL_PIXEL_ENCODING enum
3171 typedef enum FMT_CONTROL_PIXEL_ENCODING {
3179  * FMT_CONTROL_SUBSAMPLING_MODE enum
3182 typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
3190  * FMT_CONTROL_SUBSAMPLING_ORDER enum
3193 typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
3199  * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum
3202 typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
3208  * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum
3211 typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
3217  * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum
3220 typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
3227  * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum
3230 typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
3237  * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum
3240 typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
3247  * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum
3250 typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
3256  * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum
3259 typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
3267  * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum
3270 typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
3278  * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum
3281 typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
3289  * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT enum
3292 typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT {
3298  * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum
3301 typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
3307  * FMT_CLAMP_CNTL_COLOR_FORMAT enum
3310 typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
3322  * FMT_CRC_CNTL_CONT_EN enum
3325 typedef enum FMT_CRC_CNTL_CONT_EN {
3331  * FMT_CRC_CNTL_INCLUDE_OVERSCAN enum
3334 typedef enum FMT_CRC_CNTL_INCLUDE_OVERSCAN {
3340  * FMT_CRC_CNTL_ONLY_BLANKB enum
3343 typedef enum FMT_CRC_CNTL_ONLY_BLANKB {
3349  * FMT_CRC_CNTL_PSR_MODE_ENABLE enum
3352 typedef enum FMT_CRC_CNTL_PSR_MODE_ENABLE {
3358  * FMT_CRC_CNTL_INTERLACE_MODE enum
3361 typedef enum FMT_CRC_CNTL_INTERLACE_MODE {
3369  * FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE enum
3372 typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE {
3378  * FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT enum
3381 typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT {
3387  * FMT_DEBUG_CNTL_COLOR_SELECT enum
3390 typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
3398  * FMT_SPATIAL_DITHER_MODE enum
3401 typedef enum FMT_SPATIAL_DITHER_MODE {
3409  * FMT_STEREOSYNC_OVR_POL enum
3412 typedef enum FMT_STEREOSYNC_OVR_POL {
3418  * FMT_DYNAMIC_EXP_MODE enum
3421 typedef enum FMT_DYNAMIC_EXP_MODE {
3431  * HPD_INT_CONTROL_ACK enum
3434 typedef enum HPD_INT_CONTROL_ACK {
3440  * HPD_INT_CONTROL_POLARITY enum
3443 typedef enum HPD_INT_CONTROL_POLARITY {
3449  * HPD_INT_CONTROL_RX_INT_ACK enum
3452 typedef enum HPD_INT_CONTROL_RX_INT_ACK {
3462  * LB_DATA_FORMAT_PIXEL_DEPTH enum
3465 typedef enum LB_DATA_FORMAT_PIXEL_DEPTH {
3473  * LB_DATA_FORMAT_PIXEL_EXPAN_MODE enum
3476 typedef enum LB_DATA_FORMAT_PIXEL_EXPAN_MODE {
3482  * LB_DATA_FORMAT_PIXEL_REDUCE_MODE enum
3485 typedef enum LB_DATA_FORMAT_PIXEL_REDUCE_MODE {
3491  * LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH enum
3494 typedef enum LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH {
3500  * LB_DATA_FORMAT_INTERLEAVE_EN enum
3503 typedef enum LB_DATA_FORMAT_INTERLEAVE_EN {
3509  * LB_DATA_FORMAT_REQUEST_MODE enum
3512 typedef enum LB_DATA_FORMAT_REQUEST_MODE {
3518  * LB_DATA_FORMAT_ALPHA_EN enum
3521 typedef enum LB_DATA_FORMAT_ALPHA_EN {
3527  * LB_VLINE_START_END_VLINE_INV enum
3530 typedef enum LB_VLINE_START_END_VLINE_INV {
3536  * LB_VLINE2_START_END_VLINE2_INV enum
3539 typedef enum LB_VLINE2_START_END_VLINE2_INV {
3545  * LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK enum
3548 typedef enum LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK {
3554  * LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK enum
3557 typedef enum LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK {
3563  * LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK enum
3566 typedef enum LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK {
3572  * LB_VLINE_STATUS_VLINE_ACK enum
3575 typedef enum LB_VLINE_STATUS_VLINE_ACK {
3581  * LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE enum
3584 typedef enum LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE {
3590  * LB_VLINE2_STATUS_VLINE2_ACK enum
3593 typedef enum LB_VLINE2_STATUS_VLINE2_ACK {
3599  * LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE enum
3602 typedef enum LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE {
3608  * LB_VBLANK_STATUS_VBLANK_ACK enum
3611 typedef enum LB_VBLANK_STATUS_VBLANK_ACK {
3617  * LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE enum
3620 typedef enum LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE {
3626  * LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL enum
3629 typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL {
3637  * LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 enum
3640 typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 {
3646  * LB_SYNC_RESET_SEL_LB_SYNC_DURATION enum
3649 typedef enum LB_SYNC_RESET_SEL_LB_SYNC_DURATION {
3657  * LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN enum
3660 typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN {
3666  * LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN enum
3669 typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN {
3675  * LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK enum
3678 typedef enum LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK {
3684  * LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK enum
3687 typedef enum LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK {
3693  * LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE enum
3696 typedef enum LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE {
3702  * LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET enum
3705 typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET {
3711  * LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK enum
3714 typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK {
3720  * LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE enum
3723 typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE {
3730  * LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE enum
3733 typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE {
3739  * LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE enum
3742 typedef enum LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE {
3748  * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL enum
3751 typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL {
3757  * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE enum
3760 typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE {
3766  * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO enum
3769 typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO {
3775  * LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN enum
3778 typedef enum LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN {
3788  * HDMI_KEEPOUT_MODE enum
3791 typedef enum HDMI_KEEPOUT_MODE {
3797  * HDMI_DATA_SCRAMBLE_EN enum
3800 typedef enum HDMI_DATA_SCRAMBLE_EN {
3806  * HDMI_CLOCK_CHANNEL_RATE enum
3809 typedef enum HDMI_CLOCK_CHANNEL_RATE {
3815  * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum
3818 typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
3824  * HDMI_PACKET_GEN_VERSION enum
3827 typedef enum HDMI_PACKET_GEN_VERSION {
3833  * HDMI_ERROR_ACK enum
3836 typedef enum HDMI_ERROR_ACK {
3842  * HDMI_ERROR_MASK enum
3845 typedef enum HDMI_ERROR_MASK {
3851  * HDMI_DEEP_COLOR_DEPTH enum
3854 typedef enum HDMI_DEEP_COLOR_DEPTH {
3862  * HDMI_AUDIO_DELAY_EN enum
3865 typedef enum HDMI_AUDIO_DELAY_EN {
3873  * HDMI_AUDIO_SEND_MAX_PACKETS enum
3876 typedef enum HDMI_AUDIO_SEND_MAX_PACKETS {
3882  * HDMI_ACR_SEND enum
3885 typedef enum HDMI_ACR_SEND {
3891  * HDMI_ACR_CONT enum
3894 typedef enum HDMI_ACR_CONT {
3900  * HDMI_ACR_SELECT enum
3903 typedef enum HDMI_ACR_SELECT {
3911  * HDMI_ACR_SOURCE enum
3914 typedef enum HDMI_ACR_SOURCE {
3920  * HDMI_ACR_N_MULTIPLE enum
3923 typedef enum HDMI_ACR_N_MULTIPLE {
3935  * HDMI_ACR_AUDIO_PRIORITY enum
3938 typedef enum HDMI_ACR_AUDIO_PRIORITY {
3944  * HDMI_NULL_SEND enum
3947 typedef enum HDMI_NULL_SEND {
3953  * HDMI_GC_SEND enum
3956 typedef enum HDMI_GC_SEND {
3962  * HDMI_GC_CONT enum
3965 typedef enum HDMI_GC_CONT {
3971  * HDMI_ISRC_SEND enum
3974 typedef enum HDMI_ISRC_SEND {
3980  * HDMI_ISRC_CONT enum
3983 typedef enum HDMI_ISRC_CONT {
3989  * HDMI_AVI_INFO_SEND enum
3992 typedef enum HDMI_AVI_INFO_SEND {
3998  * HDMI_AVI_INFO_CONT enum
4001 typedef enum HDMI_AVI_INFO_CONT {
4007  * HDMI_AUDIO_INFO_SEND enum
4010 typedef enum HDMI_AUDIO_INFO_SEND {
4016  * HDMI_AUDIO_INFO_CONT enum
4019 typedef enum HDMI_AUDIO_INFO_CONT {
4025  * HDMI_MPEG_INFO_SEND enum
4028 typedef enum HDMI_MPEG_INFO_SEND {
4034  * HDMI_MPEG_INFO_CONT enum
4037 typedef enum HDMI_MPEG_INFO_CONT {
4043  * HDMI_GENERIC0_SEND enum
4046 typedef enum HDMI_GENERIC0_SEND {
4052  * HDMI_GENERIC0_CONT enum
4055 typedef enum HDMI_GENERIC0_CONT {
4061  * HDMI_GENERIC1_SEND enum
4064 typedef enum HDMI_GENERIC1_SEND {
4070  * HDMI_GENERIC1_CONT enum
4073 typedef enum HDMI_GENERIC1_CONT {
4079  * HDMI_GC_AVMUTE_CONT enum
4082 typedef enum HDMI_GC_AVMUTE_CONT {
4088  * HDMI_PACKING_PHASE_OVERRIDE enum
4091 typedef enum HDMI_PACKING_PHASE_OVERRIDE {
4097  * HDMI_GENERIC2_SEND enum
4100 typedef enum HDMI_GENERIC2_SEND {
4106  * HDMI_GENERIC2_CONT enum
4109 typedef enum HDMI_GENERIC2_CONT {
4115  * HDMI_GENERIC3_SEND enum
4118 typedef enum HDMI_GENERIC3_SEND {
4124  * HDMI_GENERIC3_CONT enum
4127 typedef enum HDMI_GENERIC3_CONT {
4133  * TMDS_PIXEL_ENCODING enum
4136 typedef enum TMDS_PIXEL_ENCODING {
4142  * TMDS_COLOR_FORMAT enum
4145 typedef enum TMDS_COLOR_FORMAT {
4153  * TMDS_STEREOSYNC_CTL_SEL_REG enum
4156 typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
4164  * TMDS_CTL0_DATA_SEL enum
4167 typedef enum TMDS_CTL0_DATA_SEL {
4179  * TMDS_CTL0_DATA_INVERT enum
4182 typedef enum TMDS_CTL0_DATA_INVERT {
4188  * TMDS_CTL0_DATA_MODULATION enum
4191 typedef enum TMDS_CTL0_DATA_MODULATION {
4199  * TMDS_CTL0_PATTERN_OUT_EN enum
4202 typedef enum TMDS_CTL0_PATTERN_OUT_EN {
4208  * TMDS_CTL1_DATA_SEL enum
4211 typedef enum TMDS_CTL1_DATA_SEL {
4223  * TMDS_CTL1_DATA_INVERT enum
4226 typedef enum TMDS_CTL1_DATA_INVERT {
4232  * TMDS_CTL1_DATA_MODULATION enum
4235 typedef enum TMDS_CTL1_DATA_MODULATION {
4243  * TMDS_CTL1_PATTERN_OUT_EN enum
4246 typedef enum TMDS_CTL1_PATTERN_OUT_EN {
4252  * TMDS_CTL2_DATA_SEL enum
4255 typedef enum TMDS_CTL2_DATA_SEL {
4267  * TMDS_CTL2_DATA_INVERT enum
4270 typedef enum TMDS_CTL2_DATA_INVERT {
4276  * TMDS_CTL2_DATA_MODULATION enum
4279 typedef enum TMDS_CTL2_DATA_MODULATION {
4287  * TMDS_CTL2_PATTERN_OUT_EN enum
4290 typedef enum TMDS_CTL2_PATTERN_OUT_EN {
4296  * TMDS_CTL3_DATA_INVERT enum
4299 typedef enum TMDS_CTL3_DATA_INVERT {
4305  * TMDS_CTL3_DATA_MODULATION enum
4308 typedef enum TMDS_CTL3_DATA_MODULATION {
4316  * TMDS_CTL3_PATTERN_OUT_EN enum
4319 typedef enum TMDS_CTL3_PATTERN_OUT_EN {
4325  * TMDS_CTL3_DATA_SEL enum
4328 typedef enum TMDS_CTL3_DATA_SEL {
4340  * DIG_FE_CNTL_SOURCE_SELECT enum
4343 typedef enum DIG_FE_CNTL_SOURCE_SELECT {
4353  * DIG_FE_CNTL_STEREOSYNC_SELECT enum
4356 typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
4366  * DIG_FIFO_READ_CLOCK_SRC enum
4369 typedef enum DIG_FIFO_READ_CLOCK_SRC {
4375  * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum
4378 typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
4384  * DIG_OUTPUT_CRC_DATA_SEL enum
4387 typedef enum DIG_OUTPUT_CRC_DATA_SEL {
4395  * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum
4398 typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
4404  * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum
4407 typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
4413  * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum
4416 typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
4422  * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum
4425 typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
4431  * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum
4434 typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
4440  * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum
4443 typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
4449  * DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL enum
4452 typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL {
4458  * DIG_FIFO_ERROR_ACK enum
4461 typedef enum DIG_FIFO_ERROR_ACK {
4467  * DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE enum
4470 typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE {
4476  * DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX enum
4479 typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX {
4485  * AFMT_INTERRUPT_STATUS_CHG_MASK enum
4488 typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
4494  * HDMI_GC_AVMUTE enum
4497 typedef enum HDMI_GC_AVMUTE {
4503  * HDMI_DEFAULT_PAHSE enum
4506 typedef enum HDMI_DEFAULT_PAHSE {
4512  * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum
4515 typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
4521  * AUDIO_LAYOUT_SELECT enum
4524 typedef enum AUDIO_LAYOUT_SELECT {
4530  * AFMT_AUDIO_CRC_CONTROL_CONT enum
4533 typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
4539  * AFMT_AUDIO_CRC_CONTROL_SOURCE enum
4542 typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
4548  * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum
4551 typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
4571  * AFMT_RAMP_CONTROL0_SIGN enum
4574 typedef enum AFMT_RAMP_CONTROL0_SIGN {
4580  * AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum
4583 typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
4589  * AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum
4592 typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
4598  * AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum
4601 typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
4607  * AFMT_AUDIO_SRC_CONTROL_SELECT enum
4610 typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
4621  * DIG_BE_CNTL_MODE enum
4624 typedef enum DIG_BE_CNTL_MODE {
4636  * DIG_BE_CNTL_HPD_SELECT enum
4639 typedef enum DIG_BE_CNTL_HPD_SELECT {
4649  * LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum
4652 typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
4658  * TMDS_SYNC_PHASE enum
4661 typedef enum TMDS_SYNC_PHASE {
4667  * TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum
4670 typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
4676  * TMDS_TRANSMITTER_ENABLE_HPD_MASK enum
4679 typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
4685  * TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum
4688 typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
4694  * TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum
4697 typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
4703  * TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum
4706 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
4714  * TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum
4717 typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
4723  * TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum
4726 typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
4732  * TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum
4735 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
4741  * TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum
4744 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
4750  * TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum
4753 typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
4759  * TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum
4762 typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
4768  * TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum
4771 typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
4777  * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum
4780 typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
4786  * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum
4789 typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
4795  * TMDS_REG_TEST_OUTPUTA_CNTLA enum
4798 typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
4806  * TMDS_REG_TEST_OUTPUTB_CNTLB enum
4809 typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
4821  * DCP_GRPH_ENABLE enum
4824 typedef enum DCP_GRPH_ENABLE {
4830  * DCP_GRPH_KEYER_ALPHA_SEL enum
4833 typedef enum DCP_GRPH_KEYER_ALPHA_SEL {
4839  * DCP_GRPH_DEPTH enum
4842 typedef enum DCP_GRPH_DEPTH {
4850  * DCP_GRPH_NUM_BANKS enum
4853 typedef enum DCP_GRPH_NUM_BANKS {
4862  * DCP_GRPH_NUM_PIPES enum
4865 typedef enum DCP_GRPH_NUM_PIPES {
4873  * DCP_GRPH_FORMAT enum
4876 typedef enum DCP_GRPH_FORMAT {
4884  * DCP_GRPH_ADDRESS_TRANSLATION_ENABLE enum
4887 typedef enum DCP_GRPH_ADDRESS_TRANSLATION_ENABLE {
4893  * DCP_GRPH_SW_MODE enum
4896 typedef enum DCP_GRPH_SW_MODE {
4909  * DCP_GRPH_COLOR_EXPANSION_MODE enum
4912 typedef enum DCP_GRPH_COLOR_EXPANSION_MODE {
4918  * DCP_GRPH_LUT_10BIT_BYPASS_EN enum
4921 typedef enum DCP_GRPH_LUT_10BIT_BYPASS_EN {
4927  * DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN enum
4930 typedef enum DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN {
4936  * DCP_GRPH_ENDIAN_SWAP enum
4939 typedef enum DCP_GRPH_ENDIAN_SWAP {
4947  * DCP_GRPH_RED_CROSSBAR enum
4950 typedef enum DCP_GRPH_RED_CROSSBAR {
4958  * DCP_GRPH_GREEN_CROSSBAR enum
4961 typedef enum DCP_GRPH_GREEN_CROSSBAR {
4969  * DCP_GRPH_BLUE_CROSSBAR enum
4972 typedef enum DCP_GRPH_BLUE_CROSSBAR {
4980  * DCP_GRPH_ALPHA_CROSSBAR enum
4983 typedef enum DCP_GRPH_ALPHA_CROSSBAR {
4991  * DCP_GRPH_PRIMARY_DFQ_ENABLE enum
4994 typedef enum DCP_GRPH_PRIMARY_DFQ_ENABLE {
5000  * DCP_GRPH_SECONDARY_DFQ_ENABLE enum
5003 typedef enum DCP_GRPH_SECONDARY_DFQ_ENABLE {
5009  * DCP_GRPH_INPUT_GAMMA_MODE enum
5012 typedef enum DCP_GRPH_INPUT_GAMMA_MODE {
5018  * DCP_GRPH_MODE_UPDATE_PENDING enum
5021 typedef enum DCP_GRPH_MODE_UPDATE_PENDING {
5027  * DCP_GRPH_MODE_UPDATE_TAKEN enum
5030 typedef enum DCP_GRPH_MODE_UPDATE_TAKEN {
5036  * DCP_GRPH_SURFACE_UPDATE_PENDING enum
5039 typedef enum DCP_GRPH_SURFACE_UPDATE_PENDING {
5045  * DCP_GRPH_SURFACE_UPDATE_TAKEN enum
5048 typedef enum DCP_GRPH_SURFACE_UPDATE_TAKEN {
5054  * DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE enum
5057 typedef enum DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE {
5063  * DCP_GRPH_UPDATE_LOCK enum
5066 typedef enum DCP_GRPH_UPDATE_LOCK {
5072  * DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK enum
5075 typedef enum DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
5081  * DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE enum
5084 typedef enum DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
5090  * DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE enum
5093 typedef enum DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
5099  * DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN enum
5102 typedef enum DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN {
5108  * DCP_GRPH_XDMA_SUPER_AA_EN enum
5111 typedef enum DCP_GRPH_XDMA_SUPER_AA_EN {
5117  * DCP_GRPH_DFQ_RESET enum
5120 typedef enum DCP_GRPH_DFQ_RESET {
5126  * DCP_GRPH_DFQ_SIZE enum
5129 typedef enum DCP_GRPH_DFQ_SIZE {
5141  * DCP_GRPH_DFQ_MIN_FREE_ENTRIES enum
5144 typedef enum DCP_GRPH_DFQ_MIN_FREE_ENTRIES {
5156  * DCP_GRPH_DFQ_RESET_ACK enum
5159 typedef enum DCP_GRPH_DFQ_RESET_ACK {
5165  * DCP_GRPH_PFLIP_INT_CLEAR enum
5168 typedef enum DCP_GRPH_PFLIP_INT_CLEAR {
5174  * DCP_GRPH_PFLIP_INT_MASK enum
5177 typedef enum DCP_GRPH_PFLIP_INT_MASK {
5183  * DCP_GRPH_PFLIP_INT_TYPE enum
5186 typedef enum DCP_GRPH_PFLIP_INT_TYPE {
5192  * DCP_GRPH_PRESCALE_SELECT enum
5195 typedef enum DCP_GRPH_PRESCALE_SELECT {
5201  * DCP_GRPH_PRESCALE_R_SIGN enum
5204 typedef enum DCP_GRPH_PRESCALE_R_SIGN {
5210  * DCP_GRPH_PRESCALE_G_SIGN enum
5213 typedef enum DCP_GRPH_PRESCALE_G_SIGN {
5219  * DCP_GRPH_PRESCALE_B_SIGN enum
5222 typedef enum DCP_GRPH_PRESCALE_B_SIGN {
5228  * DCP_GRPH_PRESCALE_BYPASS enum
5231 typedef enum DCP_GRPH_PRESCALE_BYPASS {
5237  * DCP_INPUT_CSC_GRPH_MODE enum
5240 typedef enum DCP_INPUT_CSC_GRPH_MODE {
5248  * DCP_OUTPUT_CSC_GRPH_MODE enum
5251 typedef enum DCP_OUTPUT_CSC_GRPH_MODE {
5263  * DCP_DENORM_MODE enum
5266 typedef enum DCP_DENORM_MODE {
5278  * DCP_DENORM_14BIT_OUT enum
5281 typedef enum DCP_DENORM_14BIT_OUT {
5287  * DCP_OUT_ROUND_TRUNC_MODE enum
5290 typedef enum DCP_OUT_ROUND_TRUNC_MODE {
5310  * DCP_KEY_MODE enum
5313 typedef enum DCP_KEY_MODE {
5321  * DCP_GRPH_DEGAMMA_MODE enum
5324 typedef enum DCP_GRPH_DEGAMMA_MODE {
5332  * DCP_CURSOR_DEGAMMA_MODE enum
5335 typedef enum DCP_CURSOR_DEGAMMA_MODE {
5343  * DCP_GRPH_GAMUT_REMAP_MODE enum
5346 typedef enum DCP_GRPH_GAMUT_REMAP_MODE {
5354  * DCP_SPATIAL_DITHER_EN enum
5357 typedef enum DCP_SPATIAL_DITHER_EN {
5363  * DCP_SPATIAL_DITHER_MODE enum
5366 typedef enum DCP_SPATIAL_DITHER_MODE {
5374  * DCP_SPATIAL_DITHER_DEPTH enum
5377 typedef enum DCP_SPATIAL_DITHER_DEPTH {
5385  * DCP_FRAME_RANDOM_ENABLE enum
5388 typedef enum DCP_FRAME_RANDOM_ENABLE {
5394  * DCP_RGB_RANDOM_ENABLE enum
5397 typedef enum DCP_RGB_RANDOM_ENABLE {
5403  * DCP_HIGHPASS_RANDOM_ENABLE enum
5406 typedef enum DCP_HIGHPASS_RANDOM_ENABLE {
5412  * DCP_CURSOR_EN enum
5415 typedef enum DCP_CURSOR_EN {
5421  * DCP_CUR_INV_TRANS_CLAMP enum
5424 typedef enum DCP_CUR_INV_TRANS_CLAMP {
5430  * DCP_CURSOR_MODE enum
5433 typedef enum DCP_CURSOR_MODE {
5441  * DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM enum
5444 typedef enum DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM {
5450  * DCP_CURSOR_2X_MAGNIFY enum
5453 typedef enum DCP_CURSOR_2X_MAGNIFY {
5459  * DCP_CURSOR_FORCE_MC_ON enum
5462 typedef enum DCP_CURSOR_FORCE_MC_ON {
5468  * DCP_CURSOR_URGENT_CONTROL enum
5471 typedef enum DCP_CURSOR_URGENT_CONTROL {
5480  * DCP_CURSOR_UPDATE_PENDING enum
5483 typedef enum DCP_CURSOR_UPDATE_PENDING {
5489  * DCP_CURSOR_UPDATE_TAKEN enum
5492 typedef enum DCP_CURSOR_UPDATE_TAKEN {
5498  * DCP_CURSOR_UPDATE_LOCK enum
5501 typedef enum DCP_CURSOR_UPDATE_LOCK {
5507  * DCP_CURSOR_DISABLE_MULTIPLE_UPDATE enum
5510 typedef enum DCP_CURSOR_DISABLE_MULTIPLE_UPDATE {
5516  * DCP_CURSOR_UPDATE_STEREO_MODE enum
5519 typedef enum DCP_CURSOR_UPDATE_STEREO_MODE {
5527  * DCP_CUR2_INV_TRANS_CLAMP enum
5530 typedef enum DCP_CUR2_INV_TRANS_CLAMP {
5536  * DCP_CUR_REQUEST_FILTER_DIS enum
5539 typedef enum DCP_CUR_REQUEST_FILTER_DIS {
5545  * DCP_CURSOR_STEREO_EN enum
5548 typedef enum DCP_CURSOR_STEREO_EN {
5554  * DCP_CURSOR_STEREO_OFFSET_YNX enum
5557 typedef enum DCP_CURSOR_STEREO_OFFSET_YNX {
5563  * DCP_DC_LUT_RW_MODE enum
5566 typedef enum DCP_DC_LUT_RW_MODE {
5572  * DCP_DC_LUT_VGA_ACCESS_ENABLE enum
5575 typedef enum DCP_DC_LUT_VGA_ACCESS_ENABLE {
5581  * DCP_DC_LUT_AUTOFILL enum
5584 typedef enum DCP_DC_LUT_AUTOFILL {
5590  * DCP_DC_LUT_AUTOFILL_DONE enum
5593 typedef enum DCP_DC_LUT_AUTOFILL_DONE {
5599  * DCP_DC_LUT_INC_B enum
5602 typedef enum DCP_DC_LUT_INC_B {
5616  * DCP_DC_LUT_DATA_B_SIGNED_EN enum
5619 typedef enum DCP_DC_LUT_DATA_B_SIGNED_EN {
5625  * DCP_DC_LUT_DATA_B_FLOAT_POINT_EN enum
5628 typedef enum DCP_DC_LUT_DATA_B_FLOAT_POINT_EN {
5634  * DCP_DC_LUT_DATA_B_FORMAT enum
5637 typedef enum DCP_DC_LUT_DATA_B_FORMAT {
5645  * DCP_DC_LUT_INC_G enum
5648 typedef enum DCP_DC_LUT_INC_G {
5662  * DCP_DC_LUT_DATA_G_SIGNED_EN enum
5665 typedef enum DCP_DC_LUT_DATA_G_SIGNED_EN {
5671  * DCP_DC_LUT_DATA_G_FLOAT_POINT_EN enum
5674 typedef enum DCP_DC_LUT_DATA_G_FLOAT_POINT_EN {
5680  * DCP_DC_LUT_DATA_G_FORMAT enum
5683 typedef enum DCP_DC_LUT_DATA_G_FORMAT {
5691  * DCP_DC_LUT_INC_R enum
5694 typedef enum DCP_DC_LUT_INC_R {
5708  * DCP_DC_LUT_DATA_R_SIGNED_EN enum
5711 typedef enum DCP_DC_LUT_DATA_R_SIGNED_EN {
5717  * DCP_DC_LUT_DATA_R_FLOAT_POINT_EN enum
5720 typedef enum DCP_DC_LUT_DATA_R_FLOAT_POINT_EN {
5726  * DCP_DC_LUT_DATA_R_FORMAT enum
5729 typedef enum DCP_DC_LUT_DATA_R_FORMAT {
5737  * DCP_CRC_ENABLE enum
5740 typedef enum DCP_CRC_ENABLE {
5746  * DCP_CRC_SOURCE_SEL enum
5749 typedef enum DCP_CRC_SOURCE_SEL {
5757  * DCP_CRC_LINE_SEL enum
5760 typedef enum DCP_CRC_LINE_SEL {
5768  * DCP_GRPH_FLIP_RATE enum
5771 typedef enum DCP_GRPH_FLIP_RATE {
5783  * DCP_GRPH_FLIP_RATE_ENABLE enum
5786 typedef enum DCP_GRPH_FLIP_RATE_ENABLE {
5792  * DCP_GSL0_EN enum
5795 typedef enum DCP_GSL0_EN {
5801  * DCP_GSL1_EN enum
5804 typedef enum DCP_GSL1_EN {
5810  * DCP_GSL2_EN enum
5813 typedef enum DCP_GSL2_EN {
5819  * DCP_GSL_MASTER_EN enum
5822 typedef enum DCP_GSL_MASTER_EN {
5828  * DCP_GSL_XDMA_GROUP enum
5831 typedef enum DCP_GSL_XDMA_GROUP {
5839  * DCP_GSL_XDMA_GROUP_UNDERFLOW_EN enum
5842 typedef enum DCP_GSL_XDMA_GROUP_UNDERFLOW_EN {
5848  * DCP_GSL_SYNC_SOURCE enum
5851 typedef enum DCP_GSL_SYNC_SOURCE {
5859  * DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC enum
5862 typedef enum DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC {
5868  * DCP_GSL_DELAY_SURFACE_UPDATE_PENDING enum
5871 typedef enum DCP_GSL_DELAY_SURFACE_UPDATE_PENDING {
5877  * DCP_TEST_DEBUG_WRITE_EN enum
5880 typedef enum DCP_TEST_DEBUG_WRITE_EN {
5886  * DCP_GRPH_STEREOSYNC_FLIP_EN enum
5889 typedef enum DCP_GRPH_STEREOSYNC_FLIP_EN {
5895  * DCP_GRPH_STEREOSYNC_FLIP_MODE enum
5898 typedef enum DCP_GRPH_STEREOSYNC_FLIP_MODE {
5906  * DCP_GRPH_STEREOSYNC_SELECT_DISABLE enum
5909 typedef enum DCP_GRPH_STEREOSYNC_SELECT_DISABLE {
5915  * DCP_GRPH_ROTATION_ANGLE enum
5918 typedef enum DCP_GRPH_ROTATION_ANGLE {
5926  * DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN enum
5929 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN {
5935  * DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE enum
5938 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE {
5944  * DCP_GRPH_REGAMMA_MODE enum
5947 typedef enum DCP_GRPH_REGAMMA_MODE {
5956  * DCP_ALPHA_ROUND_TRUNC_MODE enum
5959 typedef enum DCP_ALPHA_ROUND_TRUNC_MODE {
5965  * DCP_CURSOR_ALPHA_BLND_ENA enum
5968 typedef enum DCP_CURSOR_ALPHA_BLND_ENA {
5974  * DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK enum
5977 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK {
5983  * DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK enum
5986 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK {
5992  * DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK enum
5995 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK {
6001  * DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK enum
6004 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK {
6010  * DCP_GRPH_SURFACE_COUNTER_EN enum
6013 typedef enum DCP_GRPH_SURFACE_COUNTER_EN {
6019  * DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT enum
6022 typedef enum DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT {
6038  * DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED enum
6041 typedef enum DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED {
6047  * DCP_GRPH_XDMA_FLIP_TYPE_CLEAR enum
6050 typedef enum DCP_GRPH_XDMA_FLIP_TYPE_CLEAR {
6056  * DCP_GRPH_XDMA_DRR_MODE_ENABLE enum
6059 typedef enum DCP_GRPH_XDMA_DRR_MODE_ENABLE {
6065  * DCP_GRPH_XDMA_MULTIFLIP_ENABLE enum
6068 typedef enum DCP_GRPH_XDMA_MULTIFLIP_ENABLE {
6074  * DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK enum
6077 typedef enum DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK {
6083  * DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK enum
6086 typedef enum DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK {
6096  * PERFCOUNTER_CVALUE_SEL enum
6099 typedef enum PERFCOUNTER_CVALUE_SEL {
6111  * PERFCOUNTER_INC_MODE enum
6114 typedef enum PERFCOUNTER_INC_MODE {
6123  * PERFCOUNTER_HW_CNTL_SEL enum
6126 typedef enum PERFCOUNTER_HW_CNTL_SEL {
6132  * PERFCOUNTER_RUNEN_MODE enum
6135 typedef enum PERFCOUNTER_RUNEN_MODE {
6141  * PERFCOUNTER_CNTOFF_START_DIS enum
6144 typedef enum PERFCOUNTER_CNTOFF_START_DIS {
6150  * PERFCOUNTER_RESTART_EN enum
6153 typedef enum PERFCOUNTER_RESTART_EN {
6159  * PERFCOUNTER_INT_EN enum
6162 typedef enum PERFCOUNTER_INT_EN {
6168  * PERFCOUNTER_OFF_MASK enum
6171 typedef enum PERFCOUNTER_OFF_MASK {
6177  * PERFCOUNTER_ACTIVE enum
6180 typedef enum PERFCOUNTER_ACTIVE {
6186  * PERFCOUNTER_INT_TYPE enum
6189 typedef enum PERFCOUNTER_INT_TYPE {
6195  * PERFCOUNTER_COUNTED_VALUE_TYPE enum
6198 typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
6205  * PERFCOUNTER_CNTL_SEL enum
6208 typedef enum PERFCOUNTER_CNTL_SEL {
6220  * PERFCOUNTER_CNT0_STATE enum
6223 typedef enum PERFCOUNTER_CNT0_STATE {
6231  * PERFCOUNTER_STATE_SEL0 enum
6234 typedef enum PERFCOUNTER_STATE_SEL0 {
6240  * PERFCOUNTER_CNT1_STATE enum
6243 typedef enum PERFCOUNTER_CNT1_STATE {
6251  * PERFCOUNTER_STATE_SEL1 enum
6254 typedef enum PERFCOUNTER_STATE_SEL1 {
6260  * PERFCOUNTER_CNT2_STATE enum
6263 typedef enum PERFCOUNTER_CNT2_STATE {
6271  * PERFCOUNTER_STATE_SEL2 enum
6274 typedef enum PERFCOUNTER_STATE_SEL2 {
6280  * PERFCOUNTER_CNT3_STATE enum
6283 typedef enum PERFCOUNTER_CNT3_STATE {
6291  * PERFCOUNTER_STATE_SEL3 enum
6294 typedef enum PERFCOUNTER_STATE_SEL3 {
6300  * PERFCOUNTER_CNT4_STATE enum
6303 typedef enum PERFCOUNTER_CNT4_STATE {
6311  * PERFCOUNTER_STATE_SEL4 enum
6314 typedef enum PERFCOUNTER_STATE_SEL4 {
6320  * PERFCOUNTER_CNT5_STATE enum
6323 typedef enum PERFCOUNTER_CNT5_STATE {
6331  * PERFCOUNTER_STATE_SEL5 enum
6334 typedef enum PERFCOUNTER_STATE_SEL5 {
6340  * PERFCOUNTER_CNT6_STATE enum
6343 typedef enum PERFCOUNTER_CNT6_STATE {
6351  * PERFCOUNTER_STATE_SEL6 enum
6354 typedef enum PERFCOUNTER_STATE_SEL6 {
6360  * PERFCOUNTER_CNT7_STATE enum
6363 typedef enum PERFCOUNTER_CNT7_STATE {
6371  * PERFCOUNTER_STATE_SEL7 enum
6374 typedef enum PERFCOUNTER_STATE_SEL7 {
6380  * PERFMON_STATE enum
6383 typedef enum PERFMON_STATE {
6391  * PERFMON_CNTOFF_AND_OR enum
6394 typedef enum PERFMON_CNTOFF_AND_OR {
6400  * PERFMON_CNTOFF_INT_EN enum
6403 typedef enum PERFMON_CNTOFF_INT_EN {
6409  * PERFMON_CNTOFF_INT_TYPE enum
6412 typedef enum PERFMON_CNTOFF_INT_TYPE {
6422  * SCL_C_RAM_TAP_PAIR_IDX enum
6425 typedef enum SCL_C_RAM_TAP_PAIR_IDX {
6434  * SCL_C_RAM_PHASE enum
6437 typedef enum SCL_C_RAM_PHASE {
6450  * SCL_C_RAM_FILTER_TYPE enum
6453 typedef enum SCL_C_RAM_FILTER_TYPE {
6461  * SCL_MODE_SEL enum
6464 typedef enum SCL_MODE_SEL {
6472  * SCL_PSCL_EN enum
6475 typedef enum SCL_PSCL_EN {
6481  * SCL_V_NUM_OF_TAPS enum
6484 typedef enum SCL_V_NUM_OF_TAPS {
6494  * SCL_H_NUM_OF_TAPS enum
6497 typedef enum SCL_H_NUM_OF_TAPS {
6507  * SCL_BOUNDARY_MODE enum
6510 typedef enum SCL_BOUNDARY_MODE {
6516  * SCL_EARLY_EOL_MOD enum
6519 typedef enum SCL_EARLY_EOL_MOD {
6525  * SCL_BYPASS_MODE enum
6528 typedef enum SCL_BYPASS_MODE {
6536  * SCL_V_MANUAL_REPLICATE_FACTOR enum
6539 typedef enum SCL_V_MANUAL_REPLICATE_FACTOR {
6559  * SCL_H_MANUAL_REPLICATE_FACTOR enum
6562 typedef enum SCL_H_MANUAL_REPLICATE_FACTOR {
6582  * SCL_V_CALC_AUTO_RATIO_EN enum
6585 typedef enum SCL_V_CALC_AUTO_RATIO_EN {
6591  * SCL_H_CALC_AUTO_RATIO_EN enum
6594 typedef enum SCL_H_CALC_AUTO_RATIO_EN {
6600  * SCL_H_FILTER_PICK_NEAREST enum
6603 typedef enum SCL_H_FILTER_PICK_NEAREST {
6609  * SCL_H_2TAP_HARDCODE_COEF_EN enum
6612 typedef enum SCL_H_2TAP_HARDCODE_COEF_EN {
6618  * SCL_V_FILTER_PICK_NEAREST enum
6621 typedef enum SCL_V_FILTER_PICK_NEAREST {
6627  * SCL_V_2TAP_HARDCODE_COEF_EN enum
6630 typedef enum SCL_V_2TAP_HARDCODE_COEF_EN {
6636  * SCL_UPDATE_TAKEN enum
6639 typedef enum SCL_UPDATE_TAKEN {
6645  * SCL_UPDATE_LOCK enum
6648 typedef enum SCL_UPDATE_LOCK {
6654  * SCL_COEF_UPDATE_COMPLETE enum
6657 typedef enum SCL_COEF_UPDATE_COMPLETE {
6663  * SCL_HF_SHARP_SCALE_FACTOR enum
6666 typedef enum SCL_HF_SHARP_SCALE_FACTOR {
6678  * SCL_HF_SHARP_EN enum
6681 typedef enum SCL_HF_SHARP_EN {
6687  * SCL_VF_SHARP_SCALE_FACTOR enum
6690 typedef enum SCL_VF_SHARP_SCALE_FACTOR {
6702  * SCL_VF_SHARP_EN enum
6705 typedef enum SCL_VF_SHARP_EN {
6711  * SCL_ALU_DISABLE enum
6714 typedef enum SCL_ALU_DISABLE {
6720  * SCL_HOST_CONFLICT_MASK enum
6723 typedef enum SCL_HOST_CONFLICT_MASK {
6729  * SCL_SCL_MODE_CHANGE_MASK enum
6732 typedef enum SCL_SCL_MODE_CHANGE_MASK {
6742  * SCLV_MODE_SEL enum
6745 typedef enum SCLV_MODE_SEL {
6753  * SCLV_INTERLACE_SOURCE enum
6756 typedef enum SCLV_INTERLACE_SOURCE {
6763  * SCLV_UPDATE_LOCK enum
6766 typedef enum SCLV_UPDATE_LOCK {
6772  * SCLV_COEF_UPDATE_COMPLETE enum
6775 typedef enum SCLV_COEF_UPDATE_COMPLETE {
6785  * DPRX_SD_PIXEL_ENCODING enum
6788 typedef enum DPRX_SD_PIXEL_ENCODING {
6796  * DPRX_SD_COMPONENT_DEPTH enum
6799 typedef enum DPRX_SD_COMPONENT_DEPTH {
6812  * AZ_LATENCY_COUNTER_CONTROL enum
6815 typedef enum AZ_LATENCY_COUNTER_CONTROL {
6825  * BLND_CONTROL_BLND_MODE enum
6828 typedef enum BLND_CONTROL_BLND_MODE {
6836  * BLND_CONTROL_BLND_STEREO_TYPE enum
6839 typedef enum BLND_CONTROL_BLND_STEREO_TYPE {
6847  * BLND_CONTROL_BLND_STEREO_POLARITY enum
6850 typedef enum BLND_CONTROL_BLND_STEREO_POLARITY {
6856  * BLND_CONTROL_BLND_FEEDTHROUGH_EN enum
6859 typedef enum BLND_CONTROL_BLND_FEEDTHROUGH_EN {
6865  * BLND_CONTROL_BLND_ALPHA_MODE enum
6868 typedef enum BLND_CONTROL_BLND_ALPHA_MODE {
6876  * BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY enum
6879 typedef enum BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
6885  * BLND_CONTROL_BLND_MULTIPLIED_MODE enum
6888 typedef enum BLND_CONTROL_BLND_MULTIPLIED_MODE {
6894  * BLND_SM_CONTROL2_SM_MODE enum
6897 typedef enum BLND_SM_CONTROL2_SM_MODE {
6905  * BLND_SM_CONTROL2_SM_FRAME_ALTERNATE enum
6908 typedef enum BLND_SM_CONTROL2_SM_FRAME_ALTERNATE {
6914  * BLND_SM_CONTROL2_SM_FIELD_ALTERNATE enum
6917 typedef enum BLND_SM_CONTROL2_SM_FIELD_ALTERNATE {
6923  * BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL enum
6926 typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
6934  * BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL enum
6937 typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
6945  * BLND_CONTROL2_PTI_ENABLE enum
6948 typedef enum BLND_CONTROL2_PTI_ENABLE {
6954  * BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN enum
6957 typedef enum BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
6963  * BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN enum
6966 typedef enum BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
6972  * BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK enum
6975 typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
6981  * BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK enum
6984 typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
6990  * BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK enum
6993 typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
6999  * BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK enum
7002 typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
7008  * BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK enum
7011 typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
7017  * BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK enum
7020 typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
7026  * BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK enum
7029 typedef enum BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
7035  * BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK enum
7038 typedef enum BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
7044  * BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE enum
7047 typedef enum BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
7053  * BLND_DEBUG_BLND_CNV_MUX_SELECT enum
7056 typedef enum BLND_DEBUG_BLND_CNV_MUX_SELECT {
7062  * BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN enum
7065 typedef enum BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
7075  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7078 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7092  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7095 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7101  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7104 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7110  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7113 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7119  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7122 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7128 … AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7131 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAP…
7137  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7140 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7146  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7149 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7155  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
7158 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
7164  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7167 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVER…
7173  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7176 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT…
7182  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7185 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7191  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
7194 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITI…
7200  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7203 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7217  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7220 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7226  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7229 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7235  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7238 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7244  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7247 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7253  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7256 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILIT…
7262  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7265 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7271  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7274 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7280  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7283 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
7289  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7292 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
7298  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7301 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7307  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
7310 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
7316  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
7319 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
7325  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
7328 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
7334  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
7337 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
7343  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
7346 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
7352  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
7355 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
7361  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
7364 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
7370  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
7373 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
7379  * AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
7382 typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
7388  * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
7391 typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
7401  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7404 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7418  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7421 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7427  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7430 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7436  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7439 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7445  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7448 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7454 …A_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7457 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPON…
7463  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7466 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7472  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7475 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7481  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
7484 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
7490 …ALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7493 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETE…
7499  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7502 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_P…
7508  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7511 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PR…
7517 …AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
7520 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPA…
7526  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7529 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7543  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7546 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7552  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7555 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7561  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7564 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7570  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7573 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7579 … AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7582 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAP…
7588  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7591 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7597  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7600 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7606  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7609 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVER…
7615  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7618 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT…
7624  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7627 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7633  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP enum
7636 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
7642  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
7645 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
7651  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI enum
7654 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
7660  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
7663 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
7669  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
7672 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
7678  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
7681 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
7687  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
7690 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
7696  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
7699 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
7705  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
7708 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
7714  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
7717 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
7723  * AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
7726 typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
7736  * UNP_GRPH_EN enum
7739 typedef enum UNP_GRPH_EN {
7745  * UNP_GRPH_DEPTH enum
7748 typedef enum UNP_GRPH_DEPTH {
7755  * UNP_GRPH_NUM_BANKS enum
7758 typedef enum UNP_GRPH_NUM_BANKS {
7766  * UNP_GRPH_BANK_WIDTH enum
7769 typedef enum UNP_GRPH_BANK_WIDTH {
7777  * UNP_GRPH_BANK_HEIGHT enum
7780 typedef enum UNP_GRPH_BANK_HEIGHT {
7788  * UNP_GRPH_TILE_SPLIT enum
7791 typedef enum UNP_GRPH_TILE_SPLIT {
7802  * UNP_GRPH_ADDRESS_TRANSLATION_ENABLE enum
7805 typedef enum UNP_GRPH_ADDRESS_TRANSLATION_ENABLE {
7811  * UNP_GRPH_MACRO_TILE_ASPECT enum
7814 typedef enum UNP_GRPH_MACRO_TILE_ASPECT {
7822  * UNP_GRPH_COLOR_EXPANSION_MODE enum
7825 typedef enum UNP_GRPH_COLOR_EXPANSION_MODE {
7831  * UNP_VIDEO_FORMAT enum
7834 typedef enum UNP_VIDEO_FORMAT {
7846  * UNP_GRPH_ENDIAN_SWAP enum
7849 typedef enum UNP_GRPH_ENDIAN_SWAP {
7857  * UNP_GRPH_RED_CROSSBAR enum
7860 typedef enum UNP_GRPH_RED_CROSSBAR {
7868  * UNP_GRPH_GREEN_CROSSBAR enum
7871 typedef enum UNP_GRPH_GREEN_CROSSBAR {
7879  * UNP_GRPH_BLUE_CROSSBAR enum
7882 typedef enum UNP_GRPH_BLUE_CROSSBAR {
7890  * UNP_GRPH_MODE_UPDATE_LOCKG enum
7893 typedef enum UNP_GRPH_MODE_UPDATE_LOCKG {
7899  * UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK enum
7902 typedef enum UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
7908  * UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE enum
7911 typedef enum UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
7917  * UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE enum
7920 typedef enum UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
7926  * UNP_GRPH_STEREOSYNC_FLIP_EN enum
7929 typedef enum UNP_GRPH_STEREOSYNC_FLIP_EN {
7935  * UNP_GRPH_STEREOSYNC_FLIP_MODE enum
7938 typedef enum UNP_GRPH_STEREOSYNC_FLIP_MODE {
7946  * UNP_GRPH_STACK_INTERLACE_FLIP_EN enum
7949 typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_EN {
7955  * UNP_GRPH_STACK_INTERLACE_FLIP_MODE enum
7958 typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_MODE {
7966  * UNP_GRPH_STEREOSYNC_SELECT_DISABLE enum
7969 typedef enum UNP_GRPH_STEREOSYNC_SELECT_DISABLE {
7975  * UNP_CRC_SOURCE_SEL enum
7978 typedef enum UNP_CRC_SOURCE_SEL {
7987  * UNP_CRC_LINE_SEL enum
7990 typedef enum UNP_CRC_LINE_SEL {
7998  * UNP_ROTATION_ANGLE enum
8001 typedef enum UNP_ROTATION_ANGLE {
8013  * UNP_PIXEL_DROP enum
8016 typedef enum UNP_PIXEL_DROP {
8022  * UNP_BUFFER_MODE enum
8025 typedef enum UNP_BUFFER_MODE {
8035  * DP_LINK_TRAINING_COMPLETE enum
8038 typedef enum DP_LINK_TRAINING_COMPLETE {
8044  * DP_EMBEDDED_PANEL_MODE enum
8047 typedef enum DP_EMBEDDED_PANEL_MODE {
8053  * DP_PIXEL_ENCODING enum
8056 typedef enum DP_PIXEL_ENCODING {
8067  * DP_DYN_RANGE enum
8070 typedef enum DP_DYN_RANGE {
8076  * DP_YCBCR_RANGE enum
8079 typedef enum DP_YCBCR_RANGE {
8085  * DP_COMPONENT_DEPTH enum
8088 typedef enum DP_COMPONENT_DEPTH {
8098  * DP_MSA_MISC0_OVERRIDE_ENABLE enum
8101 typedef enum DP_MSA_MISC0_OVERRIDE_ENABLE {
8107  * DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE enum
8110 typedef enum DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE {
8116  * DP_UDI_LANES enum
8119 typedef enum DP_UDI_LANES {
8127  * DP_VID_STREAM_DIS_DEFER enum
8130 typedef enum DP_VID_STREAM_DIS_DEFER {
8137  * DP_STEER_OVERFLOW_ACK enum
8140 typedef enum DP_STEER_OVERFLOW_ACK {
8146  * DP_STEER_OVERFLOW_MASK enum
8149 typedef enum DP_STEER_OVERFLOW_MASK {
8155  * DP_TU_OVERFLOW_ACK enum
8158 typedef enum DP_TU_OVERFLOW_ACK {
8164  * DPHY_ALT_SCRAMBLER_RESET_EN enum
8167 typedef enum DPHY_ALT_SCRAMBLER_RESET_EN {
8173  * DPHY_ALT_SCRAMBLER_RESET_SEL enum
8176 typedef enum DPHY_ALT_SCRAMBLER_RESET_SEL {
8182  * DP_VID_TIMING_MODE enum
8185 typedef enum DP_VID_TIMING_MODE {
8191  * DP_VID_M_N_DOUBLE_BUFFER_MODE enum
8194 typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
8200  * DP_VID_M_N_GEN_EN enum
8203 typedef enum DP_VID_M_N_GEN_EN {
8209  * DP_VID_M_DOUBLE_VALUE_EN enum
8212 typedef enum DP_VID_M_DOUBLE_VALUE_EN {
8218  * DP_VID_ENHANCED_FRAME_MODE enum
8221 typedef enum DP_VID_ENHANCED_FRAME_MODE {
8227  * DP_VID_MSA_TOP_FIELD_MODE enum
8230 typedef enum DP_VID_MSA_TOP_FIELD_MODE {
8236  * DP_VID_VBID_FIELD_POL enum
8239 typedef enum DP_VID_VBID_FIELD_POL {
8245  * DP_VID_STREAM_DISABLE_ACK enum
8248 typedef enum DP_VID_STREAM_DISABLE_ACK {
8254  * DP_VID_STREAM_DISABLE_MASK enum
8257 typedef enum DP_VID_STREAM_DISABLE_MASK {
8263  * DPHY_ATEST_SEL_LANE0 enum
8266 typedef enum DPHY_ATEST_SEL_LANE0 {
8272  * DPHY_ATEST_SEL_LANE1 enum
8275 typedef enum DPHY_ATEST_SEL_LANE1 {
8281  * DPHY_ATEST_SEL_LANE2 enum
8284 typedef enum DPHY_ATEST_SEL_LANE2 {
8290  * DPHY_ATEST_SEL_LANE3 enum
8293 typedef enum DPHY_ATEST_SEL_LANE3 {
8299  * DPHY_SCRAMBLER_SEL enum
8302 typedef enum DPHY_SCRAMBLER_SEL {
8308  * DPHY_BYPASS enum
8311 typedef enum DPHY_BYPASS {
8317  * DPHY_SKEW_BYPASS enum
8320 typedef enum DPHY_SKEW_BYPASS {
8326  * DPHY_TRAINING_PATTERN_SEL enum
8329 typedef enum DPHY_TRAINING_PATTERN_SEL {
8337  * DPHY_8B10B_RESET enum
8340 typedef enum DPHY_8B10B_RESET {
8346  * DP_DPHY_8B10B_EXT_DISP enum
8349 typedef enum DP_DPHY_8B10B_EXT_DISP {
8355  * DPHY_8B10B_CUR_DISP enum
8358 typedef enum DPHY_8B10B_CUR_DISP {
8364  * DPHY_PRBS_EN enum
8367 typedef enum DPHY_PRBS_EN {
8373  * DPHY_PRBS_SEL enum
8376 typedef enum DPHY_PRBS_SEL {
8383  * DPHY_SCRAMBLER_DIS enum
8386 typedef enum DPHY_SCRAMBLER_DIS {
8392  * DPHY_SCRAMBLER_ADVANCE enum
8395 typedef enum DPHY_SCRAMBLER_ADVANCE {
8401  * DPHY_SCRAMBLER_KCODE enum
8404 typedef enum DPHY_SCRAMBLER_KCODE {
8410  * DPHY_LOAD_BS_COUNT_START enum
8413 typedef enum DPHY_LOAD_BS_COUNT_START {
8419  * DPHY_CRC_EN enum
8422 typedef enum DPHY_CRC_EN {
8428  * DPHY_CRC_CONT_EN enum
8431 typedef enum DPHY_CRC_CONT_EN {
8437  * DPHY_CRC_FIELD enum
8440 typedef enum DPHY_CRC_FIELD {
8446  * DPHY_CRC_SEL enum
8449 typedef enum DPHY_CRC_SEL {
8457  * DPHY_RX_FAST_TRAINING_CAPABLE enum
8460 typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
8466  * DP_SEC_COLLISION_ACK enum
8469 typedef enum DP_SEC_COLLISION_ACK {
8475  * DP_SEC_AUDIO_MUTE enum
8478 typedef enum DP_SEC_AUDIO_MUTE {
8484  * DP_SEC_TIMESTAMP_MODE enum
8487 typedef enum DP_SEC_TIMESTAMP_MODE {
8493  * DP_SEC_ASP_PRIORITY enum
8496 typedef enum DP_SEC_ASP_PRIORITY {
8502  * DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE enum
8505 typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
8511  * DP_MSE_SAT_UPDATE_ACT enum
8514 typedef enum DP_MSE_SAT_UPDATE_ACT {
8521  * DP_MSE_LINK_LINE enum
8524 typedef enum DP_MSE_LINK_LINE {
8532  * DP_MSE_BLANK_CODE enum
8535 typedef enum DP_MSE_BLANK_CODE {
8541  * DP_MSE_TIMESTAMP_MODE enum
8544 typedef enum DP_MSE_TIMESTAMP_MODE {
8550  * DP_MSE_ZERO_ENCODER enum
8553 typedef enum DP_MSE_ZERO_ENCODER {
8559  * DP_MSE_OUTPUT_DPDBG_DATA enum
8562 typedef enum DP_MSE_OUTPUT_DPDBG_DATA {
8568  * DP_DPHY_HBR2_PATTERN_CONTROL_MODE enum
8571 typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
8580  * DPHY_CRC_MST_PHASE_ERROR_ACK enum
8583 typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
8589  * DPHY_SW_FAST_TRAINING_START enum
8592 typedef enum DPHY_SW_FAST_TRAINING_START {
8598  * DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN enum
8601 typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
8607  * DP_DPHY_FAST_TRAINING_COMPLETE_MASK enum
8610 typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
8616  * DP_DPHY_FAST_TRAINING_COMPLETE_ACK enum
8619 typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
8625  * DP_MSA_V_TIMING_OVERRIDE_EN enum
8628 typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
8634  * DP_SEC_GSP0_PRIORITY enum
8637 typedef enum DP_SEC_GSP0_PRIORITY {
8643  * DP_SEC_GSP0_SEND enum
8646 typedef enum DP_SEC_GSP0_SEND {
8656  * COL_MAN_UPDATE_LOCK enum
8659 typedef enum COL_MAN_UPDATE_LOCK {
8665  * COL_MAN_DISABLE_MULTIPLE_UPDATE enum
8668 typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE {
8674  * COL_MAN_INPUTCSC_MODE enum
8677 typedef enum COL_MAN_INPUTCSC_MODE {
8685  * COL_MAN_INPUTCSC_TYPE enum
8688 typedef enum COL_MAN_INPUTCSC_TYPE {
8695  * COL_MAN_INPUTCSC_CONVERT enum
8698 typedef enum COL_MAN_INPUTCSC_CONVERT {
8704  * COL_MAN_PRESCALE_MODE enum
8707 typedef enum COL_MAN_PRESCALE_MODE {
8714  * COL_MAN_INPUT_GAMMA_MODE enum
8717 typedef enum COL_MAN_INPUT_GAMMA_MODE {
8724  * COL_MAN_OUTPUT_CSC_MODE enum
8727 typedef enum COL_MAN_OUTPUT_CSC_MODE {
8738  * COL_MAN_DENORM_CLAMP_CONTROL enum
8741 typedef enum COL_MAN_DENORM_CLAMP_CONTROL {
8749  * COL_MAN_REGAMMA_MODE_CONTROL enum
8752 typedef enum COL_MAN_REGAMMA_MODE_CONTROL {
8761  * COL_MAN_GLOBAL_PASSTHROUGH_ENABLE enum
8764 typedef enum COL_MAN_GLOBAL_PASSTHROUGH_ENABLE {
8770  * COL_MAN_DEGAMMA_MODE enum
8773 typedef enum COL_MAN_DEGAMMA_MODE {
8780  * COL_MAN_GAMUT_REMAP_MODE enum
8783 typedef enum COL_MAN_GAMUT_REMAP_MODE {
8799  * DP_AUX_CONTROL_HPD_SEL enum
8802 typedef enum DP_AUX_CONTROL_HPD_SEL {
8812  * DP_AUX_CONTROL_TEST_MODE enum
8815 typedef enum DP_AUX_CONTROL_TEST_MODE {
8821  * DP_AUX_SW_CONTROL_SW_GO enum
8824 typedef enum DP_AUX_SW_CONTROL_SW_GO {
8830  * DP_AUX_SW_CONTROL_LS_READ_TRIG enum
8833 typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
8839  * DP_AUX_ARB_CONTROL_ARB_PRIORITY enum
8842 typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
8850  * DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ enum
8853 typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
8859  * DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG enum
8862 typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
8868  * DP_AUX_INT_ACK enum
8871 typedef enum DP_AUX_INT_ACK {
8877  * DP_AUX_LS_UPDATE_ACK enum
8880 typedef enum DP_AUX_LS_UPDATE_ACK {
8886  * DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL enum
8889 typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
8895  * DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE enum
8898 typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
8906  * DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN enum
8909 typedef enum DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN {
8921  * DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY enum
8924 typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
8934  * DP_AUX_DPHY_RX_CONTROL_START_WINDOW enum
8937 typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
8949  * DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW enum
8952 typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
8964  * DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN enum
8967 typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
8975  * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT enum
8978 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
8984  * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START enum
8987 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
8993  * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP enum
8996 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
9002  * DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN enum
9005 typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
9013  * DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN enum
9016 typedef enum DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN {
9028  * DP_AUX_DPHY_RX_DETECTION_THRESHOLD enum
9031 typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
9043  * DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ enum
9046 typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
9052  * DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW enum
9055 typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
9063  * DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT enum
9066 typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
9074  * DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN enum
9077 typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
9085  * DP_AUX_ERR_OCCURRED_ACK enum
9088 typedef enum DP_AUX_ERR_OCCURRED_ACK {
9094  * DP_AUX_POTENTIAL_ERR_REACHED_ACK enum
9097 typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
9103  * DP_AUX_DEFINITE_ERR_REACHED_ACK enum
9106 typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
9112  * DP_AUX_RESET enum
9115 typedef enum DP_AUX_RESET {
9121  * DP_AUX_RESET_DONE enum
9124 typedef enum DP_AUX_RESET_DONE {
9134  * DSI_COMMAND_MODE_SRC_FORMAT enum
9137 typedef enum DSI_COMMAND_MODE_SRC_FORMAT {
9147  * DSI_COMMAND_MODE_DST_FORMAT enum
9150 typedef enum DSI_COMMAND_MODE_DST_FORMAT {
9160  * DSI_FLAG_CLR enum
9163 typedef enum DSI_FLAG_CLR {
9169  * DSI_BIT_SWAP enum
9172 typedef enum DSI_BIT_SWAP {
9178  * DSI_CLK_GATING enum
9181 typedef enum DSI_CLK_GATING {
9187  * DSI_LANE_ULPS_REQUEST enum
9190 typedef enum DSI_LANE_ULPS_REQUEST {
9196  * DSI_LANE_ULPS_EXIT enum
9199 typedef enum DSI_LANE_ULPS_EXIT {
9205  * DSI_LANE_FORCE_TX_STOP enum
9208 typedef enum DSI_LANE_FORCE_TX_STOP {
9214  * DSI_CLOCK_LANE_HS_FORCE_REQUEST enum
9217 typedef enum DSI_CLOCK_LANE_HS_FORCE_REQUEST {
9223  * DSI_CONTROLLER_EN enum
9226 typedef enum DSI_CONTROLLER_EN {
9232  * DSI_VIDEO_MODE_EN enum
9235 typedef enum DSI_VIDEO_MODE_EN {
9241  * DSI_CMD_MODE_EN enum
9244 typedef enum DSI_CMD_MODE_EN {
9250  * DSI_DATA_LANE0_EN enum
9253 typedef enum DSI_DATA_LANE0_EN {
9259  * DSI_DATA_LANE1_EN enum
9262 typedef enum DSI_DATA_LANE1_EN {
9268  * DSI_DATA_LANE2_EN enum
9271 typedef enum DSI_DATA_LANE2_EN {
9277  * DSI_DATA_LANE3_EN enum
9280 typedef enum DSI_DATA_LANE3_EN {
9286  * DSI_CLOCK_LANE_EN enum
9289 typedef enum DSI_CLOCK_LANE_EN {
9295  * DSI_PHY_DATA_LANE0_EN enum
9298 typedef enum DSI_PHY_DATA_LANE0_EN {
9304  * DSI_PHY_DATA_LANE1_EN enum
9307 typedef enum DSI_PHY_DATA_LANE1_EN {
9313  * DSI_PHY_DATA_LANE2_EN enum
9316 typedef enum DSI_PHY_DATA_LANE2_EN {
9322  * DSI_PHY_DATA_LANE3_EN enum
9325 typedef enum DSI_PHY_DATA_LANE3_EN {
9331  * DSI_RESET_DISPCLK enum
9334 typedef enum DSI_RESET_DISPCLK {
9340  * DSI_RESET_DSICLK enum
9343 typedef enum DSI_RESET_DSICLK {
9349  * DSI_RESET_BYTECLK enum
9352 typedef enum DSI_RESET_BYTECLK {
9358  * DSI_RESET_ESCCLK enum
9361 typedef enum DSI_RESET_ESCCLK {
9367  * DSI_CRTC_SEL enum
9370 typedef enum DSI_CRTC_SEL {
9380  * DSI_PACKET_BYTE_MSB_LSB_FLIP enum
9383 typedef enum DSI_PACKET_BYTE_MSB_LSB_FLIP {
9389  * DSI_VIDEO_MODE_DST_FORMAT enum
9392 typedef enum DSI_VIDEO_MODE_DST_FORMAT {
9400  * DSI_VIDEO_TRAFFIC_MODE enum
9403 typedef enum DSI_VIDEO_TRAFFIC_MODE {
9411  * DSI_VIDEO_BLLP_PWR_MODE enum
9414 typedef enum DSI_VIDEO_BLLP_PWR_MODE {
9420  * DSI_VIDEO_EOF_BLLP_PWR_MODE enum
9423 typedef enum DSI_VIDEO_EOF_BLLP_PWR_MODE {
9429  * DSI_VIDEO_PWR_MODE enum
9432 typedef enum DSI_VIDEO_PWR_MODE {
9438  * DSI_VIDEO_PULSE_MODE_OPT enum
9441 typedef enum DSI_VIDEO_PULSE_MODE_OPT {
9447  * DSI_RGB_SWAP enum
9450 typedef enum DSI_RGB_SWAP {
9460  * DSI_CMD_PACKET_TYPE enum
9463 typedef enum DSI_CMD_PACKET_TYPE {
9469  * DSI_CMD_PWR_MODE enum
9472 typedef enum DSI_CMD_PWR_MODE {
9478  * DSI_CMD_EMBEDDED_MODE enum
9481 typedef enum DSI_CMD_EMBEDDED_MODE {
9487  * DSI_CMD_ORDER enum
9490 typedef enum DSI_CMD_ORDER {
9496  * DSI_DATA_BUFFER_ID enum
9499 typedef enum DSI_DATA_BUFFER_ID {
9505  * DSI_DWORD_BYTE_SWAP enum
9508 typedef enum DSI_DWORD_BYTE_SWAP {
9516  * DSI_INSERT_DCS_COMMAND enum
9519 typedef enum DSI_INSERT_DCS_COMMAND {
9525  * DSI_DMAFIFO_WRITE_WATERMARK enum
9528 typedef enum DSI_DMAFIFO_WRITE_WATERMARK {
9536  * DSI_DMAFIFO_READ_WATERMARK enum
9539 typedef enum DSI_DMAFIFO_READ_WATERMARK {
9547  * DSI_USE_DENG_LENGTH enum
9550 typedef enum DSI_USE_DENG_LENGTH {
9556  * DSI_COMMAND_TRIGGER_MODE enum
9559 typedef enum DSI_COMMAND_TRIGGER_MODE {
9565  * DSI_COMMAND_TRIGGER_SEL enum
9568 typedef enum DSI_COMMAND_TRIGGER_SEL {
9576  * DSI_HW_SOURCE_SEL enum
9579 typedef enum DSI_HW_SOURCE_SEL {
9587  * DSI_COMMAND_TRIGGER_ORDER enum
9590 typedef enum DSI_COMMAND_TRIGGER_ORDER {
9596  * DSI_TE_SRC_SEL enum
9599 typedef enum DSI_TE_SRC_SEL {
9605  * DSI_EXT_TE_MUX enum
9608 typedef enum DSI_EXT_TE_MUX {
9621  * DSI_EXT_TE_MODE enum
9624 typedef enum DSI_EXT_TE_MODE {
9632  * DSI_EXT_RESET_POL enum
9635 typedef enum DSI_EXT_RESET_POL {
9641  * DSI_EXT_TE_POL enum
9644 typedef enum DSI_EXT_TE_POL {
9650  * DSI_RESET_PANEL enum
9653 typedef enum DSI_RESET_PANEL {
9659  * DSI_CRC_ENABLE enum
9662 typedef enum DSI_CRC_ENABLE {
9668  * DSI_TX_EOT_APPEND enum
9671 typedef enum DSI_TX_EOT_APPEND {
9677  * DSI_RX_EOT_IGNORE enum
9680 typedef enum DSI_RX_EOT_IGNORE {
9686  * DSI_MIPI_BIST_RESET enum
9689 typedef enum DSI_MIPI_BIST_RESET {
9695  * DSI_MIPI_BIST_VIDEO_FRMT enum
9698 typedef enum DSI_MIPI_BIST_VIDEO_FRMT {
9704  * DSI_MIPI_BIST_START enum
9707 typedef enum DSI_MIPI_BIST_START {
9713  * DSI_DBG_CLK_SEL enum
9716 typedef enum DSI_DBG_CLK_SEL {
9729  * DSI_DENG_FIFO_USE_OVERWRITE_LEVEL enum
9732 typedef enum DSI_DENG_FIFO_USE_OVERWRITE_LEVEL {
9738  * DSI_DENG_FIFO_FORCE_RECAL_AVERAGE enum
9741 typedef enum DSI_DENG_FIFO_FORCE_RECAL_AVERAGE {
9747  * DSI_DENG_FIFO_FORCE_RECOMP_MINMAX enum
9750 typedef enum DSI_DENG_FIFO_FORCE_RECOMP_MINMAX {
9756  * DSI_DENG_FIFO_START enum
9759 typedef enum DSI_DENG_FIFO_START {
9765  * DSI_USE_CMDFIFO enum
9768 typedef enum DSI_USE_CMDFIFO {
9774  * DSI_CRTC_FREEZE_TRIG enum
9777 typedef enum DSI_CRTC_FREEZE_TRIG {
9783  * DSI_PERF_LATENCY_SEL enum
9786 typedef enum DSI_PERF_LATENCY_SEL {
9794  * DSI_DEBUG_DSICLK_SEL enum
9797 typedef enum DSI_DEBUG_DSICLK_SEL {
9808  * DSI_DEBUG_BYTECLK_SEL enum
9811 typedef enum DSI_DEBUG_BYTECLK_SEL {
9834  * DCIOCHIP_HPD_SEL enum
9837 typedef enum DCIOCHIP_HPD_SEL {
9843  * DCIOCHIP_PAD_MODE enum
9846 typedef enum DCIOCHIP_PAD_MODE {
9852  * DCIOCHIP_AUXSLAVE_PAD_MODE enum
9855 typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
9861  * DCIOCHIP_INVERT enum
9864 typedef enum DCIOCHIP_INVERT {
9870  * DCIOCHIP_PD_EN enum
9873 typedef enum DCIOCHIP_PD_EN {
9879  * DCIOCHIP_GPIO_MASK_EN enum
9882 typedef enum DCIOCHIP_GPIO_MASK_EN {
9888  * DCIOCHIP_MASK enum
9891 typedef enum DCIOCHIP_MASK {
9897  * DCIOCHIP_GPIO_I2C_MASK enum
9900 typedef enum DCIOCHIP_GPIO_I2C_MASK {
9906  * DCIOCHIP_GPIO_I2C_DRIVE enum
9909 typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
9915  * DCIOCHIP_GPIO_I2C_EN enum
9918 typedef enum DCIOCHIP_GPIO_I2C_EN {
9924  * DCIOCHIP_MASK_4BIT enum
9927 typedef enum DCIOCHIP_MASK_4BIT {
9933  * DCIOCHIP_ENABLE_4BIT enum
9936 typedef enum DCIOCHIP_ENABLE_4BIT {
9942  * DCIOCHIP_MASK_5BIT enum
9945 typedef enum DCIOCHIP_MASK_5BIT {
9951  * DCIOCHIP_ENABLE_5BIT enum
9954 typedef enum DCIOCHIP_ENABLE_5BIT {
9960  * DCIOCHIP_MASK_2BIT enum
9963 typedef enum DCIOCHIP_MASK_2BIT {
9969  * DCIOCHIP_ENABLE_2BIT enum
9972 typedef enum DCIOCHIP_ENABLE_2BIT {
9978  * DCIOCHIP_REF_27_SRC_SEL enum
9981 typedef enum DCIOCHIP_REF_27_SRC_SEL {
9989  * DCIOCHIP_DVO_VREFPON enum
9992 typedef enum DCIOCHIP_DVO_VREFPON {
9998  * DCIOCHIP_DVO_VREFSEL enum
10001 typedef enum DCIOCHIP_DVO_VREFSEL {
10007  * DCIOCHIP_SPDIF1_IMODE enum
10010 typedef enum DCIOCHIP_SPDIF1_IMODE {
10016  * DCIOCHIP_AUX_FALLSLEWSEL enum
10019 typedef enum DCIOCHIP_AUX_FALLSLEWSEL {
10027  * DCIOCHIP_AUX_SPIKESEL enum
10030 typedef enum DCIOCHIP_AUX_SPIKESEL {
10036  * DCIOCHIP_AUX_CSEL0P9 enum
10039 typedef enum DCIOCHIP_AUX_CSEL0P9 {
10045  * DCIOCHIP_AUX_CSEL1P1 enum
10048 typedef enum DCIOCHIP_AUX_CSEL1P1 {
10054  * DCIOCHIP_AUX_RSEL0P9 enum
10057 typedef enum DCIOCHIP_AUX_RSEL0P9 {
10063  * DCIOCHIP_AUX_RSEL1P1 enum
10066 typedef enum DCIOCHIP_AUX_RSEL1P1 {
10076  * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL enum
10079 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
10085  * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED enum
10088 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
10094  * GENERIC_AZ_CONTROLLER_REGISTER_STATUS enum
10097 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
10103  * GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED enum
10106 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
10112  * AZ_GLOBAL_CAPABILITIES enum
10115 typedef enum AZ_GLOBAL_CAPABILITIES {
10121  * GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE enum
10124 typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
10130  * GLOBAL_CONTROL_FLUSH_CONTROL enum
10133 typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
10139  * GLOBAL_CONTROL_CONTROLLER_RESET enum
10142 typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
10148  * AZ_STATE_CHANGE_STATUS enum
10151 typedef enum AZ_STATE_CHANGE_STATUS {
10157  * GLOBAL_STATUS_FLUSH_STATUS enum
10160 typedef enum GLOBAL_STATUS_FLUSH_STATUS {
10166  * STREAM_0_SYNCHRONIZATION enum
10169 typedef enum STREAM_0_SYNCHRONIZATION {
10175  * STREAM_1_SYNCHRONIZATION enum
10178 typedef enum STREAM_1_SYNCHRONIZATION {
10184  * STREAM_2_SYNCHRONIZATION enum
10187 typedef enum STREAM_2_SYNCHRONIZATION {
10193  * STREAM_3_SYNCHRONIZATION enum
10196 typedef enum STREAM_3_SYNCHRONIZATION {
10202  * STREAM_4_SYNCHRONIZATION enum
10205 typedef enum STREAM_4_SYNCHRONIZATION {
10211  * STREAM_5_SYNCHRONIZATION enum
10214 typedef enum STREAM_5_SYNCHRONIZATION {
10220  * STREAM_6_SYNCHRONIZATION enum
10223 typedef enum STREAM_6_SYNCHRONIZATION {
10229  * STREAM_7_SYNCHRONIZATION enum
10232 typedef enum STREAM_7_SYNCHRONIZATION {
10238  * STREAM_8_SYNCHRONIZATION enum
10241 typedef enum STREAM_8_SYNCHRONIZATION {
10247  * STREAM_9_SYNCHRONIZATION enum
10250 typedef enum STREAM_9_SYNCHRONIZATION {
10256  * STREAM_10_SYNCHRONIZATION enum
10259 typedef enum STREAM_10_SYNCHRONIZATION {
10265  * STREAM_11_SYNCHRONIZATION enum
10268 typedef enum STREAM_11_SYNCHRONIZATION {
10274  * STREAM_12_SYNCHRONIZATION enum
10277 typedef enum STREAM_12_SYNCHRONIZATION {
10283  * STREAM_13_SYNCHRONIZATION enum
10286 typedef enum STREAM_13_SYNCHRONIZATION {
10292  * STREAM_14_SYNCHRONIZATION enum
10295 typedef enum STREAM_14_SYNCHRONIZATION {
10301  * STREAM_15_SYNCHRONIZATION enum
10304 typedef enum STREAM_15_SYNCHRONIZATION {
10310  * CORB_READ_POINTER_RESET enum
10313 typedef enum CORB_READ_POINTER_RESET {
10319  * AZ_CORB_SIZE enum
10322 typedef enum AZ_CORB_SIZE {
10330  * AZ_RIRB_WRITE_POINTER_RESET enum
10333 typedef enum AZ_RIRB_WRITE_POINTER_RESET {
10339  * RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL enum
10342 typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
10348  * RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL enum
10351 typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
10357  * AZ_RIRB_SIZE enum
10360 typedef enum AZ_RIRB_SIZE {
10368  * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID enum
10371 typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
10377  * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY enum
10380 typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
10386  * DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE enum
10389 typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
10399  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
10402 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
10408  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
10411 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
10417  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
10420 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
10429  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
10432 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
10444  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
10447 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
10457  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
10460 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
10473  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L enum
10476 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
10482  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO enum
10485 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
10491  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO enum
10494 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
10500  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY enum
10503 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
10509  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE enum
10512 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
10518  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG enum
10521 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
10527  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V enum
10530 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
10536  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
10539 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
10545  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE enum
10548 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
10554  * AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE enum
10557 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
10563  * AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
10566 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
10572  * AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT enum
10575 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
10581  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE enum
10584 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
10590  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE enum
10593 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
10599  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE enum
10602 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
10608  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE enum
10611 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
10617  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
10620 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
10626  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
10629 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
10635  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
10638 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
10644  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
10647 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
10653  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
10656 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
10666  * AZALIA_SOFT_RESET_REFCLK_SOFT_RESET enum
10669 typedef enum AZALIA_SOFT_RESET_REFCLK_SOFT_RESET {
10679  * CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY enum
10682 typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
10694  * CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY enum
10697 typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
10713  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
10716 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
10722  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
10725 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
10731  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
10734 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
10743  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
10746 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
10758  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
10761 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
10771  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
10774 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
10787  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
10790 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
10796  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE enum
10799 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
10805  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
10808 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
10814  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE enum
10817 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
10823  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
10826 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
10832  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE enum
10835 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
10841  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
10844 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
10850  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE enum
10853 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
10859  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
10862 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
10868  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE enum
10871 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
10877  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
10880 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
10890  * AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET enum
10893 typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
10903  * ENABLE enum
10906 typedef enum ENABLE {
10912  * ENABLE_CLOCK enum
10915 typedef enum ENABLE_CLOCK {
10921  * FORCE_VBI enum
10924 typedef enum FORCE_VBI {
10930  * OVERRIDE_CGTT_SCLK enum
10933 typedef enum OVERRIDE_CGTT_SCLK {
10939  * CLEAR_SMU_INTR enum
10942 typedef enum CLEAR_SMU_INTR {
10948  * STATIC_SCREEN_SMU_INTR enum
10951 typedef enum STATIC_SCREEN_SMU_INTR {
10957  * JITTER_REMOVE_DISABLE enum
10960 typedef enum JITTER_REMOVE_DISABLE {
10966  * DS_REF_SRC enum
10969 typedef enum DS_REF_SRC {
10976  * DISABLE_CLOCK_GATING enum
10979 typedef enum DISABLE_CLOCK_GATING {
10985  * DISABLE_CLOCK_GATING_IN_DCO enum
10988 typedef enum DISABLE_CLOCK_GATING_IN_DCO {
10994  * DCCG_DEEP_COLOR_CNTL enum
10997 typedef enum DCCG_DEEP_COLOR_CNTL {
11005  * REFCLK_CLOCK_EN enum
11008 typedef enum REFCLK_CLOCK_EN {
11014  * REFCLK_SRC_SEL enum
11017 typedef enum REFCLK_SRC_SEL {
11023  * DPREFCLK_SRC_SEL enum
11026 typedef enum DPREFCLK_SRC_SEL {
11035  * XTAL_REF_SEL enum
11038 typedef enum XTAL_REF_SEL {
11044  * XTAL_REF_CLOCK_SOURCE_SEL enum
11047 typedef enum XTAL_REF_CLOCK_SOURCE_SEL {
11053  * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
11056 typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL {
11062  * ALLOW_SR_ON_TRANS_REQ enum
11065 typedef enum ALLOW_SR_ON_TRANS_REQ {
11071  * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
11074 typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL {
11080  * PIPE_PIXEL_RATE_SOURCE enum
11083 typedef enum PIPE_PIXEL_RATE_SOURCE {
11090  * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum
11093 typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE {
11104  * PIPE_PIXEL_RATE_PLL_SOURCE enum
11107 typedef enum PIPE_PIXEL_RATE_PLL_SOURCE {
11113  * DP_DTO_DS_DISABLE enum
11116 typedef enum DP_DTO_DS_DISABLE {
11122  * CRTC_ADD_PIXEL enum
11125 typedef enum CRTC_ADD_PIXEL {
11131  * CRTC_DROP_PIXEL enum
11134 typedef enum CRTC_DROP_PIXEL {
11140  * SYMCLK_FE_FORCE_EN enum
11143 typedef enum SYMCLK_FE_FORCE_EN {
11149  * SYMCLK_FE_FORCE_SRC enum
11152 typedef enum SYMCLK_FE_FORCE_SRC {
11163  * DPDBG_CLK_FORCE_EN enum
11166 typedef enum DPDBG_CLK_FORCE_EN {
11172  * DVOACLK_COARSE_SKEW_CNTL enum
11175 typedef enum DVOACLK_COARSE_SKEW_CNTL {
11210  * DVOACLK_FINE_SKEW_CNTL enum
11213 typedef enum DVOACLK_FINE_SKEW_CNTL {
11225  * DVOACLKD_IN_PHASE enum
11228 typedef enum DVOACLKD_IN_PHASE {
11234  * DVOACLKC_IN_PHASE enum
11237 typedef enum DVOACLKC_IN_PHASE {
11243  * DVOACLKC_MVP_IN_PHASE enum
11246 typedef enum DVOACLKC_MVP_IN_PHASE {
11252  * DVOACLKC_MVP_SKEW_PHASE_OVERRIDE enum
11255 typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE {
11261  * MVP_CLK_SRC_SEL enum
11264 typedef enum MVP_CLK_SRC_SEL {
11272  * DCCG_AUDIO_DTO0_SOURCE_SEL enum
11275 typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL {
11286  * DCCG_AUDIO_DTO_SEL enum
11289 typedef enum DCCG_AUDIO_DTO_SEL {
11296  * DCCG_AUDIO_DTO2_SOURCE_SEL enum
11299 typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL {
11305  * DCCG_AUDIO_DTO_USE_512FBR_DTO enum
11308 typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO {
11314  * DCCG_DBG_EN enum
11317 typedef enum DCCG_DBG_EN {
11323  * DCCG_DBG_BLOCK_SEL enum
11326 typedef enum DCCG_DBG_BLOCK_SEL {
11333  * DISPCLK_FREQ_RAMP_DONE enum
11336 typedef enum DISPCLK_FREQ_RAMP_DONE {
11342  * DCCG_FIFO_ERRDET_RESET enum
11345 typedef enum DCCG_FIFO_ERRDET_RESET {
11351  * DCCG_FIFO_ERRDET_STATE enum
11354 typedef enum DCCG_FIFO_ERRDET_STATE {
11360  * DCCG_FIFO_ERRDET_OVR_EN enum
11363 typedef enum DCCG_FIFO_ERRDET_OVR_EN {
11369  * DISPCLK_CHG_FWD_CORR_DISABLE enum
11372 typedef enum DISPCLK_CHG_FWD_CORR_DISABLE {
11378  * DC_MEM_GLOBAL_PWR_REQ_DIS enum
11381 typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS {
11387  * DCCG_PERF_RUN enum
11390 typedef enum DCCG_PERF_RUN {
11396  * DCCG_PERF_MODE_VSYNC enum
11399 typedef enum DCCG_PERF_MODE_VSYNC {
11405  * DCCG_PERF_MODE_HSYNC enum
11408 typedef enum DCCG_PERF_MODE_HSYNC {
11414  * DCCG_PERF_CRTC_SELECT enum
11417 typedef enum DCCG_PERF_CRTC_SELECT {
11427  * CLOCK_BRANCH_SOFT_RESET enum
11430 typedef enum CLOCK_BRANCH_SOFT_RESET {
11436  * PLL_CFG_IF_SOFT_RESET enum
11439 typedef enum PLL_CFG_IF_SOFT_RESET {
11445  * DVO_ENABLE_RST enum
11448 typedef enum DVO_ENABLE_RST {
11458  * LptNumPipes enum
11461 typedef enum LptNumPipes {
11469  * LptNumBanks enum
11472 typedef enum LptNumBanks {
11481  * OVERRIDE_CGTT_DCEFCLK enum
11484 typedef enum OVERRIDE_CGTT_DCEFCLK {
11494  * DCIO_DC_GENERICA_SEL enum
11497 typedef enum DCIO_DC_GENERICA_SEL {
11519  * DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL enum
11522 typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
11535  * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL enum
11538 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
11551  * DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL enum
11554 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
11567  * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL enum
11570 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
11583  * DCIO_DC_GENERICB_SEL enum
11586 typedef enum DCIO_DC_GENERICB_SEL {
11606  * DCIO_DC_PAD_EXTERN_SIG_SEL enum
11609 typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL {
11629  * DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS enum
11632 typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS {
11640  * DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL enum
11643 typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
11651  * DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL enum
11654 typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
11662  * DCIO_DC_GPIO_VIP_DEBUG enum
11665 typedef enum DCIO_DC_GPIO_VIP_DEBUG {
11671  * DCIO_DC_GPIO_MACRO_DEBUG enum
11674 typedef enum DCIO_DC_GPIO_MACRO_DEBUG {
11682  * DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL enum
11685 typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL {
11691  * DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN enum
11694 typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN {
11700  * DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE enum
11703 typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
11709  * DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION enum
11712 typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
11724  * DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT enum
11727 typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
11733  * DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK enum
11736 typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
11744  * DCIO_UNIPHY_CHANNEL_XBAR_SOURCE enum
11747 typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
11755  * DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN enum
11758 typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
11764  * DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN enum
11767 typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
11773  * DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN enum
11776 typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
11782  * DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN enum
11785 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
11791  * DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE enum
11794 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
11800  * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL enum
11803 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
11809  * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON enum
11812 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
11818  * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL enum
11821 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
11827  * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON enum
11830 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
11836  * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL enum
11839 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
11845  * DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN enum
11848 typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
11854  * DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN enum
11857 typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
11863  * DCIO_BL_PWM_CNTL_BL_PWM_EN enum
11866 typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
11872  * DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT enum
11875 typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
11883  * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE enum
11886 typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
11892  * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN enum
11895 typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
11901  * DCIO_BL_PWM_GRP1_REG_LOCK enum
11904 typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
11910  * DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START enum
11913 typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
11919  * DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL enum
11922 typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
11932  * DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN enum
11935 typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
11941  * DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN enum
11944 typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
11950  * DCIO_GSL_SEL enum
11953 typedef enum DCIO_GSL_SEL {
11960  * DCIO_GENLK_CLK_GSL_MASK enum
11963 typedef enum DCIO_GENLK_CLK_GSL_MASK {
11970  * DCIO_GENLK_VSYNC_GSL_MASK enum
11973 typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
11980  * DCIO_SWAPLOCK_A_GSL_MASK enum
11983 typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
11990  * DCIO_SWAPLOCK_B_GSL_MASK enum
11993 typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
12000  * DCIO_GSL_VSYNC_SEL enum
12003 typedef enum DCIO_GSL_VSYNC_SEL {
12013  * DCIO_GSL0_TIMING_SYNC_SEL enum
12016 typedef enum DCIO_GSL0_TIMING_SYNC_SEL {
12025  * DCIO_GSL0_GLOBAL_UNLOCK_SEL enum
12028 typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL {
12037  * DCIO_GSL1_TIMING_SYNC_SEL enum
12040 typedef enum DCIO_GSL1_TIMING_SYNC_SEL {
12049  * DCIO_GSL1_GLOBAL_UNLOCK_SEL enum
12052 typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL {
12061  * DCIO_GSL2_TIMING_SYNC_SEL enum
12064 typedef enum DCIO_GSL2_TIMING_SYNC_SEL {
12073  * DCIO_GSL2_GLOBAL_UNLOCK_SEL enum
12076 typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL {
12085  * DCIO_DC_GPU_TIMER_START_POSITION enum
12088 typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
12100  * DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL enum
12103 typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
12110  * DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS enum
12113 typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
12119  * DCIO_DCO_DCFE_EXT_VSYNC_MUX enum
12122 typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX {
12134  * DCIO_DCO_EXT_VSYNC_MASK enum
12137 typedef enum DCIO_DCO_EXT_VSYNC_MASK {
12149  * DCIO_DSYNC_SOFT_RESET enum
12152 typedef enum DCIO_DSYNC_SOFT_RESET {
12158  * DCIO_DACA_SOFT_RESET enum
12161 typedef enum DCIO_DACA_SOFT_RESET {
12167  * DCIO_DCRXPHY_SOFT_RESET enum
12170 typedef enum DCIO_DCRXPHY_SOFT_RESET {
12176  * DCIO_DPHY_LANE_SEL enum
12179 typedef enum DCIO_DPHY_LANE_SEL {
12187  * DCIO_DPCS_INTERRUPT_TYPE enum
12190 typedef enum DCIO_DPCS_INTERRUPT_TYPE {
12196  * DCIO_DPCS_INTERRUPT_MASK enum
12199 typedef enum DCIO_DPCS_INTERRUPT_MASK {
12205  * DCIO_DC_GPU_TIMER_READ_SELECT enum
12208 typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
12248  * DCIO_IMPCAL_STEP_DELAY enum
12251 typedef enum DCIO_IMPCAL_STEP_DELAY {
12271  * DCIO_UNIPHY_IMPCAL_SEL enum
12274 typedef enum DCIO_UNIPHY_IMPCAL_SEL {
12280  * DCIO_DBG_ASYNC_BLOCK_SEL enum
12283 typedef enum DCIO_DBG_ASYNC_BLOCK_SEL {
12291  * DCIO_DBG_ASYNC_4BIT_SEL enum
12294 typedef enum DCIO_DBG_ASYNC_4BIT_SEL {
12310  * AOUT_EN enum
12313 typedef enum AOUT_EN {
12319  * AOUT_FIFO_START_ADDR enum
12322 typedef enum AOUT_FIFO_START_ADDR {
12328  * AOUT_CRC_TEST_EN enum
12331 typedef enum AOUT_CRC_TEST_EN {
12337  * AOUT_CRC_SOFT_RESET enum
12340 typedef enum AOUT_CRC_SOFT_RESET {
12346  * AOUT_CRC_CONT_EN enum
12349 typedef enum AOUT_CRC_CONT_EN {
12355  * I2S_WORD_SIZE enum
12358 typedef enum I2S_WORD_SIZE {
12364  * I2S_SAMPLE_ALIGNMENT enum
12367 typedef enum I2S_SAMPLE_ALIGNMENT {
12373  * I2S_SAMPLE_BIT_ORDER enum
12376 typedef enum I2S_SAMPLE_BIT_ORDER {
12382  * I2S_LRCLK_POLARITY enum
12385 typedef enum I2S_LRCLK_POLARITY {
12391  * I2S_WORD_ALIGNMENT enum
12394 typedef enum I2S_WORD_ALIGNMENT {
12400  * SPDIF_INVERT_EN enum
12403 typedef enum SPDIF_INVERT_EN {
12413  * DPDBG_EN enum
12416 typedef enum DPDBG_EN {
12422  * DPDBG_INPUT_EN enum
12425 typedef enum DPDBG_INPUT_EN {
12431  * DPDBG_ERROR_DETECTION_MODE enum
12434 typedef enum DPDBG_ERROR_DETECTION_MODE {
12440  * DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK enum
12443 typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK {
12449  * DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE enum
12452 typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE {
12458  * DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK enum
12461 typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK {
12467  * PM_ASSERT_RESET enum
12470 typedef enum PM_ASSERT_RESET {
12476  * DAC_MUX_SELECT enum
12479 typedef enum DAC_MUX_SELECT {
12485  * TMDS_DVO_MUX_SELECT enum
12488 typedef enum TMDS_DVO_MUX_SELECT {
12496  * DACA_SOFT_RESET enum
12499 typedef enum DACA_SOFT_RESET {
12505  * I2S0_SPDIF0_SOFT_RESET enum
12508 typedef enum I2S0_SPDIF0_SOFT_RESET {
12514  * I2S1_SOFT_RESET enum
12517 typedef enum I2S1_SOFT_RESET {
12523  * SPDIF1_SOFT_RESET enum
12526 typedef enum SPDIF1_SOFT_RESET {
12532  * DB_CLK_SOFT_RESET enum
12535 typedef enum DB_CLK_SOFT_RESET {
12541  * FMT0_SOFT_RESET enum
12544 typedef enum FMT0_SOFT_RESET {
12550  * FMT1_SOFT_RESET enum
12553 typedef enum FMT1_SOFT_RESET {
12559  * FMT2_SOFT_RESET enum
12562 typedef enum FMT2_SOFT_RESET {
12568  * FMT3_SOFT_RESET enum
12571 typedef enum FMT3_SOFT_RESET {
12577  * FMT4_SOFT_RESET enum
12580 typedef enum FMT4_SOFT_RESET {
12586  * FMT5_SOFT_RESET enum
12589 typedef enum FMT5_SOFT_RESET {
12595  * MVP_SOFT_RESET enum
12598 typedef enum MVP_SOFT_RESET {
12604  * ABM_SOFT_RESET enum
12607 typedef enum ABM_SOFT_RESET {
12613  * DVO_SOFT_RESET enum
12616 typedef enum DVO_SOFT_RESET {
12622  * DIGA_FE_SOFT_RESET enum
12625 typedef enum DIGA_FE_SOFT_RESET {
12631  * DIGA_BE_SOFT_RESET enum
12634 typedef enum DIGA_BE_SOFT_RESET {
12640  * DIGB_FE_SOFT_RESET enum
12643 typedef enum DIGB_FE_SOFT_RESET {
12649  * DIGB_BE_SOFT_RESET enum
12652 typedef enum DIGB_BE_SOFT_RESET {
12658  * DIGC_FE_SOFT_RESET enum
12661 typedef enum DIGC_FE_SOFT_RESET {
12667  * DIGC_BE_SOFT_RESET enum
12670 typedef enum DIGC_BE_SOFT_RESET {
12676  * DIGD_FE_SOFT_RESET enum
12679 typedef enum DIGD_FE_SOFT_RESET {
12685  * DIGD_BE_SOFT_RESET enum
12688 typedef enum DIGD_BE_SOFT_RESET {
12694  * DIGE_FE_SOFT_RESET enum
12697 typedef enum DIGE_FE_SOFT_RESET {
12703  * DIGE_BE_SOFT_RESET enum
12706 typedef enum DIGE_BE_SOFT_RESET {
12712  * DIGF_FE_SOFT_RESET enum
12715 typedef enum DIGF_FE_SOFT_RESET {
12721  * DIGF_BE_SOFT_RESET enum
12724 typedef enum DIGF_BE_SOFT_RESET {
12730  * DIGG_FE_SOFT_RESET enum
12733 typedef enum DIGG_FE_SOFT_RESET {
12739  * DIGG_BE_SOFT_RESET enum
12742 typedef enum DIGG_BE_SOFT_RESET {
12748  * DPDBG_SOFT_RESET enum
12751 typedef enum DPDBG_SOFT_RESET {
12757  * DIGLPA_FE_SOFT_RESET enum
12760 typedef enum DIGLPA_FE_SOFT_RESET {
12766  * DIGLPA_BE_SOFT_RESET enum
12769 typedef enum DIGLPA_BE_SOFT_RESET {
12775  * DIGLPB_FE_SOFT_RESET enum
12778 typedef enum DIGLPB_FE_SOFT_RESET {
12784  * DIGLPB_BE_SOFT_RESET enum
12787 typedef enum DIGLPB_BE_SOFT_RESET {
12793  * GENERICA_STEREOSYNC_SEL enum
12796 typedef enum GENERICA_STEREOSYNC_SEL {
12807  * GENERICB_STEREOSYNC_SEL enum
12810 typedef enum GENERICB_STEREOSYNC_SEL {
12821  * DCO_DBG_BLOCK_SEL enum
12824 typedef enum DCO_DBG_BLOCK_SEL {
12883  * DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE enum
12886 typedef enum DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE {
12892  * FMT420_MEMORY_SOURCE_SEL enum
12895 typedef enum FMT420_MEMORY_SOURCE_SEL {
12910  * DOUT_I2C_CONTROL_GO enum
12913 typedef enum DOUT_I2C_CONTROL_GO {
12919  * DOUT_I2C_CONTROL_SOFT_RESET enum
12922 typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
12928  * DOUT_I2C_CONTROL_SEND_RESET enum
12931 typedef enum DOUT_I2C_CONTROL_SEND_RESET {
12937  * DOUT_I2C_CONTROL_SW_STATUS_RESET enum
12940 typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
12946  * DOUT_I2C_CONTROL_DDC_SELECT enum
12949 typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
12960  * DOUT_I2C_CONTROL_TRANSACTION_COUNT enum
12963 typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
12971  * DOUT_I2C_CONTROL_DBG_REF_SEL enum
12974 typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL {
12980  * DOUT_I2C_ARBITRATION_SW_PRIORITY enum
12983 typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
12991  * DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO enum
12994 typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
13000  * DOUT_I2C_ARBITRATION_ABORT_XFER enum
13003 typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
13009  * DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ enum
13012 typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
13018  * DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG enum
13021 typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
13027  * DOUT_I2C_ACK enum
13030 typedef enum DOUT_I2C_ACK {
13036  * DOUT_I2C_DDC_SPEED_THRESHOLD enum
13039 typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
13047  * DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN enum
13050 typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
13056  * DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL enum
13059 typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
13065  * DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE enum
13068 typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
13074  * DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN enum
13077 typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
13083  * DOUT_I2C_TRANSACTION_STOP_ON_NACK enum
13086 typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
13092  * DOUT_I2C_DATA_INDEX_WRITE enum
13095 typedef enum DOUT_I2C_DATA_INDEX_WRITE {
13101  * DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET enum
13104 typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
13110  * DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE enum
13113 typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
13123  * FBC_IDLE_MASK_MASK_BITS enum
13126 typedef enum FBC_IDLE_MASK_MASK_BITS {
13166  * DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL enum
13169 typedef enum DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL {
13177  * DPCSRX_DBG_CFGCLK_SEL enum
13180 typedef enum DPCSRX_DBG_CFGCLK_SEL {
13188  * DPCSRX_RX_SYMCLK_SEL enum
13191 typedef enum DPCSRX_RX_SYMCLK_SEL {
13202  * DPCSTX_DBG_CFGCLK_SEL enum
13205 typedef enum DPCSTX_DBG_CFGCLK_SEL {
13213  * DPCSTX_TX_SYMCLK_SEL enum
13216 typedef enum DPCSTX_TX_SYMCLK_SEL {
13223  * DPCSTX_TX_SYMCLK_DIV2_SEL enum
13226 typedef enum DPCSTX_TX_SYMCLK_DIV2_SEL {
13240  * SurfaceNumber enum
13243 typedef enum SurfaceNumber {
13255  * SurfaceSwap enum
13258 typedef enum SurfaceSwap {
13266  * CBMode enum
13269 typedef enum CBMode {
13280  * RoundMode enum
13283 typedef enum RoundMode {
13289  * SourceFormat enum
13292 typedef enum SourceFormat {
13300  * BlendOp enum
13303 typedef enum BlendOp {
13328  * CombFunc enum
13331 typedef enum CombFunc {
13340  * BlendOpt enum
13343 typedef enum BlendOpt {
13355  * CmaskCode enum
13358 typedef enum CmaskCode {
13378  * CmaskAddr enum
13381 typedef enum CmaskAddr {
13388  * MemArbMode enum
13391 typedef enum MemArbMode {
13399  * CBPerfSel enum
13402 typedef enum CBPerfSel {
13811  * CBPerfOpFilterSel enum
13814 typedef enum CBPerfOpFilterSel {
13824  * CBPerfClearFilterSel enum
13827 typedef enum CBPerfClearFilterSel {
13837  * TC_OP_MASKS enum
13840 typedef enum TC_OP_MASKS {
13847  * TC_OP enum
13850 typedef enum TC_OP {
13982  * TC_CHUB_REQ_CREDITS_ENUM enum
13985 typedef enum TC_CHUB_REQ_CREDITS_ENUM {
13990  * CHUB_TC_RET_CREDITS_ENUM enum
13993 typedef enum CHUB_TC_RET_CREDITS_ENUM {
13998  * TC_NACKS enum
14001 typedef enum TC_NACKS {
14009  * TC_EA_CID enum
14012 typedef enum TC_EA_CID {
14036  * SPI_SAMPLE_CNTL enum
14039 typedef enum SPI_SAMPLE_CNTL {
14047  * SPI_FOG_MODE enum
14050 typedef enum SPI_FOG_MODE {
14058  * SPI_PNT_SPRITE_OVERRIDE enum
14061 typedef enum SPI_PNT_SPRITE_OVERRIDE {
14070  * SPI_PERFCNT_SEL enum
14073 typedef enum SPI_PERFCNT_SEL {
14274  * SPI_SHADER_FORMAT enum
14277 typedef enum SPI_SHADER_FORMAT {
14286  * SPI_SHADER_EX_FORMAT enum
14289 typedef enum SPI_SHADER_EX_FORMAT {
14303  * CLKGATE_SM_MODE enum
14306 typedef enum CLKGATE_SM_MODE {
14315  * CLKGATE_BASE_MODE enum
14318 typedef enum CLKGATE_BASE_MODE {
14328  * SQ_TEX_CLAMP enum
14331 typedef enum SQ_TEX_CLAMP {
14343  * SQ_TEX_XY_FILTER enum
14346 typedef enum SQ_TEX_XY_FILTER {
14354  * SQ_TEX_Z_FILTER enum
14357 typedef enum SQ_TEX_Z_FILTER {
14364  * SQ_TEX_MIP_FILTER enum
14367 typedef enum SQ_TEX_MIP_FILTER {
14375  * SQ_TEX_ANISO_RATIO enum
14378 typedef enum SQ_TEX_ANISO_RATIO {
14387  * SQ_TEX_DEPTH_COMPARE enum
14390 typedef enum SQ_TEX_DEPTH_COMPARE {
14402  * SQ_TEX_BORDER_COLOR enum
14405 typedef enum SQ_TEX_BORDER_COLOR {
14413  * SQ_RSRC_BUF_TYPE enum
14416 typedef enum SQ_RSRC_BUF_TYPE {
14424  * SQ_RSRC_IMG_TYPE enum
14427 typedef enum SQ_RSRC_IMG_TYPE {
14447  * SQ_RSRC_FLAT_TYPE enum
14450 typedef enum SQ_RSRC_FLAT_TYPE {
14458  * SQ_IMG_FILTER_TYPE enum
14461 typedef enum SQ_IMG_FILTER_TYPE {
14468  * SQ_SEL_XYZW01 enum
14471 typedef enum SQ_SEL_XYZW01 {
14483  * SQ_WAVE_TYPE enum
14486 typedef enum SQ_WAVE_TYPE {
14498  * SQ_THREAD_TRACE_TOKEN_TYPE enum
14501 typedef enum SQ_THREAD_TRACE_TOKEN_TYPE {
14521  * SQ_THREAD_TRACE_MISC_TOKEN_TYPE enum
14524 typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE {
14536  * SQ_THREAD_TRACE_INST_TYPE enum
14539 typedef enum SQ_THREAD_TRACE_INST_TYPE {
14569  * SQ_THREAD_TRACE_REG_TYPE enum
14572 typedef enum SQ_THREAD_TRACE_REG_TYPE {
14584  * SQ_THREAD_TRACE_REG_OP enum
14587 typedef enum SQ_THREAD_TRACE_REG_OP {
14593  * SQ_THREAD_TRACE_MODE_SEL enum
14596 typedef enum SQ_THREAD_TRACE_MODE_SEL {
14602  * SQ_THREAD_TRACE_CAPTURE_MODE enum
14605 typedef enum SQ_THREAD_TRACE_CAPTURE_MODE {
14612  * SQ_THREAD_TRACE_VM_ID_MASK enum
14615 typedef enum SQ_THREAD_TRACE_VM_ID_MASK {
14622  * SQ_THREAD_TRACE_WAVE_MASK enum
14625 typedef enum SQ_THREAD_TRACE_WAVE_MASK {
14631  * SQ_THREAD_TRACE_ISSUE enum
14634 typedef enum SQ_THREAD_TRACE_ISSUE {
14642  * SQ_THREAD_TRACE_ISSUE_MASK enum
14645 typedef enum SQ_THREAD_TRACE_ISSUE_MASK {
14653  * SQ_PERF_SEL enum
14656 typedef enum SQ_PERF_SEL {
14957  * SQ_CAC_POWER_SEL enum
14960 typedef enum SQ_CAC_POWER_SEL {
14973  * SQ_IND_CMD_CMD enum
14976 typedef enum SQ_IND_CMD_CMD {
14988  * SQ_IND_CMD_MODE enum
14991 typedef enum SQ_IND_CMD_MODE {
15000  * SQ_EDC_INFO_SOURCE enum
15003 typedef enum SQ_EDC_INFO_SOURCE {
15014  * SQ_ROUND_MODE enum
15017 typedef enum SQ_ROUND_MODE {
15025  * SQ_INTERRUPT_WORD_ENCODING enum
15028 typedef enum SQ_INTERRUPT_WORD_ENCODING {
15035  * ENUM_SQ_EXPORT_RAT_INST enum
15038 typedef enum ENUM_SQ_EXPORT_RAT_INST {
15084  * SQ_IBUF_ST enum
15087 typedef enum SQ_IBUF_ST {
15099  * SQ_INST_STR_ST enum
15102 typedef enum SQ_INST_STR_ST {
15114  * SQ_WAVE_IB_ECC_ST enum
15117 typedef enum SQ_WAVE_IB_ECC_ST {
15125  * SH_MEM_ADDRESS_MODE enum
15128 typedef enum SH_MEM_ADDRESS_MODE {
15134  * SH_MEM_ALIGNMENT_MODE enum
15137 typedef enum SH_MEM_ALIGNMENT_MODE {
15145  * SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX enum
15148 typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX {
15154  * SQ_LB_CTR_SEL_VALUES enum
15157 typedef enum SQ_LB_CTR_SEL_VALUES {
15328  * CSDATA_TYPE enum
15331 typedef enum CSDATA_TYPE {
15361  * VGT_OUT_PRIM_TYPE enum
15364 typedef enum VGT_OUT_PRIM_TYPE {
15383  * VGT_DI_PRIM_TYPE enum
15386 typedef enum VGT_DI_PRIM_TYPE {
15412  * VGT_DI_SOURCE_SELECT enum
15415 typedef enum VGT_DI_SOURCE_SELECT {
15423  * VGT_DI_MAJOR_MODE_SELECT enum
15426 typedef enum VGT_DI_MAJOR_MODE_SELECT {
15432  * VGT_DI_INDEX_SIZE enum
15435 typedef enum VGT_DI_INDEX_SIZE {
15442  * VGT_EVENT_TYPE enum
15445 typedef enum VGT_EVENT_TYPE {
15513  * VGT_DMA_SWAP_MODE enum
15516 typedef enum VGT_DMA_SWAP_MODE {
15524  * VGT_INDEX_TYPE_MODE enum
15527 typedef enum VGT_INDEX_TYPE_MODE {
15534  * VGT_DMA_BUF_TYPE enum
15537 typedef enum VGT_DMA_BUF_TYPE {
15545  * VGT_OUTPATH_SELECT enum
15548 typedef enum VGT_OUTPATH_SELECT {
15558  * VGT_GRP_PRIM_TYPE enum
15561 typedef enum VGT_GRP_PRIM_TYPE {
15584  * VGT_GRP_PRIM_ORDER enum
15587 typedef enum VGT_GRP_PRIM_ORDER {
15596  * VGT_GROUP_CONV_SEL enum
15599 typedef enum VGT_GROUP_CONV_SEL {
15612  * VGT_GS_MODE_TYPE enum
15615 typedef enum VGT_GS_MODE_TYPE {
15625  * VGT_GS_CUT_MODE enum
15628 typedef enum VGT_GS_CUT_MODE {
15636  * VGT_GS_OUTPRIM_TYPE enum
15639 typedef enum VGT_GS_OUTPRIM_TYPE {
15647  * VGT_CACHE_INVALID_MODE enum
15650 typedef enum VGT_CACHE_INVALID_MODE {
15657  * VGT_TESS_TYPE enum
15660 typedef enum VGT_TESS_TYPE {
15667  * VGT_TESS_PARTITION enum
15670 typedef enum VGT_TESS_PARTITION {
15678  * VGT_TESS_TOPOLOGY enum
15681 typedef enum VGT_TESS_TOPOLOGY {
15689  * VGT_RDREQ_POLICY enum
15692 typedef enum VGT_RDREQ_POLICY {
15698  * VGT_DIST_MODE enum
15701 typedef enum VGT_DIST_MODE {
15709  * VGT_STAGES_LS_EN enum
15712 typedef enum VGT_STAGES_LS_EN {
15720  * VGT_STAGES_HS_EN enum
15723 typedef enum VGT_STAGES_HS_EN {
15729  * VGT_STAGES_ES_EN enum
15732 typedef enum VGT_STAGES_ES_EN {
15740  * VGT_STAGES_GS_EN enum
15743 typedef enum VGT_STAGES_GS_EN {
15749  * VGT_STAGES_VS_EN enum
15752 typedef enum VGT_STAGES_VS_EN {
15760  * VGT_PERFCOUNT_SELECT enum
15763 typedef enum VGT_PERFCOUNT_SELECT {
15914  * IA_PERFCOUNT_SELECT enum
15917 typedef enum IA_PERFCOUNT_SELECT {
15945  * WD_PERFCOUNT_SELECT enum
15948 typedef enum WD_PERFCOUNT_SELECT {
15989  * WD_IA_DRAW_TYPE enum
15992 typedef enum WD_IA_DRAW_TYPE {
16004  * WD_IA_DRAW_REG_XFER enum
16007 typedef enum WD_IA_DRAW_REG_XFER {
16013  * WD_IA_DRAW_SOURCE enum
16016 typedef enum WD_IA_DRAW_SOURCE {
16034  * GB_EDC_DED_MODE enum
16037 typedef enum GB_EDC_DED_MODE {
16060  * TA_TC_ADDR_MODES enum
16063 typedef enum TA_TC_ADDR_MODES {
16074  * TA_PERFCOUNT_SEL enum
16077 typedef enum TA_PERFCOUNT_SEL {
16200  * TD_PERFCOUNT_SEL enum
16203 typedef enum TD_PERFCOUNT_SEL {
16264  * TCP_PERFCOUNT_SELECT enum
16267 typedef enum TCP_PERFCOUNT_SELECT {
16467  * TCP_CACHE_POLICIES enum
16470 typedef enum TCP_CACHE_POLICIES {
16478  * TCP_CACHE_STORE_POLICIES enum
16481 typedef enum TCP_CACHE_STORE_POLICIES {
16487  * TCP_WATCH_MODES enum
16490 typedef enum TCP_WATCH_MODES {
16498  * TCP_DSM_DATA_SEL enum
16501 typedef enum TCP_DSM_DATA_SEL {
16509  * TCP_DSM_SINGLE_WRITE enum
16512 typedef enum TCP_DSM_SINGLE_WRITE {
16518  * TCP_DSM_INJECT_SEL enum
16521 typedef enum TCP_DSM_INJECT_SEL {
16533  * TCC_PERF_SEL enum
16536 typedef enum TCC_PERF_SEL {
16780  * TCA_PERF_SEL enum
16783 typedef enum TCA_PERF_SEL {
16826  * GRBM_PERF_SEL enum
16829 typedef enum GRBM_PERF_SEL {
16871  * GRBM_SE0_PERF_SEL enum
16874 typedef enum GRBM_SE0_PERF_SEL {
16894  * GRBM_SE1_PERF_SEL enum
16897 typedef enum GRBM_SE1_PERF_SEL {
16917  * GRBM_SE2_PERF_SEL enum
16920 typedef enum GRBM_SE2_PERF_SEL {
16940  * GRBM_SE3_PERF_SEL enum
16943 typedef enum GRBM_SE3_PERF_SEL {
16967  * CP_RING_ID enum
16970 typedef enum CP_RING_ID {
16978  * CP_PIPE_ID enum
16981 typedef enum CP_PIPE_ID {
16989  * CP_ME_ID enum
16992 typedef enum CP_ME_ID {
17000  * SPM_PERFMON_STATE enum
17003 typedef enum SPM_PERFMON_STATE {
17013  * CP_PERFMON_STATE enum
17016 typedef enum CP_PERFMON_STATE {
17026  * CP_PERFMON_ENABLE_MODE enum
17029 typedef enum CP_PERFMON_ENABLE_MODE {
17037  * CPG_PERFCOUNT_SEL enum
17040 typedef enum CPG_PERFCOUNT_SEL {
17093  * CPF_PERFCOUNT_SEL enum
17096 typedef enum CPF_PERFCOUNT_SEL {
17121  * CPC_PERFCOUNT_SEL enum
17124 typedef enum CPC_PERFCOUNT_SEL {
17153  * CP_ALPHA_TAG_RAM_SEL enum
17156 typedef enum CP_ALPHA_TAG_RAM_SEL {
19463  * SX_BLEND_OPT enum
19466 typedef enum SX_BLEND_OPT {
19478  * SX_OPT_COMB_FCN enum
19481 typedef enum SX_OPT_COMB_FCN {
19493  * SX_DOWNCONVERT_FORMAT enum
19496 typedef enum SX_DOWNCONVERT_FORMAT {
19511  * SX_PERFCOUNTER_VALS enum
19514 typedef enum SX_PERFCOUNTER_VALS {
19720  * ForceControl enum
19723 typedef enum ForceControl {
19731  * ZSamplePosition enum
19734 typedef enum ZSamplePosition {
19740  * ZOrder enum
19743 typedef enum ZOrder {
19751  * ZpassControl enum
19754 typedef enum ZpassControl {
19761  * ZModeForce enum
19764 typedef enum ZModeForce {
19772  * ZLimitSumm enum
19775 typedef enum ZLimitSumm {
19783  * CompareFrag enum
19786 typedef enum CompareFrag {
19798  * StencilOp enum
19801 typedef enum StencilOp {
19821  * ConservativeZExport enum
19824 typedef enum ConservativeZExport {
19832  * DbPSLControl enum
19835 typedef enum DbPSLControl {
19843  * DbPRTFaultBehavior enum
19846 typedef enum DbPRTFaultBehavior {
19854  * PerfCounter_Vals enum
19857 typedef enum PerfCounter_Vals {
20150  * RingCounterControl enum
20153 typedef enum RingCounterControl {
20160  * DbMemArbWatermarks enum
20163 typedef enum DbMemArbWatermarks {
20175  * DFSMFlushEvents enum
20178 typedef enum DFSMFlushEvents {
20188  * PixelPipeCounterId enum
20191 typedef enum PixelPipeCounterId {
20203  * PixelPipeStride enum
20206 typedef enum PixelPipeStride {
20218  * TEX_BORDER_COLOR_TYPE enum
20221 typedef enum TEX_BORDER_COLOR_TYPE {
20229  * TEX_CHROMA_KEY enum
20232 typedef enum TEX_CHROMA_KEY {
20240  * TEX_CLAMP enum
20243 typedef enum TEX_CLAMP {
20255  * TEX_COORD_TYPE enum
20258 typedef enum TEX_COORD_TYPE {
20264  * TEX_DEPTH_COMPARE_FUNCTION enum
20267 typedef enum TEX_DEPTH_COMPARE_FUNCTION {
20279  * TEX_DIM enum
20282 typedef enum TEX_DIM {
20294  * TEX_FORMAT_COMP enum
20297 typedef enum TEX_FORMAT_COMP {
20305  * TEX_MAX_ANISO_RATIO enum
20308 typedef enum TEX_MAX_ANISO_RATIO {
20320  * TEX_MIP_FILTER enum
20323 typedef enum TEX_MIP_FILTER {
20331  * TEX_REQUEST_SIZE enum
20334 typedef enum TEX_REQUEST_SIZE {
20342  * TEX_SAMPLER_TYPE enum
20345 typedef enum TEX_SAMPLER_TYPE {
20351  * TEX_XY_FILTER enum
20354 typedef enum TEX_XY_FILTER {
20362  * TEX_Z_FILTER enum
20365 typedef enum TEX_Z_FILTER {
20373  * VTX_CLAMP enum
20376 typedef enum VTX_CLAMP {
20382  * VTX_FETCH_TYPE enum
20385 typedef enum VTX_FETCH_TYPE {
20393  * VTX_FORMAT_COMP_ALL enum
20396 typedef enum VTX_FORMAT_COMP_ALL {
20402  * VTX_MEM_REQUEST_SIZE enum
20405 typedef enum VTX_MEM_REQUEST_SIZE {
20411  * TVX_DATA_FORMAT enum
20414 typedef enum TVX_DATA_FORMAT {
20482  * TVX_DST_SEL enum
20485 typedef enum TVX_DST_SEL {
20497  * TVX_ENDIAN_SWAP enum
20500 typedef enum TVX_ENDIAN_SWAP {
20508  * TVX_INST enum
20511 typedef enum TVX_INST {
20547  * TVX_NUM_FORMAT_ALL enum
20550 typedef enum TVX_NUM_FORMAT_ALL {
20558  * TVX_SRC_SEL enum
20561 typedef enum TVX_SRC_SEL {
20571  * TVX_SRF_MODE_ALL enum
20574 typedef enum TVX_SRF_MODE_ALL {
20580  * TVX_TYPE enum
20583 typedef enum TVX_TYPE {
20595  * SU_PERFCNT_SEL enum
20598 typedef enum SU_PERFCNT_SEL {
20755  * SC_PERFCNT_SEL enum
20758 typedef enum SC_PERFCNT_SEL {
21193  * SePairXsel enum
21196 typedef enum SePairXsel {
21205  * SePairYsel enum
21208 typedef enum SePairYsel {
21217  * SePairMap enum
21220 typedef enum SePairMap {
21228  * SeXsel enum
21231 typedef enum SeXsel {
21240  * SeYsel enum
21243 typedef enum SeYsel {
21252  * SeMap enum
21255 typedef enum SeMap {
21263  * ScXsel enum
21266 typedef enum ScXsel {
21274  * ScYsel enum
21277 typedef enum ScYsel {
21285  * ScMap enum
21288 typedef enum ScMap {
21296  * PkrXsel2 enum
21299 typedef enum PkrXsel2 {
21307  * PkrXsel enum
21310 typedef enum PkrXsel {
21318  * PkrYsel enum
21321 typedef enum PkrYsel {
21329  * PkrMap enum
21332 typedef enum PkrMap {
21340  * RbXsel enum
21343 typedef enum RbXsel {
21349  * RbYsel enum
21352 typedef enum RbYsel {
21358  * RbXsel2 enum
21361 typedef enum RbXsel2 {
21369  * RbMap enum
21372 typedef enum RbMap {
21380  * BinningMode enum
21383 typedef enum BinningMode {
21391  * BinEventCntl enum
21394 typedef enum BinEventCntl {
21401  * CovToShaderSel enum
21404 typedef enum CovToShaderSel {
21416  * RMIPerfSel enum
21419 typedef enum RMIPerfSel {
21659  * IH_PERF_SEL enum
21662 typedef enum IH_PERF_SEL {
22182  * SEM_PERF_SEL enum
22185 typedef enum SEM_PERF_SEL {
22367  * SDMA_PERF_SEL enum
22370 typedef enum SDMA_PERF_SEL {
22478  * ENUM_XDMA_LOCAL_SW_MODE enum
22481 typedef enum ENUM_XDMA_LOCAL_SW_MODE {
22492  * ENUM_XDMA_SLV_ALPHA_POSITION enum
22495 typedef enum ENUM_XDMA_SLV_ALPHA_POSITION {
22507  * ENUM_XDMA_MSTR_ALPHA_POSITION enum
22510 typedef enum ENUM_XDMA_MSTR_ALPHA_POSITION {
22518  * ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL enum
22521 typedef enum ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL {