Lines Matching full:enum

51  * DSM_DATA_SEL enum
54 typedef enum DSM_DATA_SEL {
62  * DSM_ENABLE_ERROR_INJECT enum
65 typedef enum DSM_ENABLE_ERROR_INJECT {
73  * DSM_SELECT_INJECT_DELAY enum
76 typedef enum DSM_SELECT_INJECT_DELAY {
82  * DSM_SINGLE_WRITE enum
85 typedef enum DSM_SINGLE_WRITE {
91  * ENUM_NUM_SIMD_PER_CU enum
94 typedef enum ENUM_NUM_SIMD_PER_CU {
99  * GATCL1RequestType enum
102 typedef enum GATCL1RequestType {
109  * GL0V_CACHE_POLICIES enum
112 typedef enum GL0V_CACHE_POLICIES {
120  * GL1_CACHE_POLICIES enum
123 typedef enum GL1_CACHE_POLICIES {
131  * GL1_CACHE_STORE_POLICIES enum
134 typedef enum GL1_CACHE_STORE_POLICIES {
139  * GL2_CACHE_POLICIES enum
142 typedef enum GL2_CACHE_POLICIES {
150  * Hdp_SurfaceEndian enum
153 typedef enum Hdp_SurfaceEndian {
161  * MTYPE enum
164 typedef enum MTYPE {
176  * PERFMON_COUNTER_MODE enum
179 typedef enum PERFMON_COUNTER_MODE {
194  * PERFMON_SPM_MODE enum
197 typedef enum PERFMON_SPM_MODE {
212  * RMI_CID enum
215 typedef enum RMI_CID {
227  * ReadPolicy enum
230 typedef enum ReadPolicy {
238  * SDMA_PERFMON_SEL enum
241 typedef enum SDMA_PERFMON_SEL {
339  * SDMA_PERF_SEL enum
342 typedef enum SDMA_PERF_SEL {
466  * TCC_CACHE_POLICIES enum
469 typedef enum TCC_CACHE_POLICIES {
475  * TCC_MTYPE enum
478 typedef enum TCC_MTYPE {
485  * UTCL0FaultType enum
488 typedef enum UTCL0FaultType {
496  * UTCL0RequestType enum
499 typedef enum UTCL0RequestType {
506  * UTCL1FaultType enum
509 typedef enum UTCL1FaultType {
517  * UTCL1RequestType enum
520 typedef enum UTCL1RequestType {
527  * VMEMCMD_RETURN_ORDER enum
530 typedef enum VMEMCMD_RETURN_ORDER {
537  * WritePolicy enum
540 typedef enum WritePolicy {
552  * CNVC_BYPASS enum
555 typedef enum CNVC_BYPASS {
561  * CNVC_COEF_FORMAT_ENUM enum
564 typedef enum CNVC_COEF_FORMAT_ENUM {
570  * CNVC_ENABLE enum
573 typedef enum CNVC_ENABLE {
579  * CNVC_PENDING enum
582 typedef enum CNVC_PENDING {
588  * COLOR_KEYER_MODE enum
591 typedef enum COLOR_KEYER_MODE {
599  * DENORM_TRUNCATE enum
602 typedef enum DENORM_TRUNCATE {
608  * FORMAT_CROSSBAR enum
611 typedef enum FORMAT_CROSSBAR {
618  * PIX_EXPAND_MODE enum
621 typedef enum PIX_EXPAND_MODE {
627  * PRE_CSC_MODE_ENUM enum
630 typedef enum PRE_CSC_MODE_ENUM {
637  * PRE_DEGAM_MODE enum
640 typedef enum PRE_DEGAM_MODE {
646  * PRE_DEGAM_SELECT enum
649 typedef enum PRE_DEGAM_SELECT {
660  * SURFACE_PIXEL_FORMAT enum
663 typedef enum SURFACE_PIXEL_FORMAT {
742  * XNORM enum
745 typedef enum XNORM {
755  * CUR_ENABLE enum
758 typedef enum CUR_ENABLE {
764  * CUR_EXPAND_MODE enum
767 typedef enum CUR_EXPAND_MODE {
773  * CUR_INV_CLAMP enum
776 typedef enum CUR_INV_CLAMP {
782  * CUR_MODE enum
785 typedef enum CUR_MODE {
795  * CUR_PENDING enum
798 typedef enum CUR_PENDING {
804  * CUR_ROM_EN enum
807 typedef enum CUR_ROM_EN {
817  * COEF_RAM_SELECT_RD enum
820 typedef enum COEF_RAM_SELECT_RD {
826  * DSCL_MODE_SEL enum
829 typedef enum DSCL_MODE_SEL {
840  * LB_ALPHA_EN enum
843 typedef enum LB_ALPHA_EN {
849  * LB_INTERLEAVE_EN enum
852 typedef enum LB_INTERLEAVE_EN {
858  * LB_MEMORY_CONFIG enum
861 typedef enum LB_MEMORY_CONFIG {
869  * OBUF_BYPASS_SEL enum
872 typedef enum OBUF_BYPASS_SEL {
878  * OBUF_IS_HALF_RECOUT_WIDTH_SEL enum
881 typedef enum OBUF_IS_HALF_RECOUT_WIDTH_SEL {
887  * OBUF_USE_FULL_BUFFER_SEL enum
890 typedef enum OBUF_USE_FULL_BUFFER_SEL {
896  * SCL_2TAP_HARDCODE enum
899 typedef enum SCL_2TAP_HARDCODE {
905  * SCL_ALPHA_COEF enum
908 typedef enum SCL_ALPHA_COEF {
914  * SCL_AUTOCAL_MODE enum
917 typedef enum SCL_AUTOCAL_MODE {
925  * SCL_BOUNDARY enum
928 typedef enum SCL_BOUNDARY {
934  * SCL_CHROMA_COEF enum
937 typedef enum SCL_CHROMA_COEF {
943  * SCL_COEF_FILTER_TYPE_SEL enum
946 typedef enum SCL_COEF_FILTER_TYPE_SEL {
954  * SCL_COEF_RAM_SEL enum
957 typedef enum SCL_COEF_RAM_SEL {
963  * SCL_SHARP_EN enum
966 typedef enum SCL_SHARP_EN {
976  * CMC_3DLUT_30BIT_ENUM enum
979 typedef enum CMC_3DLUT_30BIT_ENUM {
985  * CMC_3DLUT_RAM_SEL enum
988 typedef enum CMC_3DLUT_RAM_SEL {
996  * CMC_3DLUT_SIZE_ENUM enum
999 typedef enum CMC_3DLUT_SIZE_ENUM {
1005  * CMC_LUT_2_CONFIG_ENUM enum
1008 typedef enum CMC_LUT_2_CONFIG_ENUM {
1015  * CMC_LUT_2_MODE_ENUM enum
1018 typedef enum CMC_LUT_2_MODE_ENUM {
1025  * CMC_LUT_NUM_SEG enum
1028 typedef enum CMC_LUT_NUM_SEG {
1040  * CMC_LUT_RAM_SEL enum
1043 typedef enum CMC_LUT_RAM_SEL {
1049  * CM_BYPASS enum
1052 typedef enum CM_BYPASS {
1058  * CM_COEF_FORMAT_ENUM enum
1061 typedef enum CM_COEF_FORMAT_ENUM {
1067  * CM_DATA_SIGNED enum
1070 typedef enum CM_DATA_SIGNED {
1076  * CM_EN enum
1079 typedef enum CM_EN {
1085  * CM_GAMMA_LUT_MODE_ENUM enum
1088 typedef enum CM_GAMMA_LUT_MODE_ENUM {
1096  * CM_GAMMA_LUT_PWL_DISABLE_ENUM enum
1099 typedef enum CM_GAMMA_LUT_PWL_DISABLE_ENUM {
1105  * CM_GAMMA_LUT_SEL_ENUM enum
1108 typedef enum CM_GAMMA_LUT_SEL_ENUM {
1114  * CM_GAMUT_REMAP_MODE_ENUM enum
1117 typedef enum CM_GAMUT_REMAP_MODE_ENUM {
1124  * CM_LUT_2_CONFIG_ENUM enum
1127 typedef enum CM_LUT_2_CONFIG_ENUM {
1134  * CM_LUT_2_MODE_ENUM enum
1137 typedef enum CM_LUT_2_MODE_ENUM {
1144  * CM_LUT_4_CONFIG_ENUM enum
1147 typedef enum CM_LUT_4_CONFIG_ENUM {
1156  * CM_LUT_4_MODE_ENUM enum
1159 typedef enum CM_LUT_4_MODE_ENUM {
1168  * CM_LUT_CONFIG_MODE enum
1171 typedef enum CM_LUT_CONFIG_MODE {
1177  * CM_LUT_NUM_SEG enum
1180 typedef enum CM_LUT_NUM_SEG {
1192  * CM_LUT_RAM_SEL enum
1195 typedef enum CM_LUT_RAM_SEL {
1201  * CM_LUT_READ_COLOR_SEL enum
1204 typedef enum CM_LUT_READ_COLOR_SEL {
1211  * CM_LUT_READ_DBG enum
1214 typedef enum CM_LUT_READ_DBG {
1220  * CM_PENDING enum
1223 typedef enum CM_PENDING {
1229  * CM_POST_CSC_MODE_ENUM enum
1232 typedef enum CM_POST_CSC_MODE_ENUM {
1239  * CM_WRITE_BASE_ONLY enum
1242 typedef enum CM_WRITE_BASE_ONLY {
1252  * CRC_CUR_SEL enum
1255 typedef enum CRC_CUR_SEL {
1261  * CRC_INTERLACE_SEL enum
1264 typedef enum CRC_INTERLACE_SEL {
1272  * CRC_IN_CUR_SEL enum
1275 typedef enum CRC_IN_CUR_SEL {
1283  * CRC_IN_PIX_SEL enum
1286 typedef enum CRC_IN_PIX_SEL {
1298  * CRC_SRC_SEL enum
1301 typedef enum CRC_SRC_SEL {
1309  * CRC_STEREO_SEL enum
1312 typedef enum CRC_STEREO_SEL {
1320  * TEST_CLK_SEL enum
1323 typedef enum TEST_CLK_SEL {
1339  * PERFCOUNTER_ACTIVE enum
1342 typedef enum PERFCOUNTER_ACTIVE {
1348  * PERFCOUNTER_CNT0_STATE enum
1351 typedef enum PERFCOUNTER_CNT0_STATE {
1359  * PERFCOUNTER_CNT1_STATE enum
1362 typedef enum PERFCOUNTER_CNT1_STATE {
1370  * PERFCOUNTER_CNT2_STATE enum
1373 typedef enum PERFCOUNTER_CNT2_STATE {
1381  * PERFCOUNTER_CNT3_STATE enum
1384 typedef enum PERFCOUNTER_CNT3_STATE {
1392  * PERFCOUNTER_CNT4_STATE enum
1395 typedef enum PERFCOUNTER_CNT4_STATE {
1403  * PERFCOUNTER_CNT5_STATE enum
1406 typedef enum PERFCOUNTER_CNT5_STATE {
1414  * PERFCOUNTER_CNT6_STATE enum
1417 typedef enum PERFCOUNTER_CNT6_STATE {
1425  * PERFCOUNTER_CNT7_STATE enum
1428 typedef enum PERFCOUNTER_CNT7_STATE {
1436  * PERFCOUNTER_CNTL_SEL enum
1439 typedef enum PERFCOUNTER_CNTL_SEL {
1451  * PERFCOUNTER_CNTOFF_START_DIS enum
1454 typedef enum PERFCOUNTER_CNTOFF_START_DIS {
1460  * PERFCOUNTER_COUNTED_VALUE_TYPE enum
1463 typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
1470  * PERFCOUNTER_CVALUE_SEL enum
1473 typedef enum PERFCOUNTER_CVALUE_SEL {
1485  * PERFCOUNTER_HW_CNTL_SEL enum
1488 typedef enum PERFCOUNTER_HW_CNTL_SEL {
1494  * PERFCOUNTER_HW_STOP1_SEL enum
1497 typedef enum PERFCOUNTER_HW_STOP1_SEL {
1503  * PERFCOUNTER_HW_STOP2_SEL enum
1506 typedef enum PERFCOUNTER_HW_STOP2_SEL {
1512  * PERFCOUNTER_INC_MODE enum
1515 typedef enum PERFCOUNTER_INC_MODE {
1524  * PERFCOUNTER_INT_EN enum
1527 typedef enum PERFCOUNTER_INT_EN {
1533  * PERFCOUNTER_INT_TYPE enum
1536 typedef enum PERFCOUNTER_INT_TYPE {
1542  * PERFCOUNTER_OFF_MASK enum
1545 typedef enum PERFCOUNTER_OFF_MASK {
1551  * PERFCOUNTER_RESTART_EN enum
1554 typedef enum PERFCOUNTER_RESTART_EN {
1560  * PERFCOUNTER_RUNEN_MODE enum
1563 typedef enum PERFCOUNTER_RUNEN_MODE {
1569  * PERFCOUNTER_STATE_SEL0 enum
1572 typedef enum PERFCOUNTER_STATE_SEL0 {
1578  * PERFCOUNTER_STATE_SEL1 enum
1581 typedef enum PERFCOUNTER_STATE_SEL1 {
1587  * PERFCOUNTER_STATE_SEL2 enum
1590 typedef enum PERFCOUNTER_STATE_SEL2 {
1596  * PERFCOUNTER_STATE_SEL3 enum
1599 typedef enum PERFCOUNTER_STATE_SEL3 {
1605  * PERFCOUNTER_STATE_SEL4 enum
1608 typedef enum PERFCOUNTER_STATE_SEL4 {
1614  * PERFCOUNTER_STATE_SEL5 enum
1617 typedef enum PERFCOUNTER_STATE_SEL5 {
1623  * PERFCOUNTER_STATE_SEL6 enum
1626 typedef enum PERFCOUNTER_STATE_SEL6 {
1632  * PERFCOUNTER_STATE_SEL7 enum
1635 typedef enum PERFCOUNTER_STATE_SEL7 {
1641  * PERFMON_CNTOFF_AND_OR enum
1644 typedef enum PERFMON_CNTOFF_AND_OR {
1650  * PERFMON_CNTOFF_INT_EN enum
1653 typedef enum PERFMON_CNTOFF_INT_EN {
1659  * PERFMON_CNTOFF_INT_TYPE enum
1662 typedef enum PERFMON_CNTOFF_INT_TYPE {
1668  * PERFMON_STATE enum
1671 typedef enum PERFMON_STATE {
1683  * BIGK_FRAGMENT_SIZE enum
1686 typedef enum BIGK_FRAGMENT_SIZE {
1700  * CHUNK_SIZE enum
1703 typedef enum CHUNK_SIZE {
1714  * COMPAT_LEVEL enum
1717 typedef enum COMPAT_LEVEL {
1725  * DPTE_GROUP_SIZE enum
1728 typedef enum DPTE_GROUP_SIZE {
1738  * FORCE_ONE_ROW_FOR_FRAME enum
1741 typedef enum FORCE_ONE_ROW_FOR_FRAME {
1747  * HUBP_BLANK_EN enum
1750 typedef enum HUBP_BLANK_EN {
1756  * HUBP_IN_BLANK enum
1759 typedef enum HUBP_IN_BLANK {
1765  * HUBP_MEASURE_WIN_MODE_DCFCLK enum
1768 typedef enum HUBP_MEASURE_WIN_MODE_DCFCLK {
1776  * HUBP_NO_OUTSTANDING_REQ enum
1779 typedef enum HUBP_NO_OUTSTANDING_REQ {
1785  * HUBP_SOFT_RESET enum
1788 typedef enum HUBP_SOFT_RESET {
1794  * HUBP_TTU_DISABLE enum
1797 typedef enum HUBP_TTU_DISABLE {
1803  * HUBP_VREADY_AT_OR_AFTER_VSYNC enum
1806 typedef enum HUBP_VREADY_AT_OR_AFTER_VSYNC {
1812  * HUBP_VTG_SEL enum
1815 typedef enum HUBP_VTG_SEL {
1825  * H_MIRROR_EN enum
1828 typedef enum H_MIRROR_EN {
1834  * LEGACY_PIPE_INTERLEAVE enum
1837 typedef enum LEGACY_PIPE_INTERLEAVE {
1843  * META_CHUNK_SIZE enum
1846 typedef enum META_CHUNK_SIZE {
1854  * META_LINEAR enum
1857 typedef enum META_LINEAR {
1863  * MIN_CHUNK_SIZE enum
1866 typedef enum MIN_CHUNK_SIZE {
1874  * MIN_META_CHUNK_SIZE enum
1877 typedef enum MIN_META_CHUNK_SIZE {
1885  * PIPE_ALIGNED enum
1888 typedef enum PIPE_ALIGNED {
1894  * PTE_BUFFER_MODE enum
1897 typedef enum PTE_BUFFER_MODE {
1903  * PTE_ROW_HEIGHT_LINEAR enum
1906 typedef enum PTE_ROW_HEIGHT_LINEAR {
1918  * ROTATION_ANGLE enum
1921 typedef enum ROTATION_ANGLE {
1929  * SWATH_HEIGHT enum
1932 typedef enum SWATH_HEIGHT {
1941  * USE_MALL_FOR_CURSOR enum
1944 typedef enum USE_MALL_FOR_CURSOR {
1950  * USE_MALL_FOR_PSTATE_CHANGE enum
1953 typedef enum USE_MALL_FOR_PSTATE_CHANGE {
1959  * USE_MALL_FOR_STATIC_SCREEN enum
1962 typedef enum USE_MALL_FOR_STATIC_SCREEN {
1968  * VMPG_SIZE enum
1971 typedef enum VMPG_SIZE {
1977  * VM_GROUP_SIZE enum
1980 typedef enum VM_GROUP_SIZE {
1994  * DFQ_MIN_FREE_ENTRIES enum
1997 typedef enum DFQ_MIN_FREE_ENTRIES {
2009  * DFQ_NUM_ENTRIES enum
2012 typedef enum DFQ_NUM_ENTRIES {
2025  * DFQ_SIZE enum
2028 typedef enum DFQ_SIZE {
2040  * DMDATA_VM_DONE enum
2043 typedef enum DMDATA_VM_DONE {
2049  * EXPANSION_MODE enum
2052 typedef enum EXPANSION_MODE {
2059  * FLIP_RATE enum
2062 typedef enum FLIP_RATE {
2074  * INT_MASK enum
2077 typedef enum INT_MASK {
2083  * PIPE_IN_FLUSH_URGENT enum
2086 typedef enum PIPE_IN_FLUSH_URGENT {
2092  * PRQ_MRQ_FLUSH_URGENT enum
2095 typedef enum PRQ_MRQ_FLUSH_URGENT {
2101  * ROW_TTU_MODE enum
2104 typedef enum ROW_TTU_MODE {
2110  * SURFACE_DCC enum
2113 typedef enum SURFACE_DCC {
2119  * SURFACE_DCC_IND_128B enum
2122 typedef enum SURFACE_DCC_IND_128B {
2128  * SURFACE_DCC_IND_64B enum
2131 typedef enum SURFACE_DCC_IND_64B {
2137  * SURFACE_DCC_IND_BLK enum
2140 typedef enum SURFACE_DCC_IND_BLK {
2148  * SURFACE_FLIP_AWAY_INT_TYPE enum
2151 typedef enum SURFACE_FLIP_AWAY_INT_TYPE {
2157  * SURFACE_FLIP_EXEC_DEBUG_MODE enum
2160 typedef enum SURFACE_FLIP_EXEC_DEBUG_MODE {
2166  * SURFACE_FLIP_INT_TYPE enum
2169 typedef enum SURFACE_FLIP_INT_TYPE {
2175  * SURFACE_FLIP_IN_STEREOSYNC enum
2178 typedef enum SURFACE_FLIP_IN_STEREOSYNC {
2184  * SURFACE_FLIP_MODE_FOR_STEREOSYNC enum
2187 typedef enum SURFACE_FLIP_MODE_FOR_STEREOSYNC {
2195  * SURFACE_FLIP_STEREO_SELECT_DISABLE enum
2198 typedef enum SURFACE_FLIP_STEREO_SELECT_DISABLE {
2204  * SURFACE_FLIP_STEREO_SELECT_POLARITY enum
2207 typedef enum SURFACE_FLIP_STEREO_SELECT_POLARITY {
2213  * SURFACE_FLIP_TYPE enum
2216 typedef enum SURFACE_FLIP_TYPE {
2222  * SURFACE_FLIP_VUPDATE_SKIP_NUM enum
2225 typedef enum SURFACE_FLIP_VUPDATE_SKIP_NUM {
2245  * SURFACE_INUSE_RAED_NO_LATCH enum
2248 typedef enum SURFACE_INUSE_RAED_NO_LATCH {
2254  * SURFACE_TMZ enum
2257 typedef enum SURFACE_TMZ {
2263  * SURFACE_UPDATE_LOCK enum
2266 typedef enum SURFACE_UPDATE_LOCK {
2276  * CROSSBAR_FOR_ALPHA enum
2279 typedef enum CROSSBAR_FOR_ALPHA {
2287  * CROSSBAR_FOR_CB_B enum
2290 typedef enum CROSSBAR_FOR_CB_B {
2298  * CROSSBAR_FOR_CR_R enum
2301 typedef enum CROSSBAR_FOR_CR_R {
2309  * CROSSBAR_FOR_Y_G enum
2312 typedef enum CROSSBAR_FOR_Y_G {
2320  * DETILE_BUFFER_PACKER_ENABLE enum
2323 typedef enum DETILE_BUFFER_PACKER_ENABLE {
2329  * MEM_PWR_DIS_MODE enum
2332 typedef enum MEM_PWR_DIS_MODE {
2338  * MEM_PWR_FORCE_MODE enum
2341 typedef enum MEM_PWR_FORCE_MODE {
2349  * MEM_PWR_STATUS enum
2352 typedef enum MEM_PWR_STATUS {
2360  * PIPE_INT_MASK_MODE enum
2363 typedef enum PIPE_INT_MASK_MODE {
2369  * PIPE_INT_TYPE_MODE enum
2372 typedef enum PIPE_INT_TYPE_MODE {
2378  * PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE enum
2381 typedef enum PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE {
2391  * CROB_MEM_PWR_LIGHT_SLEEP_MODE enum
2394 typedef enum CROB_MEM_PWR_LIGHT_SLEEP_MODE {
2401  * CURSOR_2X_MAGNIFY enum
2404 typedef enum CURSOR_2X_MAGNIFY {
2410  * CURSOR_ENABLE enum
2413 typedef enum CURSOR_ENABLE {
2419  * CURSOR_LINES_PER_CHUNK enum
2422 typedef enum CURSOR_LINES_PER_CHUNK {
2431  * CURSOR_MODE enum
2434 typedef enum CURSOR_MODE {
2444  * CURSOR_PERFMON_LATENCY_MEASURE_EN enum
2447 typedef enum CURSOR_PERFMON_LATENCY_MEASURE_EN {
2453  * CURSOR_PERFMON_LATENCY_MEASURE_SEL enum
2456 typedef enum CURSOR_PERFMON_LATENCY_MEASURE_SEL {
2462  * CURSOR_PITCH enum
2465 typedef enum CURSOR_PITCH {
2472  * CURSOR_REQ_MODE enum
2475 typedef enum CURSOR_REQ_MODE {
2481  * CURSOR_SNOOP enum
2484 typedef enum CURSOR_SNOOP {
2490  * CURSOR_STEREO_EN enum
2493 typedef enum CURSOR_STEREO_EN {
2499  * CURSOR_SURFACE_TMZ enum
2502 typedef enum CURSOR_SURFACE_TMZ {
2508  * CURSOR_SYSTEM enum
2511 typedef enum CURSOR_SYSTEM {
2517  * CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS enum
2520 typedef enum CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS {
2526  * DMDATA_DONE enum
2529 typedef enum DMDATA_DONE {
2535  * DMDATA_MODE enum
2538 typedef enum DMDATA_MODE {
2544  * DMDATA_QOS_MODE enum
2547 typedef enum DMDATA_QOS_MODE {
2553  * DMDATA_REPEAT enum
2556 typedef enum DMDATA_REPEAT {
2562  * DMDATA_UNDERFLOW enum
2565 typedef enum DMDATA_UNDERFLOW {
2571  * DMDATA_UNDERFLOW_CLEAR enum
2574 typedef enum DMDATA_UNDERFLOW_CLEAR {
2580  * DMDATA_UPDATED enum
2583 typedef enum DMDATA_UPDATED {
2593  * RESPONSE_STATUS enum
2596 typedef enum RESPONSE_STATUS {
2614  * DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE enum
2617 typedef enum DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE {
2624  * DCHUBBUB_MEM_PWR_DIS_MODE enum
2627 typedef enum DCHUBBUB_MEM_PWR_DIS_MODE {
2633  * DCHUBBUB_MEM_PWR_MODE enum
2636 typedef enum DCHUBBUB_MEM_PWR_MODE {
2648  * MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET enum
2651 typedef enum MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET {
2657  * MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET enum
2660 typedef enum MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET {
2666  * MPC_CFG_ADR_VUPDATE_LOCK_SET enum
2669 typedef enum MPC_CFG_ADR_VUPDATE_LOCK_SET {
2675  * MPC_CFG_CFG_VUPDATE_LOCK_SET enum
2678 typedef enum MPC_CFG_CFG_VUPDATE_LOCK_SET {
2684  * MPC_CFG_CUR_VUPDATE_LOCK_SET enum
2687 typedef enum MPC_CFG_CUR_VUPDATE_LOCK_SET {
2693  * MPC_CFG_MPC_TEST_CLK_SEL enum
2696 typedef enum MPC_CFG_MPC_TEST_CLK_SEL {
2704  * MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN enum
2707 typedef enum MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN {
2713  * MPC_CRC_CALC_INTERLACE_MODE enum
2716 typedef enum MPC_CRC_CALC_INTERLACE_MODE {
2724  * MPC_CRC_CALC_MODE enum
2727 typedef enum MPC_CRC_CALC_MODE {
2733  * MPC_CRC_CALC_STEREO_MODE enum
2736 typedef enum MPC_CRC_CALC_STEREO_MODE {
2744  * MPC_CRC_SOURCE_SELECT enum
2747 typedef enum MPC_CRC_SOURCE_SELECT {
2755  * MPC_DEBUG_BUS1_DATA_SELECT enum
2758 typedef enum MPC_DEBUG_BUS1_DATA_SELECT {
2766  * MPC_DEBUG_BUS2_DATA_SELECT enum
2769 typedef enum MPC_DEBUG_BUS2_DATA_SELECT {
2777  * MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT enum
2780 typedef enum MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT {
2792  * MPC_DEBUG_BUS_MPCC_BYTE_SELECT enum
2795 typedef enum MPC_DEBUG_BUS_MPCC_BYTE_SELECT {
2807  * MPC_OCSC_COEF_FORMAT enum
2810 typedef enum MPC_OCSC_COEF_FORMAT {
2816  * MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN enum
2819 typedef enum MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN {
2825  * MPC_OUT_CSC_MODE enum
2828 typedef enum MPC_OUT_CSC_MODE {
2836  * MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE enum
2839 typedef enum MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE {
2851  * MPC_OUT_RATE_CONTROL_DISABLE_SET enum
2854 typedef enum MPC_OUT_RATE_CONTROL_DISABLE_SET {
2864  * MPCC_BG_COLOR_BPC enum
2867 typedef enum MPCC_BG_COLOR_BPC {
2876  * MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY enum
2879 typedef enum MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY {
2885  * MPCC_CONTROL_MPCC_ALPHA_BLND_MODE enum
2888 typedef enum MPCC_CONTROL_MPCC_ALPHA_BLND_MODE {
2896  * MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE enum
2899 typedef enum MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE {
2905  * MPCC_CONTROL_MPCC_BOT_GAIN_MODE enum
2908 typedef enum MPCC_CONTROL_MPCC_BOT_GAIN_MODE {
2914  * MPCC_CONTROL_MPCC_MODE enum
2917 typedef enum MPCC_CONTROL_MPCC_MODE {
2925  * MPCC_SM_CONTROL_MPCC_SM_EN enum
2928 typedef enum MPCC_SM_CONTROL_MPCC_SM_EN {
2934  * MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT enum
2937 typedef enum MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT {
2943  * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL enum
2946 typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL {
2954  * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL enum
2957 typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL {
2965  * MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT enum
2968 typedef enum MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT {
2974  * MPCC_SM_CONTROL_MPCC_SM_MODE enum
2977 typedef enum MPCC_SM_CONTROL_MPCC_SM_MODE {
2985  * MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN enum
2988 typedef enum MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN {
2998  * MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM enum
3001 typedef enum MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM {
3007  * MPCC_GAMUT_REMAP_MODE_ENUM enum
3010 typedef enum MPCC_GAMUT_REMAP_MODE_ENUM {
3018  * MPCC_OGAM_LUT_2_CONFIG_ENUM enum
3021 typedef enum MPCC_OGAM_LUT_2_CONFIG_ENUM {
3028  * MPCC_OGAM_LUT_CONFIG_MODE enum
3031 typedef enum MPCC_OGAM_LUT_CONFIG_MODE {
3037  * MPCC_OGAM_LUT_PWL_DISABLE_ENUM enum
3040 typedef enum MPCC_OGAM_LUT_PWL_DISABLE_ENUM {
3046  * MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL enum
3049 typedef enum MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL {
3055  * MPCC_OGAM_LUT_RAM_SEL enum
3058 typedef enum MPCC_OGAM_LUT_RAM_SEL {
3064  * MPCC_OGAM_LUT_READ_COLOR_SEL enum
3067 typedef enum MPCC_OGAM_LUT_READ_COLOR_SEL {
3074  * MPCC_OGAM_LUT_READ_DBG enum
3077 typedef enum MPCC_OGAM_LUT_READ_DBG {
3083  * MPCC_OGAM_LUT_SEL_ENUM enum
3086 typedef enum MPCC_OGAM_LUT_SEL_ENUM {
3092  * MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM enum
3095 typedef enum MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM {
3103  * MPCC_OGAM_NUM_SEG enum
3106 typedef enum MPCC_OGAM_NUM_SEG {
3118  * MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN enum
3121 typedef enum MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN {
3131  * MPCC_MCM_3DLUT_30BIT_ENUM enum
3134 typedef enum MPCC_MCM_3DLUT_30BIT_ENUM {
3140  * MPCC_MCM_3DLUT_RAM_SEL enum
3143 typedef enum MPCC_MCM_3DLUT_RAM_SEL {
3151  * MPCC_MCM_3DLUT_SIZE_ENUM enum
3154 typedef enum MPCC_MCM_3DLUT_SIZE_ENUM {
3160  * MPCC_MCM_GAMMA_LUT_MODE_ENUM enum
3163 typedef enum MPCC_MCM_GAMMA_LUT_MODE_ENUM {
3171  * MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM enum
3174 typedef enum MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM {
3180  * MPCC_MCM_GAMMA_LUT_SEL_ENUM enum
3183 typedef enum MPCC_MCM_GAMMA_LUT_SEL_ENUM {
3189  * MPCC_MCM_LUT_2_MODE_ENUM enum
3192 typedef enum MPCC_MCM_LUT_2_MODE_ENUM {
3199  * MPCC_MCM_LUT_CONFIG_MODE enum
3202 typedef enum MPCC_MCM_LUT_CONFIG_MODE {
3208  * MPCC_MCM_LUT_NUM_SEG enum
3211 typedef enum MPCC_MCM_LUT_NUM_SEG {
3223  * MPCC_MCM_LUT_RAM_SEL enum
3226 typedef enum MPCC_MCM_LUT_RAM_SEL {
3232  * MPCC_MCM_LUT_READ_COLOR_SEL enum
3235 typedef enum MPCC_MCM_LUT_READ_COLOR_SEL {
3242  * MPCC_MCM_LUT_READ_DBG enum
3245 typedef enum MPCC_MCM_LUT_READ_DBG {
3251  * MPCC_MCM_MEM_PWR_FORCE_ENUM enum
3254 typedef enum MPCC_MCM_MEM_PWR_FORCE_ENUM {
3262  * MPCC_MCM_MEM_PWR_STATE_ENUM enum
3265 typedef enum MPCC_MCM_MEM_PWR_STATE_ENUM {
3281  * ENUM_DPG_BIT_DEPTH enum
3284 typedef enum ENUM_DPG_BIT_DEPTH {
3292  * ENUM_DPG_DYNAMIC_RANGE enum
3295 typedef enum ENUM_DPG_DYNAMIC_RANGE {
3301  * ENUM_DPG_EN enum
3304 typedef enum ENUM_DPG_EN {
3310  * ENUM_DPG_FIELD_POLARITY enum
3313 typedef enum ENUM_DPG_FIELD_POLARITY {
3319  * ENUM_DPG_MODE enum
3322 typedef enum ENUM_DPG_MODE {
3338  * FMTMEM_PWR_DIS_CTRL enum
3341 typedef enum FMTMEM_PWR_DIS_CTRL {
3347  * FMTMEM_PWR_FORCE_CTRL enum
3350 typedef enum FMTMEM_PWR_FORCE_CTRL {
3358  * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum
3361 typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
3369  * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum
3372 typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
3380  * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum
3383 typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
3391  * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum
3394 typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
3401  * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum
3404 typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
3411  * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum
3414 typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
3420  * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum
3423 typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
3430  * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum
3433 typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
3439  * FMT_CLAMP_CNTL_COLOR_FORMAT enum
3442 typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
3454  * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum
3457 typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
3463  * FMT_CONTROL_PIXEL_ENCODING enum
3466 typedef enum FMT_CONTROL_PIXEL_ENCODING {
3474  * FMT_CONTROL_SUBSAMPLING_MODE enum
3477 typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
3485  * FMT_CONTROL_SUBSAMPLING_ORDER enum
3488 typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
3494  * FMT_DEBUG_CNTL_COLOR_SELECT enum
3497 typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
3505  * FMT_DYNAMIC_EXP_MODE enum
3508 typedef enum FMT_DYNAMIC_EXP_MODE {
3514  * FMT_FRAME_RANDOM_ENABLE_CONTROL enum
3517 typedef enum FMT_FRAME_RANDOM_ENABLE_CONTROL {
3523  * FMT_POWER_STATE_ENUM enum
3526 typedef enum FMT_POWER_STATE_ENUM {
3534  * FMT_RGB_RANDOM_ENABLE_CONTROL enum
3537 typedef enum FMT_RGB_RANDOM_ENABLE_CONTROL {
3543  * FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL enum
3546 typedef enum FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL {
3554  * FMT_SPATIAL_DITHER_MODE enum
3557 typedef enum FMT_SPATIAL_DITHER_MODE {
3565  * FMT_STEREOSYNC_OVERRIDE_CONTROL enum
3568 typedef enum FMT_STEREOSYNC_OVERRIDE_CONTROL {
3574  * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum
3577 typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
3587  * OPPBUF_DISPLAY_SEGMENTATION enum
3590 typedef enum OPPBUF_DISPLAY_SEGMENTATION {
3603  * OPP_PIPE_CLOCK_ENABLE_CONTROL enum
3606 typedef enum OPP_PIPE_CLOCK_ENABLE_CONTROL {
3612  * OPP_PIPE_DIGTIAL_BYPASS_CONTROL enum
3615 typedef enum OPP_PIPE_DIGTIAL_BYPASS_CONTROL {
3625  * OPP_PIPE_CRC_CONT_EN enum
3628 typedef enum OPP_PIPE_CRC_CONT_EN {
3634  * OPP_PIPE_CRC_EN enum
3637 typedef enum OPP_PIPE_CRC_EN {
3643  * OPP_PIPE_CRC_INTERLACE_EN enum
3646 typedef enum OPP_PIPE_CRC_INTERLACE_EN {
3652  * OPP_PIPE_CRC_INTERLACE_MODE enum
3655 typedef enum OPP_PIPE_CRC_INTERLACE_MODE {
3663  * OPP_PIPE_CRC_ONE_SHOT_PENDING enum
3666 typedef enum OPP_PIPE_CRC_ONE_SHOT_PENDING {
3672  * OPP_PIPE_CRC_PIXEL_SELECT enum
3675 typedef enum OPP_PIPE_CRC_PIXEL_SELECT {
3683  * OPP_PIPE_CRC_SOURCE_SELECT enum
3686 typedef enum OPP_PIPE_CRC_SOURCE_SELECT {
3692  * OPP_PIPE_CRC_STEREO_EN enum
3695 typedef enum OPP_PIPE_CRC_STEREO_EN {
3701  * OPP_PIPE_CRC_STEREO_MODE enum
3704 typedef enum OPP_PIPE_CRC_STEREO_MODE {
3716  * OPP_ABM_DEBUG_BUS_SELECT_CONTROL enum
3719 typedef enum OPP_ABM_DEBUG_BUS_SELECT_CONTROL {
3729  * OPP_DPG_DEBUG_BUS_SELECT_CONTROL enum
3732 typedef enum OPP_DPG_DEBUG_BUS_SELECT_CONTROL {
3742  * OPP_FMT_DEBUG_BUS_SELECT_CONTROL enum
3745 typedef enum OPP_FMT_DEBUG_BUS_SELECT_CONTROL {
3755  * OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL enum
3758 typedef enum OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL {
3768  * OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL enum
3771 typedef enum OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL {
3781  * OPP_TEST_CLK_SEL_CONTROL enum
3784 typedef enum OPP_TEST_CLK_SEL_CONTROL {
3802  * OPP_TOP_CLOCK_ENABLE_STATUS enum
3805 typedef enum OPP_TOP_CLOCK_ENABLE_STATUS {
3811  * OPP_TOP_CLOCK_GATING_CONTROL enum
3814 typedef enum OPP_TOP_CLOCK_GATING_CONTROL {
3824  * ENUM_DSCRM_EN enum
3827 typedef enum ENUM_DSCRM_EN {
3837  * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum
3840 typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
3846  * MASTER_UPDATE_LOCK_SEL enum
3849 typedef enum MASTER_UPDATE_LOCK_SEL {
3859  * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum
3862 typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
3870  * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN enum
3873 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN {
3879  * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB enum
3882 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB {
3888  * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR enum
3891 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR {
3897  * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE enum
3900 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE {
3908  * OTG_CONTROL_OTG_DISABLE_POINT_CNTL enum
3911 typedef enum OTG_CONTROL_OTG_DISABLE_POINT_CNTL {
3919  * OTG_CONTROL_OTG_FIELD_NUMBER_CNTL enum
3922 typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_CNTL {
3928  * OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY enum
3931 typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY {
3937  * OTG_CONTROL_OTG_MASTER_EN enum
3940 typedef enum OTG_CONTROL_OTG_MASTER_EN {
3946  * OTG_CONTROL_OTG_OUT_MUX enum
3949 typedef enum OTG_CONTROL_OTG_OUT_MUX {
3956  * OTG_CONTROL_OTG_START_POINT_CNTL enum
3959 typedef enum OTG_CONTROL_OTG_START_POINT_CNTL {
3965  * OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN enum
3968 typedef enum OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN {
3974  * OTG_CRC_CNTL_OTG_CRC1_EN enum
3977 typedef enum OTG_CRC_CNTL_OTG_CRC1_EN {
3983  * OTG_CRC_CNTL_OTG_CRC_CONT_EN enum
3986 typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_EN {
3992  * OTG_CRC_CNTL_OTG_CRC_CONT_MODE enum
3995 typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_MODE {
4001  * OTG_CRC_CNTL_OTG_CRC_EN enum
4004 typedef enum OTG_CRC_CNTL_OTG_CRC_EN {
4010  * OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE enum
4013 typedef enum OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE {
4021  * OTG_CRC_CNTL_OTG_CRC_STEREO_MODE enum
4024 typedef enum OTG_CRC_CNTL_OTG_CRC_STEREO_MODE {
4032  * OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS enum
4035 typedef enum OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS {
4041  * OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT enum
4044 typedef enum OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT {
4056  * OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT enum
4059 typedef enum OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT {
4071  * OTG_DIG_UPDATE_VCOUNT_MODE enum
4074 typedef enum OTG_DIG_UPDATE_VCOUNT_MODE {
4080  * OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE enum
4083 typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE {
4091  * OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY enum
4094 typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY {
4100  * OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME enum
4103 typedef enum OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME {
4111  * OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN enum
4114 typedef enum OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN {
4120  * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY enum
4123 typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY {
4129  * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY enum
4132 typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY {
4138  * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT enum
4141 typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT {
4165  * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK enum
4168 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK {
4174  * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR enum
4177 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR {
4183  * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE enum
4186 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE {
4194  * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL enum
4197 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL {
4203  * OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL enum
4206 typedef enum OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL {
4216  * OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL enum
4219 typedef enum OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL {
4226  * OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL enum
4229 typedef enum OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL {
4237  * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD enum
4240 typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD {
4248  * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL enum
4251 typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL {
4259  * OTG_GLOBAL_UPDATE_LOCK_EN enum
4262 typedef enum OTG_GLOBAL_UPDATE_LOCK_EN {
4268  * OTG_GSL_MASTER_MODE enum
4271 typedef enum OTG_GSL_MASTER_MODE {
4279  * OTG_HORZ_REPETITION_COUNT enum
4282 typedef enum OTG_HORZ_REPETITION_COUNT {
4302  * OTG_H_SYNC_A_POL enum
4305 typedef enum OTG_H_SYNC_A_POL {
4311  * OTG_H_TIMING_DIV_MODE enum
4314 typedef enum OTG_H_TIMING_DIV_MODE {
4322  * OTG_H_TIMING_DIV_MODE_MANUAL enum
4325 typedef enum OTG_H_TIMING_DIV_MODE_MANUAL {
4331  * OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE enum
4334 typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE {
4340  * OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD enum
4343 typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD {
4351  * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK enum
4354 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK {
4360  * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE enum
4363 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE {
4369  * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK enum
4372 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK {
4378  * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum
4381 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
4387  * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK enum
4390 typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK {
4396  * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE enum
4399 typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE {
4405  * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK enum
4408 typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK {
4414  * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE enum
4417 typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE {
4423  * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK enum
4426 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK {
4432  * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE enum
4435 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE {
4441  * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK enum
4444 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK {
4450  * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE enum
4453 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE {
4459  * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK enum
4462 typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK {
4468  * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE enum
4471 typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE {
4477  * OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE enum
4480 typedef enum OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE {
4486  * OTG_MASTER_UPDATE_LOCK_DB_EN enum
4489 typedef enum OTG_MASTER_UPDATE_LOCK_DB_EN {
4495  * OTG_MASTER_UPDATE_LOCK_GSL_EN enum
4498 typedef enum OTG_MASTER_UPDATE_LOCK_GSL_EN {
4504  * OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE enum
4507 typedef enum OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE {
4513  * OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL enum
4516 typedef enum OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL {
4524  * OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR enum
4527 typedef enum OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR {
4533  * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR enum
4536 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR {
4542  * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE enum
4545 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE {
4551  * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE enum
4554 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE {
4560  * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE enum
4563 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE {
4569  * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE enum
4572 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE {
4578  * OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL enum
4581 typedef enum OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL {
4587  * OTG_STEREO_CONTROL_OTG_STEREO_EN enum
4590 typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EN {
4596  * OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY enum
4599 typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY {
4605  * OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY enum
4608 typedef enum OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY {
4614  * OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE enum
4617 typedef enum OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE {
4625  * OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR enum
4628 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR {
4634  * OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT enum
4637 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT {
4649  * OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN enum
4652 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN {
4658  * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT enum
4661 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT {
4671  * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT enum
4674 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT {
4703  * OTG_TRIGA_FALLING_EDGE_DETECT_CNTL enum
4706 typedef enum OTG_TRIGA_FALLING_EDGE_DETECT_CNTL {
4714  * OTG_TRIGA_FREQUENCY_SELECT enum
4717 typedef enum OTG_TRIGA_FREQUENCY_SELECT {
4725  * OTG_TRIGA_RISING_EDGE_DETECT_CNTL enum
4728 typedef enum OTG_TRIGA_RISING_EDGE_DETECT_CNTL {
4736  * OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR enum
4739 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR {
4745  * OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT enum
4748 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT {
4760  * OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN enum
4763 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN {
4769  * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT enum
4772 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT {
4782  * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT enum
4785 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT {
4814  * OTG_TRIGB_FALLING_EDGE_DETECT_CNTL enum
4817 typedef enum OTG_TRIGB_FALLING_EDGE_DETECT_CNTL {
4825  * OTG_TRIGB_FREQUENCY_SELECT enum
4828 typedef enum OTG_TRIGB_FREQUENCY_SELECT {
4836  * OTG_TRIGB_RISING_EDGE_DETECT_CNTL enum
4839 typedef enum OTG_TRIGB_RISING_EDGE_DETECT_CNTL {
4847  * OTG_UPDATE_LOCK_OTG_UPDATE_LOCK enum
4850 typedef enum OTG_UPDATE_LOCK_OTG_UPDATE_LOCK {
4856  * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR enum
4859 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR {
4865  * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE enum
4868 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE {
4874  * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE enum
4877 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE {
4883  * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum
4886 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
4892  * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR enum
4895 typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR {
4901  * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE enum
4904 typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE {
4910  * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE enum
4913 typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE {
4919  * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR enum
4922 typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR {
4928  * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE enum
4931 typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE {
4937  * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE enum
4940 typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE {
4946  * OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE enum
4949 typedef enum OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE {
4957  * OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR enum
4960 typedef enum OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR {
4966  * OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR enum
4969 typedef enum OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR {
4975  * OTG_VUPDATE_BLOCK_DISABLE enum
4978 typedef enum OTG_VUPDATE_BLOCK_DISABLE {
4984  * OTG_V_SYNC_A_POL enum
4987 typedef enum OTG_V_SYNC_A_POL {
4993  * OTG_V_SYNC_MODE enum
4996 typedef enum OTG_V_SYNC_MODE {
5002  * OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD enum
5005 typedef enum OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD {
5011  * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT enum
5014 typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT {
5020  * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC enum
5023 typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC {
5029  * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL enum
5032 typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL {
5038  * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL enum
5041 typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL {
5047  * OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK enum
5050 typedef enum OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK {
5060  * OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL enum
5063 typedef enum OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL {
5077  * DC_DMCUB_INT_TYPE enum
5080 typedef enum DC_DMCUB_INT_TYPE {
5086  * DC_DMCUB_TIMER_WINDOW enum
5089 typedef enum DC_DMCUB_TIMER_WINDOW {
5105  * INVALID_REG_ACCESS_TYPE enum
5108 typedef enum INVALID_REG_ACCESS_TYPE {
5122  * DMU_DC_GPU_TIMER_READ_SELECT enum
5125 typedef enum DMU_DC_GPU_TIMER_READ_SELECT {
5221  * DMU_DC_GPU_TIMER_START_POSITION enum
5224 typedef enum DMU_DC_GPU_TIMER_START_POSITION {
5236  * IHC_INTERRUPT_DEST enum
5239 typedef enum IHC_INTERRUPT_DEST {
5245  * IHC_INTERRUPT_LINE_STATUS enum
5248 typedef enum IHC_INTERRUPT_LINE_STATUS {
5258  * DC_SMU_INTERRUPT_ENABLE enum
5261 typedef enum DC_SMU_INTERRUPT_ENABLE {
5267  * DMU_CLOCK_ON enum
5270 typedef enum DMU_CLOCK_ON {
5276  * SMU_INTR enum
5279 typedef enum SMU_INTR {
5289  * ALLOW_SR_ON_TRANS_REQ enum
5292 typedef enum ALLOW_SR_ON_TRANS_REQ {
5298  * AMCLOCK_ENABLE enum
5301 typedef enum AMCLOCK_ENABLE {
5307  * CLEAR_SMU_INTR enum
5310 typedef enum CLEAR_SMU_INTR {
5316  * CLOCK_BRANCH_SOFT_RESET enum
5319 typedef enum CLOCK_BRANCH_SOFT_RESET {
5325  * DCCG_AUDIO_DTO0_SOURCE_SEL enum
5328 typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL {
5337  * DCCG_AUDIO_DTO2_SOURCE_SEL enum
5340 typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL {
5346  * DCCG_AUDIO_DTO_SEL enum
5349 typedef enum DCCG_AUDIO_DTO_SEL {
5357  * DCCG_AUDIO_DTO_USE_512FBR_DTO enum
5360 typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO {
5366  * DCCG_DBG_BLOCK_SEL enum
5369 typedef enum DCCG_DBG_BLOCK_SEL {
5376  * DCCG_DBG_EN enum
5379 typedef enum DCCG_DBG_EN {
5385  * DCCG_DEEP_COLOR_CNTL enum
5388 typedef enum DCCG_DEEP_COLOR_CNTL {
5396  * DCCG_FIFO_ERRDET_OVR_EN enum
5399 typedef enum DCCG_FIFO_ERRDET_OVR_EN {
5405  * DCCG_FIFO_ERRDET_RESET enum
5408 typedef enum DCCG_FIFO_ERRDET_RESET {
5414  * DCCG_FIFO_ERRDET_STATE enum
5417 typedef enum DCCG_FIFO_ERRDET_STATE {
5423  * DCCG_PERF_MODE_HSYNC enum
5426 typedef enum DCCG_PERF_MODE_HSYNC {
5432  * DCCG_PERF_MODE_VSYNC enum
5435 typedef enum DCCG_PERF_MODE_VSYNC {
5441  * DCCG_PERF_OTG_SELECT enum
5444 typedef enum DCCG_PERF_OTG_SELECT {
5453  * DCCG_PERF_RUN enum
5456 typedef enum DCCG_PERF_RUN {
5462  * DC_MEM_GLOBAL_PWR_REQ_DIS enum
5465 typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS {
5471  * DIO_FIFO_ERROR enum
5474 typedef enum DIO_FIFO_ERROR {
5482  * DISABLE_CLOCK_GATING enum
5485 typedef enum DISABLE_CLOCK_GATING {
5491  * DISABLE_CLOCK_GATING_IN_DCO enum
5494 typedef enum DISABLE_CLOCK_GATING_IN_DCO {
5500  * DISPCLK_CHG_FWD_CORR_DISABLE enum
5503 typedef enum DISPCLK_CHG_FWD_CORR_DISABLE {
5509  * DISPCLK_FREQ_RAMP_DONE enum
5512 typedef enum DISPCLK_FREQ_RAMP_DONE {
5518  * DPREFCLK_SRC_SEL enum
5521 typedef enum DPREFCLK_SRC_SEL {
5529  * DP_DTO_DS_DISABLE enum
5532 typedef enum DP_DTO_DS_DISABLE {
5538  * DS_HW_CAL_ENABLE enum
5541 typedef enum DS_HW_CAL_ENABLE {
5547  * DS_JITTER_COUNT_SRC_SEL enum
5550 typedef enum DS_JITTER_COUNT_SRC_SEL {
5556  * DS_REF_SRC enum
5559 typedef enum DS_REF_SRC {
5566  * DVOACLKC_IN_PHASE enum
5569 typedef enum DVOACLKC_IN_PHASE {
5575  * DVOACLKC_MVP_IN_PHASE enum
5578 typedef enum DVOACLKC_MVP_IN_PHASE {
5584  * DVOACLKC_MVP_SKEW_PHASE_OVERRIDE enum
5587 typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE {
5593  * DVOACLKD_IN_PHASE enum
5596 typedef enum DVOACLKD_IN_PHASE {
5602  * DVOACLK_COARSE_SKEW_CNTL enum
5605 typedef enum DVOACLK_COARSE_SKEW_CNTL {
5640  * DVOACLK_FINE_SKEW_CNTL enum
5643 typedef enum DVOACLK_FINE_SKEW_CNTL {
5655  * DVO_ENABLE_RST enum
5658 typedef enum DVO_ENABLE_RST {
5664  * ENABLE enum
5667 typedef enum ENABLE {
5673  * ENABLE_CLOCK enum
5676 typedef enum ENABLE_CLOCK {
5682  * FORCE_DISABLE_CLOCK enum
5685 typedef enum FORCE_DISABLE_CLOCK {
5691  * HDMICHARCLK_SRC_SEL enum
5694 typedef enum HDMICHARCLK_SRC_SEL {
5704  * HDMISTREAMCLK_DTO_FORCE_DIS enum
5707 typedef enum HDMISTREAMCLK_DTO_FORCE_DIS {
5713  * HDMISTREAMCLK_SRC_SEL enum
5716 typedef enum HDMISTREAMCLK_SRC_SEL {
5723  * JITTER_REMOVE_DISABLE enum
5726 typedef enum JITTER_REMOVE_DISABLE {
5732  * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
5735 typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL {
5741  * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
5744 typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL {
5750  * OTG_ADD_PIXEL enum
5753 typedef enum OTG_ADD_PIXEL {
5759  * OTG_DROP_PIXEL enum
5762 typedef enum OTG_DROP_PIXEL {
5768  * PHYSYMCLK_FORCE_EN enum
5771 typedef enum PHYSYMCLK_FORCE_EN {
5777  * PHYSYMCLK_FORCE_SRC_SEL enum
5780 typedef enum PHYSYMCLK_FORCE_SRC_SEL {
5787  * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum
5790 typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE {
5799  * PIPE_PIXEL_RATE_PLL_SOURCE enum
5802 typedef enum PIPE_PIXEL_RATE_PLL_SOURCE {
5808  * PIPE_PIXEL_RATE_SOURCE enum
5811 typedef enum PIPE_PIXEL_RATE_SOURCE {
5818  * PLL_CFG_IF_SOFT_RESET enum
5821 typedef enum PLL_CFG_IF_SOFT_RESET {
5827  * SYMCLK_FE_FORCE_EN enum
5830 typedef enum SYMCLK_FE_FORCE_EN {
5836  * SYMCLK_FE_FORCE_SRC enum
5839 typedef enum SYMCLK_FE_FORCE_SRC {
5848  * TEST_CLK_DIV_SEL enum
5851 typedef enum TEST_CLK_DIV_SEL {
5859  * VSYNC_CNT_LATCH_MASK enum
5862 typedef enum VSYNC_CNT_LATCH_MASK {
5868  * VSYNC_CNT_RESET_SEL enum
5871 typedef enum VSYNC_CNT_RESET_SEL {
5877  * XTAL_REF_CLOCK_SOURCE_SEL enum
5880 typedef enum XTAL_REF_CLOCK_SOURCE_SEL {
5886  * XTAL_REF_SEL enum
5889 typedef enum XTAL_REF_SEL {
5899  * HPD_INT_CONTROL_ACK enum
5902 typedef enum HPD_INT_CONTROL_ACK {
5908  * HPD_INT_CONTROL_POLARITY enum
5911 typedef enum HPD_INT_CONTROL_POLARITY {
5917  * HPD_INT_CONTROL_RX_INT_ACK enum
5920 typedef enum HPD_INT_CONTROL_RX_INT_ACK {
5930  * DPHY_8B10B_CUR_DISP enum
5933 typedef enum DPHY_8B10B_CUR_DISP {
5939  * DPHY_8B10B_RESET enum
5942 typedef enum DPHY_8B10B_RESET {
5948  * DPHY_ALT_SCRAMBLER_RESET_EN enum
5951 typedef enum DPHY_ALT_SCRAMBLER_RESET_EN {
5957  * DPHY_ALT_SCRAMBLER_RESET_SEL enum
5960 typedef enum DPHY_ALT_SCRAMBLER_RESET_SEL {
5966  * DPHY_ATEST_SEL_LANE0 enum
5969 typedef enum DPHY_ATEST_SEL_LANE0 {
5975  * DPHY_ATEST_SEL_LANE1 enum
5978 typedef enum DPHY_ATEST_SEL_LANE1 {
5984  * DPHY_ATEST_SEL_LANE2 enum
5987 typedef enum DPHY_ATEST_SEL_LANE2 {
5993  * DPHY_ATEST_SEL_LANE3 enum
5996 typedef enum DPHY_ATEST_SEL_LANE3 {
6002  * DPHY_BYPASS enum
6005 typedef enum DPHY_BYPASS {
6011  * DPHY_CRC_CONT_EN enum
6014 typedef enum DPHY_CRC_CONT_EN {
6020  * DPHY_CRC_EN enum
6023 typedef enum DPHY_CRC_EN {
6029  * DPHY_CRC_FIELD enum
6032 typedef enum DPHY_CRC_FIELD {
6038  * DPHY_CRC_MST_PHASE_ERROR_ACK enum
6041 typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
6047  * DPHY_CRC_SEL enum
6050 typedef enum DPHY_CRC_SEL {
6058  * DPHY_FEC_ENABLE enum
6061 typedef enum DPHY_FEC_ENABLE {
6067  * DPHY_FEC_READY enum
6070 typedef enum DPHY_FEC_READY {
6076  * DPHY_LOAD_BS_COUNT_START enum
6079 typedef enum DPHY_LOAD_BS_COUNT_START {
6085  * DPHY_PRBS_EN enum
6088 typedef enum DPHY_PRBS_EN {
6094  * DPHY_PRBS_SEL enum
6097 typedef enum DPHY_PRBS_SEL {
6104  * DPHY_RX_FAST_TRAINING_CAPABLE enum
6107 typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
6113  * DPHY_SCRAMBLER_ADVANCE enum
6116 typedef enum DPHY_SCRAMBLER_ADVANCE {
6122  * DPHY_SCRAMBLER_DIS enum
6125 typedef enum DPHY_SCRAMBLER_DIS {
6131  * DPHY_SCRAMBLER_KCODE enum
6134 typedef enum DPHY_SCRAMBLER_KCODE {
6140  * DPHY_SCRAMBLER_SEL enum
6143 typedef enum DPHY_SCRAMBLER_SEL {
6149  * DPHY_SKEW_BYPASS enum
6152 typedef enum DPHY_SKEW_BYPASS {
6158  * DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM enum
6161 typedef enum DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM {
6167  * DPHY_SW_FAST_TRAINING_START enum
6170 typedef enum DPHY_SW_FAST_TRAINING_START {
6176  * DPHY_TRAINING_PATTERN_SEL enum
6179 typedef enum DPHY_TRAINING_PATTERN_SEL {
6187  * DP_COMPONENT_DEPTH enum
6190 typedef enum DP_COMPONENT_DEPTH {
6199  * DP_CP_ENCRYPTION_TYPE enum
6202 typedef enum DP_CP_ENCRYPTION_TYPE {
6208  * DP_DPHY_8B10B_EXT_DISP enum
6211 typedef enum DP_DPHY_8B10B_EXT_DISP {
6217  * DP_DPHY_FAST_TRAINING_COMPLETE_ACK enum
6220 typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
6226  * DP_DPHY_FAST_TRAINING_COMPLETE_MASK enum
6229 typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
6235  * DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN enum
6238 typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
6244  * DP_DPHY_HBR2_PATTERN_CONTROL_MODE enum
6247 typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
6256  * DP_DSC_MODE enum
6259 typedef enum DP_DSC_MODE {
6266  * DP_EMBEDDED_PANEL_MODE enum
6269 typedef enum DP_EMBEDDED_PANEL_MODE {
6275  * DP_LINK_TRAINING_COMPLETE enum
6278 typedef enum DP_LINK_TRAINING_COMPLETE {
6284  * DP_LINK_TRAINING_SWITCH_MODE enum
6287 typedef enum DP_LINK_TRAINING_SWITCH_MODE {
6293  * DP_ML_PHY_SEQ_MODE enum
6296 typedef enum DP_ML_PHY_SEQ_MODE {
6302  * DP_MSA_V_TIMING_OVERRIDE_EN enum
6305 typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
6311  * DP_MSE_BLANK_CODE enum
6314 typedef enum DP_MSE_BLANK_CODE {
6320  * DP_MSE_LINK_LINE enum
6323 typedef enum DP_MSE_LINK_LINE {
6331  * DP_MSE_SAT_ENCRYPT0 enum
6334 typedef enum DP_MSE_SAT_ENCRYPT0 {
6340  * DP_MSE_SAT_ENCRYPT1 enum
6343 typedef enum DP_MSE_SAT_ENCRYPT1 {
6349  * DP_MSE_SAT_ENCRYPT2 enum
6352 typedef enum DP_MSE_SAT_ENCRYPT2 {
6358  * DP_MSE_SAT_ENCRYPT3 enum
6361 typedef enum DP_MSE_SAT_ENCRYPT3 {
6367  * DP_MSE_SAT_ENCRYPT4 enum
6370 typedef enum DP_MSE_SAT_ENCRYPT4 {
6376  * DP_MSE_SAT_ENCRYPT5 enum
6379 typedef enum DP_MSE_SAT_ENCRYPT5 {
6385  * DP_MSE_SAT_UPDATE_ACT enum
6388 typedef enum DP_MSE_SAT_UPDATE_ACT {
6395  * DP_MSE_TIMESTAMP_MODE enum
6398 typedef enum DP_MSE_TIMESTAMP_MODE {
6404  * DP_MSE_ZERO_ENCODER enum
6407 typedef enum DP_MSE_ZERO_ENCODER {
6413  * DP_MSO_NUM_OF_SST_LINKS enum
6416 typedef enum DP_MSO_NUM_OF_SST_LINKS {
6423  * DP_PIXEL_ENCODING enum
6426 typedef enum DP_PIXEL_ENCODING {
6436  * DP_PIXEL_PER_CYCLE_PROCESSING_NUM enum
6439 typedef enum DP_PIXEL_PER_CYCLE_PROCESSING_NUM {
6445  * DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE enum
6448 typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
6454  * DP_SEC_ASP_PRIORITY enum
6457 typedef enum DP_SEC_ASP_PRIORITY {
6463  * DP_SEC_AUDIO_MUTE enum
6466 typedef enum DP_SEC_AUDIO_MUTE {
6472  * DP_SEC_COLLISION_ACK enum
6475 typedef enum DP_SEC_COLLISION_ACK {
6481  * DP_SEC_GSP0_PRIORITY enum
6484 typedef enum DP_SEC_GSP0_PRIORITY {
6490  * DP_SEC_GSP_SEND enum
6493 typedef enum DP_SEC_GSP_SEND {
6499  * DP_SEC_GSP_SEND_ANY_LINE enum
6502 typedef enum DP_SEC_GSP_SEND_ANY_LINE {
6508  * DP_SEC_GSP_SEND_PPS enum
6511 typedef enum DP_SEC_GSP_SEND_PPS {
6517  * DP_SEC_LINE_REFERENCE enum
6520 typedef enum DP_SEC_LINE_REFERENCE {
6526  * DP_SEC_TIMESTAMP_MODE enum
6529 typedef enum DP_SEC_TIMESTAMP_MODE {
6535  * DP_STEER_OVERFLOW_ACK enum
6538 typedef enum DP_STEER_OVERFLOW_ACK {
6544  * DP_STEER_OVERFLOW_MASK enum
6547 typedef enum DP_STEER_OVERFLOW_MASK {
6553  * DP_SYNC_POLARITY enum
6556 typedef enum DP_SYNC_POLARITY {
6562  * DP_TU_OVERFLOW_ACK enum
6565 typedef enum DP_TU_OVERFLOW_ACK {
6571  * DP_UDI_LANES enum
6574 typedef enum DP_UDI_LANES {
6582  * DP_VID_ENHANCED_FRAME_MODE enum
6585 typedef enum DP_VID_ENHANCED_FRAME_MODE {
6591  * DP_VID_M_N_DOUBLE_BUFFER_MODE enum
6594 typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
6600  * DP_VID_M_N_GEN_EN enum
6603 typedef enum DP_VID_M_N_GEN_EN {
6609  * DP_VID_N_MUL enum
6612 typedef enum DP_VID_N_MUL {
6620  * DP_VID_STREAM_DISABLE_ACK enum
6623 typedef enum DP_VID_STREAM_DISABLE_ACK {
6629  * DP_VID_STREAM_DISABLE_MASK enum
6632 typedef enum DP_VID_STREAM_DISABLE_MASK {
6638  * DP_VID_STREAM_DIS_DEFER enum
6641 typedef enum DP_VID_STREAM_DIS_DEFER {
6648  * DP_VID_VBID_FIELD_POL enum
6651 typedef enum DP_VID_VBID_FIELD_POL {
6657  * FEC_ACTIVE_STATUS enum
6660 typedef enum FEC_ACTIVE_STATUS {
6670  * DIG_BE_CNTL_HPD_SELECT enum
6673 typedef enum DIG_BE_CNTL_HPD_SELECT {
6683  * DIG_BE_CNTL_MODE enum
6686 typedef enum DIG_BE_CNTL_MODE {
6698  * DIG_DIGITAL_BYPASS_ENABLE enum
6701 typedef enum DIG_DIGITAL_BYPASS_ENABLE {
6707  * DIG_DIGITAL_BYPASS_SEL enum
6710 typedef enum DIG_DIGITAL_BYPASS_SEL {
6721  * DIG_FE_CNTL_SOURCE_SELECT enum
6724 typedef enum DIG_FE_CNTL_SOURCE_SELECT {
6733  * DIG_FE_CNTL_STEREOSYNC_SELECT enum
6736 typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
6745  * DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX enum
6748 typedef enum DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX {
6754  * DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL enum
6757 typedef enum DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL {
6763  * DIG_FIFO_FORCE_RECAL_AVERAGE enum
6766 typedef enum DIG_FIFO_FORCE_RECAL_AVERAGE {
6772  * DIG_FIFO_OUTPUT_PROCESSING_MODE enum
6775 typedef enum DIG_FIFO_OUTPUT_PROCESSING_MODE {
6781  * DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR enum
6784 typedef enum DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR {
6791  * DIG_FIFO_READ_CLOCK_SRC enum
6794 typedef enum DIG_FIFO_READ_CLOCK_SRC {
6800  * DIG_INPUT_PIXEL_SEL enum
6803 typedef enum DIG_INPUT_PIXEL_SEL {
6810  * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum
6813 typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
6819  * DIG_OUTPUT_CRC_DATA_SEL enum
6822 typedef enum DIG_OUTPUT_CRC_DATA_SEL {
6830  * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum
6833 typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
6839  * DIG_SL_PIXEL_GROUPING enum
6842 typedef enum DIG_SL_PIXEL_GROUPING {
6848  * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum
6851 typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
6857  * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum
6860 typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
6866  * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum
6869 typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
6875  * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum
6878 typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
6884  * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum
6887 typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
6893  * DOLBY_VISION_ENABLE enum
6896 typedef enum DOLBY_VISION_ENABLE {
6902  * HDMI_ACP_SEND enum
6905 typedef enum HDMI_ACP_SEND {
6911  * HDMI_ACR_AUDIO_PRIORITY enum
6914 typedef enum HDMI_ACR_AUDIO_PRIORITY {
6920  * HDMI_ACR_CONT enum
6923 typedef enum HDMI_ACR_CONT {
6929  * HDMI_ACR_N_MULTIPLE enum
6932 typedef enum HDMI_ACR_N_MULTIPLE {
6944  * HDMI_ACR_SELECT enum
6947 typedef enum HDMI_ACR_SELECT {
6955  * HDMI_ACR_SEND enum
6958 typedef enum HDMI_ACR_SEND {
6964  * HDMI_ACR_SOURCE enum
6967 typedef enum HDMI_ACR_SOURCE {
6973  * HDMI_AUDIO_DELAY_EN enum
6976 typedef enum HDMI_AUDIO_DELAY_EN {
6984  * HDMI_AUDIO_INFO_CONT enum
6987 typedef enum HDMI_AUDIO_INFO_CONT {
6993  * HDMI_AUDIO_INFO_SEND enum
6996 typedef enum HDMI_AUDIO_INFO_SEND {
7002  * HDMI_CLOCK_CHANNEL_RATE enum
7005 typedef enum HDMI_CLOCK_CHANNEL_RATE {
7011  * HDMI_DATA_SCRAMBLE_EN enum
7014 typedef enum HDMI_DATA_SCRAMBLE_EN {
7020  * HDMI_DEEP_COLOR_DEPTH enum
7023 typedef enum HDMI_DEEP_COLOR_DEPTH {
7031  * HDMI_DEFAULT_PAHSE enum
7034 typedef enum HDMI_DEFAULT_PAHSE {
7040  * HDMI_ERROR_ACK enum
7043 typedef enum HDMI_ERROR_ACK {
7049  * HDMI_ERROR_MASK enum
7052 typedef enum HDMI_ERROR_MASK {
7058  * HDMI_GC_AVMUTE enum
7061 typedef enum HDMI_GC_AVMUTE {
7067  * HDMI_GC_AVMUTE_CONT enum
7070 typedef enum HDMI_GC_AVMUTE_CONT {
7076  * HDMI_GC_CONT enum
7079 typedef enum HDMI_GC_CONT {
7085  * HDMI_GC_SEND enum
7088 typedef enum HDMI_GC_SEND {
7094  * HDMI_GENERIC_CONT enum
7097 typedef enum HDMI_GENERIC_CONT {
7103  * HDMI_GENERIC_SEND enum
7106 typedef enum HDMI_GENERIC_SEND {
7112  * HDMI_ISRC_CONT enum
7115 typedef enum HDMI_ISRC_CONT {
7121  * HDMI_ISRC_SEND enum
7124 typedef enum HDMI_ISRC_SEND {
7130  * HDMI_KEEPOUT_MODE enum
7133 typedef enum HDMI_KEEPOUT_MODE {
7139  * HDMI_METADATA_ENABLE enum
7142 typedef enum HDMI_METADATA_ENABLE {
7148  * HDMI_MPEG_INFO_CONT enum
7151 typedef enum HDMI_MPEG_INFO_CONT {
7157  * HDMI_MPEG_INFO_SEND enum
7160 typedef enum HDMI_MPEG_INFO_SEND {
7166  * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum
7169 typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
7175  * HDMI_NULL_SEND enum
7178 typedef enum HDMI_NULL_SEND {
7184  * HDMI_PACKET_GEN_VERSION enum
7187 typedef enum HDMI_PACKET_GEN_VERSION {
7193  * HDMI_PACKET_LINE_REFERENCE enum
7196 typedef enum HDMI_PACKET_LINE_REFERENCE {
7202  * HDMI_PACKING_PHASE_OVERRIDE enum
7205 typedef enum HDMI_PACKING_PHASE_OVERRIDE {
7211  * LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum
7214 typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
7220  * TMDS_COLOR_FORMAT enum
7223 typedef enum TMDS_COLOR_FORMAT {
7231  * TMDS_CTL0_DATA_INVERT enum
7234 typedef enum TMDS_CTL0_DATA_INVERT {
7240  * TMDS_CTL0_DATA_MODULATION enum
7243 typedef enum TMDS_CTL0_DATA_MODULATION {
7251  * TMDS_CTL0_DATA_SEL enum
7254 typedef enum TMDS_CTL0_DATA_SEL {
7266  * TMDS_CTL0_PATTERN_OUT_EN enum
7269 typedef enum TMDS_CTL0_PATTERN_OUT_EN {
7275  * TMDS_CTL1_DATA_INVERT enum
7278 typedef enum TMDS_CTL1_DATA_INVERT {
7284  * TMDS_CTL1_DATA_MODULATION enum
7287 typedef enum TMDS_CTL1_DATA_MODULATION {
7295  * TMDS_CTL1_DATA_SEL enum
7298 typedef enum TMDS_CTL1_DATA_SEL {
7310  * TMDS_CTL1_PATTERN_OUT_EN enum
7313 typedef enum TMDS_CTL1_PATTERN_OUT_EN {
7319  * TMDS_CTL2_DATA_INVERT enum
7322 typedef enum TMDS_CTL2_DATA_INVERT {
7328  * TMDS_CTL2_DATA_MODULATION enum
7331 typedef enum TMDS_CTL2_DATA_MODULATION {
7339  * TMDS_CTL2_DATA_SEL enum
7342 typedef enum TMDS_CTL2_DATA_SEL {
7354  * TMDS_CTL2_PATTERN_OUT_EN enum
7357 typedef enum TMDS_CTL2_PATTERN_OUT_EN {
7363  * TMDS_CTL3_DATA_INVERT enum
7366 typedef enum TMDS_CTL3_DATA_INVERT {
7372  * TMDS_CTL3_DATA_MODULATION enum
7375 typedef enum TMDS_CTL3_DATA_MODULATION {
7383  * TMDS_CTL3_DATA_SEL enum
7386 typedef enum TMDS_CTL3_DATA_SEL {
7398  * TMDS_CTL3_PATTERN_OUT_EN enum
7401 typedef enum TMDS_CTL3_PATTERN_OUT_EN {
7407  * TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum
7410 typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
7416  * TMDS_PIXEL_ENCODING enum
7419 typedef enum TMDS_PIXEL_ENCODING {
7425  * TMDS_REG_TEST_OUTPUTA_CNTLA enum
7428 typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
7436  * TMDS_REG_TEST_OUTPUTB_CNTLB enum
7439 typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
7447  * TMDS_STEREOSYNC_CTL_SEL_REG enum
7450 typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
7458  * TMDS_SYNC_PHASE enum
7461 typedef enum TMDS_SYNC_PHASE {
7467  * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum
7470 typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
7476  * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum
7479 typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
7485  * TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum
7488 typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
7494  * TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum
7497 typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
7503  * TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum
7506 typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
7512  * TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum
7515 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
7523  * TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum
7526 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
7532  * TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum
7535 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
7541  * TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum
7544 typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
7550  * TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum
7553 typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
7559  * TMDS_TRANSMITTER_ENABLE_HPD_MASK enum
7562 typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
7568  * TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum
7571 typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
7577  * TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum
7580 typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
7590  * DP_AUX_ARB_CONTROL_ARB_PRIORITY enum
7593 typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
7601  * DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG enum
7604 typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
7610  * DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ enum
7613 typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
7619  * DP_AUX_ARB_STATUS enum
7622 typedef enum DP_AUX_ARB_STATUS {
7631  * DP_AUX_CONTROL_HPD_SEL enum
7634 typedef enum DP_AUX_CONTROL_HPD_SEL {
7644  * DP_AUX_CONTROL_TEST_MODE enum
7647 typedef enum DP_AUX_CONTROL_TEST_MODE {
7653  * DP_AUX_DEFINITE_ERR_REACHED_ACK enum
7656 typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
7662  * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT enum
7665 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
7671  * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START enum
7674 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
7680  * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP enum
7683 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
7689  * DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN enum
7692 typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
7700  * DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN enum
7703 typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
7711  * DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW enum
7714 typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
7726  * DP_AUX_DPHY_RX_CONTROL_START_WINDOW enum
7729 typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
7741  * DP_AUX_DPHY_RX_DETECTION_THRESHOLD enum
7744 typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
7756  * DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY enum
7759 typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
7769  * DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE enum
7772 typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
7780  * DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL enum
7783 typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
7789  * DP_AUX_ERR_OCCURRED_ACK enum
7792 typedef enum DP_AUX_ERR_OCCURRED_ACK {
7798  * DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ enum
7801 typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
7807  * DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW enum
7810 typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
7818  * DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT enum
7821 typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
7829  * DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN enum
7832 typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
7840  * DP_AUX_INT_ACK enum
7843 typedef enum DP_AUX_INT_ACK {
7849  * DP_AUX_LS_UPDATE_ACK enum
7852 typedef enum DP_AUX_LS_UPDATE_ACK {
7858  * DP_AUX_PHY_WAKE_PRIORITY enum
7861 typedef enum DP_AUX_PHY_WAKE_PRIORITY {
7867  * DP_AUX_POTENTIAL_ERR_REACHED_ACK enum
7870 typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
7876  * DP_AUX_RESET enum
7879 typedef enum DP_AUX_RESET {
7885  * DP_AUX_RESET_DONE enum
7888 typedef enum DP_AUX_RESET_DONE {
7894  * DP_AUX_RX_TIMEOUT_LEN_MUL enum
7897 typedef enum DP_AUX_RX_TIMEOUT_LEN_MUL {
7905  * DP_AUX_SW_CONTROL_LS_READ_TRIG enum
7908 typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
7914  * DP_AUX_SW_CONTROL_SW_GO enum
7917 typedef enum DP_AUX_SW_CONTROL_SW_GO {
7923  * DP_AUX_TX_PRECHARGE_LEN_MUL enum
7926 typedef enum DP_AUX_TX_PRECHARGE_LEN_MUL {
7938  * DOUT_I2C_ACK enum
7941 typedef enum DOUT_I2C_ACK {
7947  * DOUT_I2C_ARBITRATION_ABORT_XFER enum
7950 typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
7956  * DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG enum
7959 typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
7965  * DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO enum
7968 typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
7974  * DOUT_I2C_ARBITRATION_SW_PRIORITY enum
7977 typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
7985  * DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ enum
7988 typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
7994  * DOUT_I2C_CONTROL_DBG_REF_SEL enum
7997 typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL {
8003  * DOUT_I2C_CONTROL_DDC_SELECT enum
8006 typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
8016  * DOUT_I2C_CONTROL_GO enum
8019 typedef enum DOUT_I2C_CONTROL_GO {
8025  * DOUT_I2C_CONTROL_SEND_RESET enum
8028 typedef enum DOUT_I2C_CONTROL_SEND_RESET {
8034  * DOUT_I2C_CONTROL_SEND_RESET_LENGTH enum
8037 typedef enum DOUT_I2C_CONTROL_SEND_RESET_LENGTH {
8043  * DOUT_I2C_CONTROL_SOFT_RESET enum
8046 typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
8052  * DOUT_I2C_CONTROL_SW_STATUS_RESET enum
8055 typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
8061  * DOUT_I2C_CONTROL_TRANSACTION_COUNT enum
8064 typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
8072  * DOUT_I2C_DATA_INDEX_WRITE enum
8075 typedef enum DOUT_I2C_DATA_INDEX_WRITE {
8081  * DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN enum
8084 typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
8090  * DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN enum
8093 typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
8099  * DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL enum
8102 typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
8108  * DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE enum
8111 typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
8117  * DOUT_I2C_DDC_SPEED_THRESHOLD enum
8120 typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
8128  * DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET enum
8131 typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
8137  * DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE enum
8140 typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
8146  * DOUT_I2C_TRANSACTION_STOP_ON_NACK enum
8149 typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
8159  * CLOCK_GATING_EN enum
8162 typedef enum CLOCK_GATING_EN {
8168  * DAC_MUX_SELECT enum
8171 typedef enum DAC_MUX_SELECT {
8177  * DIOMEM_PWR_DIS_CTRL enum
8180 typedef enum DIOMEM_PWR_DIS_CTRL {
8186  * DIOMEM_PWR_FORCE_CTRL enum
8189 typedef enum DIOMEM_PWR_FORCE_CTRL {
8197  * DIOMEM_PWR_FORCE_CTRL2 enum
8200 typedef enum DIOMEM_PWR_FORCE_CTRL2 {
8206  * DIOMEM_PWR_SEL_CTRL enum
8209 typedef enum DIOMEM_PWR_SEL_CTRL {
8216  * DIOMEM_PWR_SEL_CTRL2 enum
8219 typedef enum DIOMEM_PWR_SEL_CTRL2 {
8225  * DIO_DBG_BLOCK_SEL enum
8228 typedef enum DIO_DBG_BLOCK_SEL {
8260  * DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE enum
8263 typedef enum DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE {
8269  * DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE enum
8272 typedef enum DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE {
8278  * ENUM_DIO_DCN_ACTIVE_STATUS enum
8281 typedef enum ENUM_DIO_DCN_ACTIVE_STATUS {
8287  * GENERIC_STEREOSYNC_SEL enum
8290 typedef enum GENERIC_STEREOSYNC_SEL {
8299  * PM_ASSERT_RESET enum
8302 typedef enum PM_ASSERT_RESET {
8308  * SOFT_RESET enum
8311 typedef enum SOFT_RESET {
8317  * TMDS_MUX_SELECT enum
8320 typedef enum TMDS_MUX_SELECT {
8332  * DME_MEM_POWER_STATE_ENUM enum
8335 typedef enum DME_MEM_POWER_STATE_ENUM {
8343  * DME_MEM_PWR_DIS_CTRL enum
8346 typedef enum DME_MEM_PWR_DIS_CTRL {
8352  * DME_MEM_PWR_FORCE_CTRL enum
8355 typedef enum DME_MEM_PWR_FORCE_CTRL {
8363  * METADATA_HUBP_SEL enum
8366 typedef enum METADATA_HUBP_SEL {
8375  * METADATA_STREAM_TYPE_SEL enum
8378 typedef enum METADATA_STREAM_TYPE_SEL {
8388  * VPG_MEM_PWR_DIS_CTRL enum
8391 typedef enum VPG_MEM_PWR_DIS_CTRL {
8397  * VPG_MEM_PWR_FORCE_CTRL enum
8400 typedef enum VPG_MEM_PWR_FORCE_CTRL {
8410  * AFMT_ACP_TYPE enum
8413 typedef enum AFMT_ACP_TYPE {
8421  * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum
8424 typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
8444  * AFMT_AUDIO_CRC_CONTROL_CONT enum
8447 typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
8453  * AFMT_AUDIO_CRC_CONTROL_SOURCE enum
8456 typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
8462  * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum
8465 typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
8471  * AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum
8474 typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
8480  * AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum
8483 typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
8489  * AFMT_AUDIO_SRC_CONTROL_SELECT enum
8492 typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
8502  * AFMT_HDMI_AUDIO_SEND_MAX_PACKETS enum
8505 typedef enum AFMT_HDMI_AUDIO_SEND_MAX_PACKETS {
8511  * AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum
8514 typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
8520  * AFMT_INTERRUPT_STATUS_CHG_MASK enum
8523 typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
8529  * AFMT_MEM_PWR_DIS_CTRL enum
8532 typedef enum AFMT_MEM_PWR_DIS_CTRL {
8538  * AFMT_MEM_PWR_FORCE_CTRL enum
8541 typedef enum AFMT_MEM_PWR_FORCE_CTRL {
8549  * AFMT_RAMP_CONTROL0_SIGN enum
8552 typedef enum AFMT_RAMP_CONTROL0_SIGN {
8558  * AFMT_VBI_PACKET_CONTROL_ACP_SOURCE enum
8561 typedef enum AFMT_VBI_PACKET_CONTROL_ACP_SOURCE {
8567  * AUDIO_LAYOUT_SELECT enum
8570 typedef enum AUDIO_LAYOUT_SELECT {
8580  * HPO_TOP_CLOCK_GATING_DISABLE enum
8583 typedef enum HPO_TOP_CLOCK_GATING_DISABLE {
8589  * HPO_TOP_TEST_CLK_SEL enum
8592 typedef enum HPO_TOP_TEST_CLK_SEL {
8612  * DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET enum
8615 typedef enum DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET {
8626  * HDMI_STREAM_ENC_DB_DISABLE_CONTROL enum
8629 typedef enum HDMI_STREAM_ENC_DB_DISABLE_CONTROL {
8635  * HDMI_STREAM_ENC_DSC_MODE enum
8638 typedef enum HDMI_STREAM_ENC_DSC_MODE {
8645  * HDMI_STREAM_ENC_ENABLE_CONTROL enum
8648 typedef enum HDMI_STREAM_ENC_ENABLE_CONTROL {
8654  * HDMI_STREAM_ENC_ODM_COMBINE_MODE enum
8657 typedef enum HDMI_STREAM_ENC_ODM_COMBINE_MODE {
8665  * HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR enum
8668 typedef enum HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR {
8675  * HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT enum
8678 typedef enum HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT {
8684  * HDMI_STREAM_ENC_PIXEL_ENCODING enum
8687 typedef enum HDMI_STREAM_ENC_PIXEL_ENCODING {
8694  * HDMI_STREAM_ENC_READ_CLOCK_CONTROL enum
8697 typedef enum HDMI_STREAM_ENC_READ_CLOCK_CONTROL {
8703  * HDMI_STREAM_ENC_RESET_CONTROL enum
8706 typedef enum HDMI_STREAM_ENC_RESET_CONTROL {
8712  * HDMI_STREAM_ENC_STREAM_ACTIVE enum
8715 typedef enum HDMI_STREAM_ENC_STREAM_ACTIVE {
8725  * BORROWBUFFER_MEM_POWER_STATE_ENUM enum
8728 typedef enum BORROWBUFFER_MEM_POWER_STATE_ENUM {
8736  * HDMI_BORROW_MODE enum
8739 typedef enum HDMI_BORROW_MODE {
8747  * HDMI_TB_ENC_ACP_SEND enum
8750 typedef enum HDMI_TB_ENC_ACP_SEND {
8756  * HDMI_TB_ENC_ACR_AUDIO_PRIORITY enum
8759 typedef enum HDMI_TB_ENC_ACR_AUDIO_PRIORITY {
8765  * HDMI_TB_ENC_ACR_CONT enum
8768 typedef enum HDMI_TB_ENC_ACR_CONT {
8774  * HDMI_TB_ENC_ACR_N_MULTIPLE enum
8777 typedef enum HDMI_TB_ENC_ACR_N_MULTIPLE {
8789  * HDMI_TB_ENC_ACR_SELECT enum
8792 typedef enum HDMI_TB_ENC_ACR_SELECT {
8800  * HDMI_TB_ENC_ACR_SEND enum
8803 typedef enum HDMI_TB_ENC_ACR_SEND {
8809  * HDMI_TB_ENC_ACR_SOURCE enum
8812 typedef enum HDMI_TB_ENC_ACR_SOURCE {
8818  * HDMI_TB_ENC_AUDIO_INFO_CONT enum
8821 typedef enum HDMI_TB_ENC_AUDIO_INFO_CONT {
8827  * HDMI_TB_ENC_AUDIO_INFO_SEND enum
8830 typedef enum HDMI_TB_ENC_AUDIO_INFO_SEND {
8836  * HDMI_TB_ENC_CRC_SRC_SEL enum
8839 typedef enum HDMI_TB_ENC_CRC_SRC_SEL {
8847  * HDMI_TB_ENC_CRC_TYPE enum
8850 typedef enum HDMI_TB_ENC_CRC_TYPE {
8858  * HDMI_TB_ENC_DEEP_COLOR_DEPTH enum
8861 typedef enum HDMI_TB_ENC_DEEP_COLOR_DEPTH {
8869  * HDMI_TB_ENC_DEFAULT_PAHSE enum
8872 typedef enum HDMI_TB_ENC_DEFAULT_PAHSE {
8878  * HDMI_TB_ENC_DSC_MODE enum
8881 typedef enum HDMI_TB_ENC_DSC_MODE {
8888  * HDMI_TB_ENC_ENABLE enum
8891 typedef enum HDMI_TB_ENC_ENABLE {
8897  * HDMI_TB_ENC_GC_AVMUTE enum
8900 typedef enum HDMI_TB_ENC_GC_AVMUTE {
8906  * HDMI_TB_ENC_GC_AVMUTE_CONT enum
8909 typedef enum HDMI_TB_ENC_GC_AVMUTE_CONT {
8915  * HDMI_TB_ENC_GC_CONT enum
8918 typedef enum HDMI_TB_ENC_GC_CONT {
8924  * HDMI_TB_ENC_GC_SEND enum
8927 typedef enum HDMI_TB_ENC_GC_SEND {
8933  * HDMI_TB_ENC_GENERIC_CONT enum
8936 typedef enum HDMI_TB_ENC_GENERIC_CONT {
8942  * HDMI_TB_ENC_GENERIC_LOCK_EN enum
8945 typedef enum HDMI_TB_ENC_GENERIC_LOCK_EN {
8951  * HDMI_TB_ENC_GENERIC_SEND enum
8954 typedef enum HDMI_TB_ENC_GENERIC_SEND {
8960  * HDMI_TB_ENC_ISRC_CONT enum
8963 typedef enum HDMI_TB_ENC_ISRC_CONT {
8969  * HDMI_TB_ENC_ISRC_SEND enum
8972 typedef enum HDMI_TB_ENC_ISRC_SEND {
8978  * HDMI_TB_ENC_METADATA_ENABLE enum
8981 typedef enum HDMI_TB_ENC_METADATA_ENABLE {
8987  * HDMI_TB_ENC_PACKET_LINE_REFERENCE enum
8990 typedef enum HDMI_TB_ENC_PACKET_LINE_REFERENCE {
8996  * HDMI_TB_ENC_PIXEL_ENCODING enum
8999 typedef enum HDMI_TB_ENC_PIXEL_ENCODING {
9006  * HDMI_TB_ENC_RESET enum
9009 typedef enum HDMI_TB_ENC_RESET {
9015  * HDMI_TB_ENC_SYNC_PHASE enum
9018 typedef enum HDMI_TB_ENC_SYNC_PHASE {
9024  * INPUT_FIFO_ERROR_TYPE enum
9027 typedef enum INPUT_FIFO_ERROR_TYPE {
9037  * DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR enum
9040 typedef enum DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR {
9047  * DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT enum
9050 typedef enum DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT {
9056  * DP_STREAM_ENC_READ_CLOCK_CONTROL enum
9059 typedef enum DP_STREAM_ENC_READ_CLOCK_CONTROL {
9065  * DP_STREAM_ENC_RESET_CONTROL enum
9068 typedef enum DP_STREAM_ENC_RESET_CONTROL {
9074  * DP_STREAM_ENC_STREAM_ACTIVE enum
9077 typedef enum DP_STREAM_ENC_STREAM_ACTIVE {
9087  * ENUM_DP_SYM32_ENC_AUDIO_MUTE enum
9090 typedef enum ENUM_DP_SYM32_ENC_AUDIO_MUTE {
9096  * ENUM_DP_SYM32_ENC_CONTINUOUS_MODE enum
9099 typedef enum ENUM_DP_SYM32_ENC_CONTINUOUS_MODE {
9105  * ENUM_DP_SYM32_ENC_CRC_VALID enum
9108 typedef enum ENUM_DP_SYM32_ENC_CRC_VALID {
9114  * ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH enum
9117 typedef enum ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH {
9125  * ENUM_DP_SYM32_ENC_ENABLE enum
9128 typedef enum ENUM_DP_SYM32_ENC_ENABLE {
9134  * ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED enum
9137 typedef enum ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED {
9143  * ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION enum
9146 typedef enum ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION {
9152  * ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE enum
9155 typedef enum ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE {
9163  * ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING enum
9166 typedef enum ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING {
9172  * ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM enum
9175 typedef enum ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM {
9183  * ENUM_DP_SYM32_ENC_OVERFLOW_STATUS enum
9186 typedef enum ENUM_DP_SYM32_ENC_OVERFLOW_STATUS {
9192  * ENUM_DP_SYM32_ENC_PENDING enum
9195 typedef enum ENUM_DP_SYM32_ENC_PENDING {
9201  * ENUM_DP_SYM32_ENC_PIXEL_ENCODING enum
9204 typedef enum ENUM_DP_SYM32_ENC_PIXEL_ENCODING {
9212  * ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE enum
9215 typedef enum ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE {
9221  * ENUM_DP_SYM32_ENC_POWER_STATE_ENUM enum
9224 typedef enum ENUM_DP_SYM32_ENC_POWER_STATE_ENUM {
9232  * ENUM_DP_SYM32_ENC_RESET enum
9235 typedef enum ENUM_DP_SYM32_ENC_RESET {
9241  * ENUM_DP_SYM32_ENC_SDP_PRIORITY enum
9244 typedef enum ENUM_DP_SYM32_ENC_SDP_PRIORITY {
9250  * ENUM_DP_SYM32_ENC_SOF_REFERENCE enum
9253 typedef enum ENUM_DP_SYM32_ENC_SOF_REFERENCE {
9259  * ENUM_DP_SYM32_ENC_VID_STREAM_DEFER enum
9262 typedef enum ENUM_DP_SYM32_ENC_VID_STREAM_DEFER {
9273  * ENUM_DP_DPHY_SYM32_CRC_END_EVENT enum
9276 typedef enum ENUM_DP_DPHY_SYM32_CRC_END_EVENT {
9284  * ENUM_DP_DPHY_SYM32_CRC_START_EVENT enum
9287 typedef enum ENUM_DP_DPHY_SYM32_CRC_START_EVENT {
9296  * ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE enum
9299 typedef enum ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE {
9306  * ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS enum
9309 typedef enum ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS {
9315  * ENUM_DP_DPHY_SYM32_ENABLE enum
9318 typedef enum ENUM_DP_DPHY_SYM32_ENABLE {
9324  * ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE enum
9327 typedef enum ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE {
9333  * ENUM_DP_DPHY_SYM32_MODE enum
9336 typedef enum ENUM_DP_DPHY_SYM32_MODE {
9344  * ENUM_DP_DPHY_SYM32_NUM_LANES enum
9347 typedef enum ENUM_DP_DPHY_SYM32_NUM_LANES {
9355  * ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING enum
9358 typedef enum ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING {
9364  * ENUM_DP_DPHY_SYM32_RESET enum
9367 typedef enum ENUM_DP_DPHY_SYM32_RESET {
9373  * ENUM_DP_DPHY_SYM32_RESET_STATUS enum
9376 typedef enum ENUM_DP_DPHY_SYM32_RESET_STATUS {
9382  * ENUM_DP_DPHY_SYM32_SAT_UPDATE enum
9385 typedef enum ENUM_DP_DPHY_SYM32_SAT_UPDATE {
9392  * ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING enum
9395 typedef enum ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING {
9402  * ENUM_DP_DPHY_SYM32_STATUS enum
9405 typedef enum ENUM_DP_DPHY_SYM32_STATUS {
9411  * ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE enum
9414 typedef enum ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE {
9421  * ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE enum
9424 typedef enum ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE {
9430  * ENUM_DP_DPHY_SYM32_TP_PRBS_SEL enum
9433 typedef enum ENUM_DP_DPHY_SYM32_TP_PRBS_SEL {
9443  * ENUM_DP_DPHY_SYM32_TP_SELECT enum
9446 typedef enum ENUM_DP_DPHY_SYM32_TP_SELECT {
9459  * APG_AUDIO_CRC_CONTROL_CH_SEL enum
9462 typedef enum APG_AUDIO_CRC_CONTROL_CH_SEL {
9482  * APG_AUDIO_CRC_CONTROL_CONT enum
9485 typedef enum APG_AUDIO_CRC_CONTROL_CONT {
9491  * APG_DBG_ACP_TYPE enum
9494 typedef enum APG_DBG_ACP_TYPE {
9502  * APG_DBG_AUDIO_DTO_BASE enum
9505 typedef enum APG_DBG_AUDIO_DTO_BASE {
9511  * APG_DBG_AUDIO_DTO_DIV enum
9514 typedef enum APG_DBG_AUDIO_DTO_DIV {
9526  * APG_DBG_AUDIO_DTO_MULTI enum
9529 typedef enum APG_DBG_AUDIO_DTO_MULTI {
9538  * APG_DBG_MUX_SEL enum
9541 typedef enum APG_DBG_MUX_SEL {
9547  * APG_DP_ASP_CHANNEL_COUNT_OVERRIDE enum
9550 typedef enum APG_DP_ASP_CHANNEL_COUNT_OVERRIDE {
9556  * APG_MEM_POWER_STATE enum
9559 typedef enum APG_MEM_POWER_STATE {
9567  * APG_MEM_PWR_DIS_CTRL enum
9570 typedef enum APG_MEM_PWR_DIS_CTRL {
9576  * APG_MEM_PWR_FORCE_CTRL enum
9579 typedef enum APG_MEM_PWR_FORCE_CTRL {
9587  * APG_PACKET_CONTROL_ACP_SOURCE enum
9590 typedef enum APG_PACKET_CONTROL_ACP_SOURCE {
9596  * APG_PACKET_CONTROL_AUDIO_INFO_SOURCE enum
9599 typedef enum APG_PACKET_CONTROL_AUDIO_INFO_SOURCE {
9605  * APG_RAMP_CONTROL_SIGN enum
9608 typedef enum APG_RAMP_CONTROL_SIGN {
9618  * DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL enum
9621 typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
9631  * DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL enum
9634 typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
9641  * DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS enum
9644 typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
9650  * DCIO_DBG_ASYNC_4BIT_SEL enum
9653 typedef enum DCIO_DBG_ASYNC_4BIT_SEL {
9665  * DCIO_DBG_ASYNC_BLOCK_SEL enum
9668 typedef enum DCIO_DBG_ASYNC_BLOCK_SEL {
9676  * DCIO_DCRXPHY_SOFT_RESET enum
9679 typedef enum DCIO_DCRXPHY_SOFT_RESET {
9685  * DCIO_DC_GENERICA_SEL enum
9688 typedef enum DCIO_DC_GENERICA_SEL {
9695  * DCIO_DC_GENERICB_SEL enum
9698 typedef enum DCIO_DC_GENERICB_SEL {
9705  * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL enum
9708 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
9719  * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL enum
9722 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
9733  * DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL enum
9736 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
9747  * DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL enum
9750 typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
9761  * DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE enum
9764 typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
9770  * DCIO_DC_GPU_TIMER_READ_SELECT enum
9773 typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
9783  * DCIO_DC_GPU_TIMER_START_POSITION enum
9786 typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
9798  * DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL enum
9801 typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
9809  * DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL enum
9812 typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
9820  * DCIO_DIO_EXT_VSYNC_MASK enum
9823 typedef enum DCIO_DIO_EXT_VSYNC_MASK {
9835  * DCIO_DIO_OTG_EXT_VSYNC_MUX enum
9838 typedef enum DCIO_DIO_OTG_EXT_VSYNC_MUX {
9850  * DCIO_DPCS_INTERRUPT_MASK enum
9853 typedef enum DCIO_DPCS_INTERRUPT_MASK {
9859  * DCIO_DPCS_INTERRUPT_TYPE enum
9862 typedef enum DCIO_DPCS_INTERRUPT_TYPE {
9868  * DCIO_DSYNC_SOFT_RESET enum
9871 typedef enum DCIO_DSYNC_SOFT_RESET {
9877  * DCIO_GENLK_CLK_GSL_MASK enum
9880 typedef enum DCIO_GENLK_CLK_GSL_MASK {
9887  * DCIO_GENLK_VSYNC_GSL_MASK enum
9890 typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
9897  * DCIO_GSL_SEL enum
9900 typedef enum DCIO_GSL_SEL {
9907  * DCIO_PHY_HPO_ENC_SRC_SEL enum
9910 typedef enum DCIO_PHY_HPO_ENC_SRC_SEL {
9916  * DCIO_SWAPLOCK_A_GSL_MASK enum
9919 typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
9926  * DCIO_SWAPLOCK_B_GSL_MASK enum
9929 typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
9936  * DCIO_UNIPHY_CHANNEL_XBAR_SOURCE enum
9939 typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
9947  * DCIO_UNIPHY_IMPCAL_SEL enum
9950 typedef enum DCIO_UNIPHY_IMPCAL_SEL {
9956  * DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT enum
9959 typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
9965  * DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK enum
9968 typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
9980  * DCIOCHIP_AUX_ALL_PWR_OK enum
9983 typedef enum DCIOCHIP_AUX_ALL_PWR_OK {
9989  * DCIOCHIP_AUX_CSEL0P9 enum
9992 typedef enum DCIOCHIP_AUX_CSEL0P9 {
9998  * DCIOCHIP_AUX_CSEL1P1 enum
10001 typedef enum DCIOCHIP_AUX_CSEL1P1 {
10007  * DCIOCHIP_AUX_FALLSLEWSEL enum
10010 typedef enum DCIOCHIP_AUX_FALLSLEWSEL {
10018  * DCIOCHIP_AUX_HYS_TUNE enum
10021 typedef enum DCIOCHIP_AUX_HYS_TUNE {
10029  * DCIOCHIP_AUX_RECEIVER_SEL enum
10032 typedef enum DCIOCHIP_AUX_RECEIVER_SEL {
10040  * DCIOCHIP_AUX_RSEL0P9 enum
10043 typedef enum DCIOCHIP_AUX_RSEL0P9 {
10049  * DCIOCHIP_AUX_RSEL1P1 enum
10052 typedef enum DCIOCHIP_AUX_RSEL1P1 {
10058  * DCIOCHIP_AUX_SPIKESEL enum
10061 typedef enum DCIOCHIP_AUX_SPIKESEL {
10067  * DCIOCHIP_AUX_VOD_TUNE enum
10070 typedef enum DCIOCHIP_AUX_VOD_TUNE {
10078  * DCIOCHIP_GPIO_MASK_EN enum
10081 typedef enum DCIOCHIP_GPIO_MASK_EN {
10087  * DCIOCHIP_HPD_SEL enum
10090 typedef enum DCIOCHIP_HPD_SEL {
10096  * DCIOCHIP_I2C_COMPSEL enum
10099 typedef enum DCIOCHIP_I2C_COMPSEL {
10105  * DCIOCHIP_I2C_FALLSLEWSEL enum
10108 typedef enum DCIOCHIP_I2C_FALLSLEWSEL {
10116  * DCIOCHIP_I2C_RECEIVER_SEL enum
10119 typedef enum DCIOCHIP_I2C_RECEIVER_SEL {
10127  * DCIOCHIP_I2C_VPH_1V2_EN enum
10130 typedef enum DCIOCHIP_I2C_VPH_1V2_EN {
10136  * DCIOCHIP_INVERT enum
10139 typedef enum DCIOCHIP_INVERT {
10145  * DCIOCHIP_MASK enum
10148 typedef enum DCIOCHIP_MASK {
10154  * DCIOCHIP_PAD_MODE enum
10157 typedef enum DCIOCHIP_PAD_MODE {
10163  * DCIOCHIP_PD_EN enum
10166 typedef enum DCIOCHIP_PD_EN {
10172  * DCIOCHIP_REF_27_SRC_SEL enum
10175 typedef enum DCIOCHIP_REF_27_SRC_SEL {
10187  * PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE enum
10190 typedef enum PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
10196  * PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN enum
10199 typedef enum PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN {
10205  * PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT enum
10208 typedef enum PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
10216  * PWRSEQ_BL_PWM_CNTL_BL_PWM_EN enum
10219 typedef enum PWRSEQ_BL_PWM_CNTL_BL_PWM_EN {
10225  * PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN enum
10228 typedef enum PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
10234  * PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN enum
10237 typedef enum PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
10243  * PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN enum
10246 typedef enum PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
10252  * PWRSEQ_BL_PWM_GRP1_REG_LOCK enum
10255 typedef enum PWRSEQ_BL_PWM_GRP1_REG_LOCK {
10261  * PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START enum
10264 typedef enum PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
10270  * PWRSEQ_GPIO_MASK_EN enum
10273 typedef enum PWRSEQ_GPIO_MASK_EN {
10279  * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON enum
10282 typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON {
10288  * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL enum
10291 typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL {
10297  * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON enum
10300 typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON {
10306  * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL enum
10309 typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL {
10315  * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL enum
10318 typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL {
10324  * PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE enum
10327 typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE {
10333  * PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN enum
10336 typedef enum PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN {
10346  * AZ_CORB_SIZE enum
10349 typedef enum AZ_CORB_SIZE {
10357  * AZ_GLOBAL_CAPABILITIES enum
10360 typedef enum AZ_GLOBAL_CAPABILITIES {
10366  * AZ_RIRB_SIZE enum
10369 typedef enum AZ_RIRB_SIZE {
10377  * AZ_RIRB_WRITE_POINTER_RESET enum
10380 typedef enum AZ_RIRB_WRITE_POINTER_RESET {
10386  * AZ_STATE_CHANGE_STATUS enum
10389 typedef enum AZ_STATE_CHANGE_STATUS {
10395  * CORB_READ_POINTER_RESET enum
10398 typedef enum CORB_READ_POINTER_RESET {
10404  * DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE enum
10407 typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
10413  * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL enum
10416 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
10422  * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED enum
10425 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
10431  * GENERIC_AZ_CONTROLLER_REGISTER_STATUS enum
10434 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
10440  * GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED enum
10443 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
10449  * GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE enum
10452 typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
10458  * GLOBAL_CONTROL_CONTROLLER_RESET enum
10461 typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
10467  * GLOBAL_CONTROL_FLUSH_CONTROL enum
10470 typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
10476  * GLOBAL_STATUS_FLUSH_STATUS enum
10479 typedef enum GLOBAL_STATUS_FLUSH_STATUS {
10485  * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY enum
10488 typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
10494  * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID enum
10497 typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
10503  * RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL enum
10506 typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
10512  * RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL enum
10515 typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
10521  * STREAM_0_SYNCHRONIZATION enum
10524 typedef enum STREAM_0_SYNCHRONIZATION {
10530  * STREAM_10_SYNCHRONIZATION enum
10533 typedef enum STREAM_10_SYNCHRONIZATION {
10539  * STREAM_11_SYNCHRONIZATION enum
10542 typedef enum STREAM_11_SYNCHRONIZATION {
10548  * STREAM_12_SYNCHRONIZATION enum
10551 typedef enum STREAM_12_SYNCHRONIZATION {
10557  * STREAM_13_SYNCHRONIZATION enum
10560 typedef enum STREAM_13_SYNCHRONIZATION {
10566  * STREAM_14_SYNCHRONIZATION enum
10569 typedef enum STREAM_14_SYNCHRONIZATION {
10575  * STREAM_15_SYNCHRONIZATION enum
10578 typedef enum STREAM_15_SYNCHRONIZATION {
10584  * STREAM_1_SYNCHRONIZATION enum
10587 typedef enum STREAM_1_SYNCHRONIZATION {
10593  * STREAM_2_SYNCHRONIZATION enum
10596 typedef enum STREAM_2_SYNCHRONIZATION {
10602  * STREAM_3_SYNCHRONIZATION enum
10605 typedef enum STREAM_3_SYNCHRONIZATION {
10611  * STREAM_4_SYNCHRONIZATION enum
10614 typedef enum STREAM_4_SYNCHRONIZATION {
10620  * STREAM_5_SYNCHRONIZATION enum
10623 typedef enum STREAM_5_SYNCHRONIZATION {
10629  * STREAM_6_SYNCHRONIZATION enum
10632 typedef enum STREAM_6_SYNCHRONIZATION {
10638  * STREAM_7_SYNCHRONIZATION enum
10641 typedef enum STREAM_7_SYNCHRONIZATION {
10647  * STREAM_8_SYNCHRONIZATION enum
10650 typedef enum STREAM_8_SYNCHRONIZATION {
10656  * STREAM_9_SYNCHRONIZATION enum
10659 typedef enum STREAM_9_SYNCHRONIZATION {
10669  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
10672 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
10682  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
10685 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
10698  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
10701 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
10713  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
10716 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
10725  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
10728 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
10734  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
10737 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
10743  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE enum
10746 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
10752  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY enum
10755 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
10761  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
10764 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
10770  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L enum
10773 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
10779  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO enum
10782 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
10788  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE enum
10791 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
10797  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO enum
10800 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
10806  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V enum
10809 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
10815  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG enum
10818 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
10824  * AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE enum
10827 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE {
10847  * AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT enum
10850 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
10856  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE enum
10859 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
10865  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
10868 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
10874  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE enum
10877 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
10883  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
10886 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
10892  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE enum
10895 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
10901  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
10904 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
10910  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE enum
10913 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
10919  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
10922 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
10928  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
10931 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
10937  * AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
10940 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
10946  * AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE enum
10949 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
10959  * AZALIA_SOFT_RESET_REFCLK_SOFT_RESET enum
10962 typedef enum AZALIA_SOFT_RESET_REFCLK_SOFT_RESET {
10968  * MEM_PWR_DIS_CTRL enum
10971 typedef enum MEM_PWR_DIS_CTRL {
10977  * MEM_PWR_FORCE_CTRL enum
10980 typedef enum MEM_PWR_FORCE_CTRL {
10988  * MEM_PWR_FORCE_CTRL2 enum
10991 typedef enum MEM_PWR_FORCE_CTRL2 {
10997  * MEM_PWR_SEL_CTRL enum
11000 typedef enum MEM_PWR_SEL_CTRL {
11007  * MEM_PWR_SEL_CTRL2 enum
11010 typedef enum MEM_PWR_SEL_CTRL2 {
11020  * CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY enum
11023 typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
11035  * CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY enum
11038 typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
11054  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
11057 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
11067  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
11070 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
11083  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
11086 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
11098  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
11101 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
11110  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
11113 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
11119  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
11122 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
11128  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
11131 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
11137  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE enum
11140 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
11146  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
11149 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
11155  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE enum
11158 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
11164  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
11167 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
11173  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE enum
11176 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
11182  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
11185 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
11191  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE enum
11194 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
11200  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
11203 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
11209  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
11212 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
11218  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE enum
11221 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
11231  * AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET enum
11234 typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
11244  * AZ_LATENCY_COUNTER_CONTROL enum
11247 typedef enum AZ_LATENCY_COUNTER_CONTROL {
11257  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum
11260 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
11266  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum
11269 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
11275  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum
11278 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
11284  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum
11287 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
11293  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum
11296 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
11302  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum
11305 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
11311  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum
11314 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
11320  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum
11323 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
11329  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum
11332 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
11338  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum
11341 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
11351  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum
11354 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
11374  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum
11377 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
11389  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum
11392 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
11401  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum
11404 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
11414  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
11417 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVER…
11423  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
11426 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITI…
11432  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
11435 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
11441  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
11444 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
11450  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
11453 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
11459  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
11462 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
11468  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
11471 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
11477  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
11480 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT…
11486  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
11489 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
11495  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
11498 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
11504  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
11507 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
11513  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
11516 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
11530 … AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
11533 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAP…
11539  * AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
11542 typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
11548  * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
11551 typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
11557  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
11560 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
11566  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
11569 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
11575  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
11578 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
11584  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
11587 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
11593  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
11596 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
11602  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
11605 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
11611  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
11614 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
11620  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
11623 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
11629  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
11632 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
11638  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
11641 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
11655  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
11658 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILIT…
11664  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
11667 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
11673  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
11676 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
11682  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
11685 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
11691  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
11694 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
11700  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
11703 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
11709  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
11712 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
11718  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
11721 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
11727  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
11730 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
11740 …ALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
11743 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETE…
11749 …AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
11752 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPA…
11758  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
11761 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
11767  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
11770 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
11776  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
11779 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
11785  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
11788 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PR…
11794  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
11797 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
11803  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
11806 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_P…
11812  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
11815 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
11821  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
11824 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
11830  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
11833 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
11839  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
11842 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
11856 …A_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
11859 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPON…
11865  * AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
11868 typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
11874  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
11877 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVER…
11883  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
11886 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
11892  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
11895 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
11901  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
11904 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
11910  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
11913 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
11919  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
11922 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT…
11928  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
11931 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
11937  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
11940 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
11946  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
11949 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
11955  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
11958 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
11972 … AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
11975 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAP…
11981  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
11984 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
11990  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP enum
11993 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
11999  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
12002 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
12008  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI enum
12011 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
12017  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
12020 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
12026  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
12029 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
12035  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
12038 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
12044  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
12047 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
12053  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
12056 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
12062  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
12065 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
12075  * DSCC_BITS_PER_COMPONENT_ENUM enum
12078 typedef enum DSCC_BITS_PER_COMPONENT_ENUM {
12085  * DSCC_DSC_VERSION_MAJOR_ENUM enum
12088 typedef enum DSCC_DSC_VERSION_MAJOR_ENUM {
12093  * DSCC_DSC_VERSION_MINOR_ENUM enum
12096 typedef enum DSCC_DSC_VERSION_MINOR_ENUM {
12102  * DSCC_ENABLE_ENUM enum
12105 typedef enum DSCC_ENABLE_ENUM {
12111  * DSCC_ICH_RESET_ENUM enum
12114 typedef enum DSCC_ICH_RESET_ENUM {
12122  * DSCC_LINEBUF_DEPTH_ENUM enum
12125 typedef enum DSCC_LINEBUF_DEPTH_ENUM {
12135  * DSCC_MEM_PWR_DIS_ENUM enum
12138 typedef enum DSCC_MEM_PWR_DIS_ENUM {
12144  * DSCC_MEM_PWR_FORCE_ENUM enum
12147 typedef enum DSCC_MEM_PWR_FORCE_ENUM {
12155  * POWER_STATE_ENUM enum
12158 typedef enum POWER_STATE_ENUM {
12170  * DSCCIF_BITS_PER_COMPONENT_ENUM enum
12173 typedef enum DSCCIF_BITS_PER_COMPONENT_ENUM {
12180  * DSCCIF_ENABLE_ENUM enum
12183 typedef enum DSCCIF_ENABLE_ENUM {
12189  * DSCCIF_INPUT_PIXEL_FORMAT_ENUM enum
12192 typedef enum DSCCIF_INPUT_PIXEL_FORMAT_ENUM {
12205  * CLOCK_GATING_DISABLE_ENUM enum
12208 typedef enum CLOCK_GATING_DISABLE_ENUM {
12214  * ENABLE_ENUM enum
12217 typedef enum ENABLE_ENUM {
12223  * TEST_CLOCK_MUX_SELECT_ENUM enum
12226 typedef enum TEST_CLOCK_MUX_SELECT_ENUM {
12240  * DWB_CRC_CONT_EN_ENUM enum
12243 typedef enum DWB_CRC_CONT_EN_ENUM {
12249  * DWB_CRC_SRC_SEL_ENUM enum
12252 typedef enum DWB_CRC_SRC_SEL_ENUM {
12259  * DWB_DATA_OVERFLOW_INT_TYPE_ENUM enum
12262 typedef enum DWB_DATA_OVERFLOW_INT_TYPE_ENUM {
12268  * DWB_DATA_OVERFLOW_TYPE_ENUM enum
12271 typedef enum DWB_DATA_OVERFLOW_TYPE_ENUM {
12279  * DWB_DEBUG_SEL_ENUM enum
12282 typedef enum DWB_DEBUG_SEL_ENUM {
12290  * DWB_MEM_PWR_FORCE_ENUM enum
12293 typedef enum DWB_MEM_PWR_FORCE_ENUM {
12301  * DWB_MEM_PWR_STATE_ENUM enum
12304 typedef enum DWB_MEM_PWR_STATE_ENUM {
12312  * DWB_TEST_CLK_SEL_ENUM enum
12315 typedef enum DWB_TEST_CLK_SEL_ENUM {
12322  * FC_EYE_SELECTION_ENUM enum
12325 typedef enum FC_EYE_SELECTION_ENUM {
12332  * FC_FRAME_CAPTURE_RATE_ENUM enum
12335 typedef enum FC_FRAME_CAPTURE_RATE_ENUM {
12343  * FC_STEREO_EYE_POLARITY_ENUM enum
12346 typedef enum FC_STEREO_EYE_POLARITY_ENUM {
12356  * DWB_GAMUT_REMAP_COEF_FORMAT_ENUM enum
12359 typedef enum DWB_GAMUT_REMAP_COEF_FORMAT_ENUM {
12365  * DWB_GAMUT_REMAP_MODE_ENUM enum
12368 typedef enum DWB_GAMUT_REMAP_MODE_ENUM {
12376  * DWB_LUT_NUM_SEG enum
12379 typedef enum DWB_LUT_NUM_SEG {
12391  * DWB_OGAM_LUT_CONFIG_MODE_ENUM enum
12394 typedef enum DWB_OGAM_LUT_CONFIG_MODE_ENUM {
12400  * DWB_OGAM_LUT_HOST_SEL_ENUM enum
12403 typedef enum DWB_OGAM_LUT_HOST_SEL_ENUM {
12409  * DWB_OGAM_LUT_READ_COLOR_SEL_ENUM enum
12412 typedef enum DWB_OGAM_LUT_READ_COLOR_SEL_ENUM {
12420  * DWB_OGAM_LUT_READ_DBG_ENUM enum
12423 typedef enum DWB_OGAM_LUT_READ_DBG_ENUM {
12429  * DWB_OGAM_MODE_ENUM enum
12432 typedef enum DWB_OGAM_MODE_ENUM {
12439  * DWB_OGAM_PWL_DISABLE_ENUM enum
12442 typedef enum DWB_OGAM_PWL_DISABLE_ENUM {
12448  * DWB_OGAM_SELECT_ENUM enum
12451 typedef enum DWB_OGAM_SELECT_ENUM {
12461  * RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN enum
12464 typedef enum RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN {
12470  * RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN enum
12473 typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN {
12479  * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON enum
12482 typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON {
12488  * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN enum
12491 typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN {
12497  * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS enum
12500 typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS {
12506  * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON enum
12509 typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON {
12515  * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON enum
12518 typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON {
12524  * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN enum
12527 typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN {
12533  * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS enum
12536 typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS {
12542  * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS enum
12545 typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS {
12551  * RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN enum
12554 typedef enum RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN {
12560  * RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN enum
12563 typedef enum RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN {
12569  * RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET enum
12572 typedef enum RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET {
12578  * RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET enum
12581 typedef enum RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET {
12587  * RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK enum
12590 typedef enum RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK {
12596  * RDPCSPIPE_DBG_OCLA_SEL enum
12599 typedef enum RDPCSPIPE_DBG_OCLA_SEL {
12611  * RDPCSPIPE_ENC_TYPE enum
12614 typedef enum RDPCSPIPE_ENC_TYPE {
12621  * RDPCSPIPE_FIFO_EMPTY enum
12624 typedef enum RDPCSPIPE_FIFO_EMPTY {
12630  * RDPCSPIPE_FIFO_FULL enum
12633 typedef enum RDPCSPIPE_FIFO_FULL {
12639  * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK enum
12642 typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK {
12648  * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE enum
12651 typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE {
12657  * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK enum
12660 typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK {
12666  * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE enum
12669 typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE {
12675  * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK enum
12678 typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK {
12684  * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK enum
12687 typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK {
12693  * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK enum
12696 typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK {
12702  * RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK enum
12705 typedef enum RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK {
12711  * RDPCSPIPE_PACK_MODE enum
12714 typedef enum RDPCSPIPE_PACK_MODE {
12720  * RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL enum
12723 typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL {
12729  * RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL enum
12732 typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL {
12738  * RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE enum
12741 typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE {
12753  * RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE enum
12756 typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE {
12762  * RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE enum
12765 typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE {
12771  * RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV enum
12774 typedef enum RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV {
12783  * RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV enum
12786 typedef enum RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV {
12794  * RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV enum
12797 typedef enum RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV {
12809  * RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL enum
12812 typedef enum RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL {
12824  * RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT enum
12827 typedef enum RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT {
12833  * RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE enum
12836 typedef enum RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE {
12843  * RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH enum
12846 typedef enum RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH {
12854  * RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE enum
12857 typedef enum RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE {
12865  * RDPCSPIPE_PHY_IF_WIDTH enum
12868 typedef enum RDPCSPIPE_PHY_IF_WIDTH {
12876  * RDPCSPIPE_PHY_RATE enum
12879 typedef enum RDPCSPIPE_PHY_RATE {
12895  * RDPCSPIPE_PHY_REF_ALT_CLK_EN enum
12898 typedef enum RDPCSPIPE_PHY_REF_ALT_CLK_EN {
12904  * RDPCSPIPE_TEST_CLK_SEL enum
12907 typedef enum RDPCSPIPE_TEST_CLK_SEL {
12929  * RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB enum
12932 typedef enum RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB {
12938  * RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE enum
12941 typedef enum RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE {
12949  * RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE enum
12952 typedef enum RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE {
12960  * RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK enum
12963 typedef enum RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK {
12973  * GDS_PERFCOUNT_SELECT enum
12976 typedef enum GDS_PERFCOUNT_SELECT {
13092  * BlendOp enum
13095 typedef enum BlendOp {
13118  * BlendOpt enum
13121 typedef enum BlendOpt {
13133  * CBMode enum
13136 typedef enum CBMode {
13145  * CBPerfClearFilterSel enum
13148 typedef enum CBPerfClearFilterSel {
13154  * CBPerfOpFilterSel enum
13157 typedef enum CBPerfOpFilterSel {
13167  * CBPerfSel enum
13170 typedef enum CBPerfSel {
13640  * CBRamList enum
13643 typedef enum CBRamList {
13664  * CmaskCode enum
13667 typedef enum CmaskCode {
13687  * CombFunc enum
13690 typedef enum CombFunc {
13699  * MemArbMode enum
13702 typedef enum MemArbMode {
13710  * SourceFormat enum
13713 typedef enum SourceFormat {
13725  * BinEventCntl enum
13728 typedef enum BinEventCntl {
13736  * BinMapMode enum
13739 typedef enum BinMapMode {
13746  * BinSizeExtend enum
13749 typedef enum BinSizeExtend {
13758  * BinningMode enum
13761 typedef enum BinningMode {
13769  * CovToShaderSel enum
13772 typedef enum CovToShaderSel {
13780  * PkrMap enum
13783 typedef enum PkrMap {
13791  * PkrXsel enum
13794 typedef enum PkrXsel {
13802  * PkrXsel2 enum
13805 typedef enum PkrXsel2 {
13813  * PkrYsel enum
13816 typedef enum PkrYsel {
13824  * RbMap enum
13827 typedef enum RbMap {
13835  * RbXsel enum
13838 typedef enum RbXsel {
13844  * RbXsel2 enum
13847 typedef enum RbXsel2 {
13855  * RbYsel enum
13858 typedef enum RbYsel {
13864  * SC_PERFCNT_SEL enum
13867 typedef enum SC_PERFCNT_SEL {
14449  * ScMap enum
14452 typedef enum ScMap {
14460  * ScUncertaintyRegionMode enum
14463 typedef enum ScUncertaintyRegionMode {
14470  * ScUncertaintyRegionMult enum
14473 typedef enum ScUncertaintyRegionMult {
14481  * ScXsel enum
14484 typedef enum ScXsel {
14492  * ScYsel enum
14495 typedef enum ScYsel {
14503  * SeMap enum
14506 typedef enum SeMap {
14514  * SePairMap enum
14517 typedef enum SePairMap {
14525  * SePairXsel enum
14528 typedef enum SePairXsel {
14536  * SePairYsel enum
14539 typedef enum SePairYsel {
14547  * SeXsel enum
14550 typedef enum SeXsel {
14558  * SeYsel enum
14561 typedef enum SeYsel {
14569  * VRSCombinerModeSC enum
14572 typedef enum VRSCombinerModeSC {
14581  * VRSrate enum
14584 typedef enum VRSrate {
14608  * TC_EA_CID enum
14611 typedef enum TC_EA_CID {
14631  * TC_NACKS enum
14634 typedef enum TC_NACKS {
14642  * TC_OP enum
14645 typedef enum TC_OP {
14777  * TC_OP_MASKS enum
14780 typedef enum TC_OP_MASKS {
14791  * GL2_EA_CID enum
14794 typedef enum GL2_EA_CID {
14813  * GL2_NACKS enum
14816 typedef enum GL2_NACKS {
14824  * GL2_OP enum
14827 typedef enum GL2_OP {
14919  * GL2_OP_MASKS enum
14922 typedef enum GL2_OP_MASKS {
14933  * RLC_DOORBELL_MODE enum
14936 typedef enum RLC_DOORBELL_MODE {
14944  * RLC_PERFCOUNTER_SEL enum
14947 typedef enum RLC_PERFCOUNTER_SEL {
14958  * RLC_PERFMON_STATE enum
14961 typedef enum RLC_PERFMON_STATE {
14973  * RSPM_CMD enum
14976 typedef enum RSPM_CMD {
14995  * CLKGATE_BASE_MODE enum
14998 typedef enum CLKGATE_BASE_MODE {
15004  * CLKGATE_SM_MODE enum
15007 typedef enum CLKGATE_SM_MODE {
15016  * SPI_FOG_MODE enum
15019 typedef enum SPI_FOG_MODE {
15027  * SPI_LB_WAVES_SELECT enum
15030 typedef enum SPI_LB_WAVES_SELECT {
15038  * SPI_PERFCNT_SEL enum
15041 typedef enum SPI_PERFCNT_SEL {
15275  * SPI_PNT_SPRITE_OVERRIDE enum
15278 typedef enum SPI_PNT_SPRITE_OVERRIDE {
15287  * SPI_PS_LDS_GROUP_SIZE enum
15290 typedef enum SPI_PS_LDS_GROUP_SIZE {
15297  * SPI_SAMPLE_CNTL enum
15300 typedef enum SPI_SAMPLE_CNTL {
15308  * SPI_SHADER_EX_FORMAT enum
15311 typedef enum SPI_SHADER_EX_FORMAT {
15325  * SPI_SHADER_FORMAT enum
15328 typedef enum SPI_SHADER_FORMAT {
15341  * SH_MEM_ADDRESS_MODE enum
15344 typedef enum SH_MEM_ADDRESS_MODE {
15350  * SH_MEM_ALIGNMENT_MODE enum
15353 typedef enum SH_MEM_ALIGNMENT_MODE {
15361  * SQG_PERF_SEL enum
15364 typedef enum SQG_PERF_SEL {
15403  * SQ_CAC_POWER_SEL enum
15406 typedef enum SQ_CAC_POWER_SEL {
15419  * SQ_EDC_INFO_SOURCE enum
15422 typedef enum SQ_EDC_INFO_SOURCE {
15433  * SQ_IBUF_ST enum
15436 typedef enum SQ_IBUF_ST {
15448  * SQ_IMG_FILTER_TYPE enum
15451 typedef enum SQ_IMG_FILTER_TYPE {
15458  * SQ_IND_CMD_CMD enum
15461 typedef enum SQ_IND_CMD_CMD {
15474  * SQ_IND_CMD_MODE enum
15477 typedef enum SQ_IND_CMD_MODE {
15486  * SQ_INST_STR_ST enum
15489 typedef enum SQ_INST_STR_ST {
15499  * SQ_INST_TYPE enum
15502 typedef enum SQ_INST_TYPE {
15519  * SQ_LLC_CTL enum
15522 typedef enum SQ_LLC_CTL {
15530  * SQ_NO_INST_ISSUE enum
15533 typedef enum SQ_NO_INST_ISSUE {
15544  * SQ_OOB_SELECT enum
15547 typedef enum SQ_OOB_SELECT {
15555  * SQ_PERF_SEL enum
15558 typedef enum SQ_PERF_SEL {
15868  * SQ_ROUND_MODE enum
15871 typedef enum SQ_ROUND_MODE {
15879  * SQ_RSRC_BUF_TYPE enum
15882 typedef enum SQ_RSRC_BUF_TYPE {
15890  * SQ_RSRC_FLAT_TYPE enum
15893 typedef enum SQ_RSRC_FLAT_TYPE {
15901  * SQ_RSRC_IMG_TYPE enum
15904 typedef enum SQ_RSRC_IMG_TYPE {
15924  * SQ_SEL_XYZW01 enum
15927 typedef enum SQ_SEL_XYZW01 {
15939  * SQ_TEX_ANISO_RATIO enum
15942 typedef enum SQ_TEX_ANISO_RATIO {
15951  * SQ_TEX_BORDER_COLOR enum
15954 typedef enum SQ_TEX_BORDER_COLOR {
15962  * SQ_TEX_CLAMP enum
15965 typedef enum SQ_TEX_CLAMP {
15977  * SQ_TEX_DEPTH_COMPARE enum
15980 typedef enum SQ_TEX_DEPTH_COMPARE {
15992  * SQ_TEX_MIP_FILTER enum
15995 typedef enum SQ_TEX_MIP_FILTER {
16003  * SQ_TEX_XY_FILTER enum
16006 typedef enum SQ_TEX_XY_FILTER {
16014  * SQ_TEX_Z_FILTER enum
16017 typedef enum SQ_TEX_Z_FILTER {
16024  * SQ_TT_MODE enum
16027 typedef enum SQ_TT_MODE {
16035  * SQ_TT_RT_FREQ enum
16038 typedef enum SQ_TT_RT_FREQ {
16045  * SQ_TT_TOKEN_MASK_INST_EXCLUDE enum
16048 typedef enum SQ_TT_TOKEN_MASK_INST_EXCLUDE {
16054  * SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT enum
16057 typedef enum SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT {
16063  * SQ_TT_TOKEN_MASK_REG_EXCLUDE enum
16066 typedef enum SQ_TT_TOKEN_MASK_REG_EXCLUDE {
16073  * SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT enum
16076 typedef enum SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT {
16083  * SQ_TT_TOKEN_MASK_REG_INCLUDE enum
16086 typedef enum SQ_TT_TOKEN_MASK_REG_INCLUDE {
16098  * SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT enum
16101 typedef enum SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT {
16113  * SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT enum
16116 typedef enum SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT {
16132  * SQ_TT_UTIL_TIMER enum
16135 typedef enum SQ_TT_UTIL_TIMER {
16141  * SQ_TT_WAVESTART_MODE enum
16144 typedef enum SQ_TT_WAVESTART_MODE {
16151  * SQ_TT_WTYPE_INCLUDE enum
16154 typedef enum SQ_TT_WTYPE_INCLUDE {
16165  * SQ_TT_WTYPE_INCLUDE_SHIFT enum
16168 typedef enum SQ_TT_WTYPE_INCLUDE_SHIFT {
16179  * SQ_WATCH_MODES enum
16182 typedef enum SQ_WATCH_MODES {
16190  * SQ_WAVE_FWD_PROG_INTERVAL enum
16193 typedef enum SQ_WAVE_FWD_PROG_INTERVAL {
16201  * SQ_WAVE_IB_ECC_ST enum
16204 typedef enum SQ_WAVE_IB_ECC_ST {
16212  * SQ_WAVE_SCHED_MODES enum
16215 typedef enum SQ_WAVE_SCHED_MODES {
16222  * SQ_WAVE_TYPE enum
16225 typedef enum SQ_WAVE_TYPE {
16420  * CSCNTL_TYPE enum
16423 typedef enum CSCNTL_TYPE {
16431  * CSDATA_TYPE enum
16434 typedef enum CSDATA_TYPE {
16482  * GE1_PERFCOUNT_SELECT enum
16485 typedef enum GE1_PERFCOUNT_SELECT {
16529  * GE2_DIST_PERFCOUNT_SELECT enum
16532 typedef enum GE2_DIST_PERFCOUNT_SELECT {
16628  * GE2_SE_PERFCOUNT_SELECT enum
16631 typedef enum GE2_SE_PERFCOUNT_SELECT {
16706  * VGT_DETECT_ONE enum
16709 typedef enum VGT_DETECT_ONE {
16715  * VGT_DETECT_ZERO enum
16718 typedef enum VGT_DETECT_ZERO {
16724  * VGT_DIST_MODE enum
16727 typedef enum VGT_DIST_MODE {
16735  * VGT_DI_INDEX_SIZE enum
16738 typedef enum VGT_DI_INDEX_SIZE {
16745  * VGT_DI_MAJOR_MODE_SELECT enum
16748 typedef enum VGT_DI_MAJOR_MODE_SELECT {
16754  * VGT_DI_PRIM_TYPE enum
16757 typedef enum VGT_DI_PRIM_TYPE {
16783  * VGT_DI_SOURCE_SELECT enum
16786 typedef enum VGT_DI_SOURCE_SELECT {
16794  * VGT_DMA_BUF_TYPE enum
16797 typedef enum VGT_DMA_BUF_TYPE {
16805  * VGT_DMA_SWAP_MODE enum
16808 typedef enum VGT_DMA_SWAP_MODE {
16816  * VGT_EVENT_TYPE enum
16819 typedef enum VGT_EVENT_TYPE {
16887  * VGT_GROUP_CONV_SEL enum
16890 typedef enum VGT_GROUP_CONV_SEL {
16903  * VGT_GS_MODE_TYPE enum
16906 typedef enum VGT_GS_MODE_TYPE {
16916  * VGT_GS_OUTPRIM_TYPE enum
16919 typedef enum VGT_GS_OUTPRIM_TYPE {
16928  * VGT_INDEX_TYPE_MODE enum
16931 typedef enum VGT_INDEX_TYPE_MODE {
16938  * VGT_OUTPATH_SELECT enum
16941 typedef enum VGT_OUTPATH_SELECT {
16952  * VGT_OUT_PRIM_TYPE enum
16955 typedef enum VGT_OUT_PRIM_TYPE {
16974  * VGT_RDREQ_POLICY enum
16977 typedef enum VGT_RDREQ_POLICY {
16984  * VGT_STAGES_ES_EN enum
16987 typedef enum VGT_STAGES_ES_EN {
16995  * VGT_STAGES_GS_EN enum
16998 typedef enum VGT_STAGES_GS_EN {
17004  * VGT_STAGES_HS_EN enum
17007 typedef enum VGT_STAGES_HS_EN {
17013  * VGT_STAGES_LS_EN enum
17016 typedef enum VGT_STAGES_LS_EN {
17024  * VGT_STAGES_VS_EN enum
17027 typedef enum VGT_STAGES_VS_EN {
17035  * VGT_TESS_PARTITION enum
17038 typedef enum VGT_TESS_PARTITION {
17046  * VGT_TESS_TOPOLOGY enum
17049 typedef enum VGT_TESS_TOPOLOGY {
17057  * VGT_TESS_TYPE enum
17060 typedef enum VGT_TESS_TYPE {
17067  * WD_IA_DRAW_REG_XFER enum
17070 typedef enum WD_IA_DRAW_REG_XFER {
17083  * WD_IA_DRAW_SOURCE enum
17086 typedef enum WD_IA_DRAW_SOURCE {
17094  * WD_IA_DRAW_TYPE enum
17097 typedef enum WD_IA_DRAW_TYPE {
17119  * GB_EDC_DED_MODE enum
17122 typedef enum GB_EDC_DED_MODE {
17145  * CHA_PERF_SEL enum
17148 typedef enum CHA_PERF_SEL {
17192  * CHCG_PERF_SEL enum
17195 typedef enum CHCG_PERF_SEL {
17243  * CHC_PERF_SEL enum
17246 typedef enum CHC_PERF_SEL {
17294  * GL1A_PERF_SEL enum
17297 typedef enum GL1A_PERF_SEL {
17325  * GL1C_PERF_SEL enum
17328 typedef enum GL1C_PERF_SEL {
17420  * GL1H_REQ_PERF_SEL enum
17423 typedef enum GL1H_REQ_PERF_SEL {
17443  * TA_PERFCOUNT_SEL enum
17446 typedef enum TA_PERFCOUNT_SEL {
17659  * TEX_BC_SWIZZLE enum
17662 typedef enum TEX_BC_SWIZZLE {
17672  * TEX_BORDER_COLOR_TYPE enum
17675 typedef enum TEX_BORDER_COLOR_TYPE {
17683  * TEX_CHROMA_KEY enum
17686 typedef enum TEX_CHROMA_KEY {
17694  * TEX_CLAMP enum
17697 typedef enum TEX_CLAMP {
17709  * TEX_COORD_TYPE enum
17712 typedef enum TEX_COORD_TYPE {
17718  * TEX_DEPTH_COMPARE_FUNCTION enum
17721 typedef enum TEX_DEPTH_COMPARE_FUNCTION {
17733  * TEX_FORMAT_COMP enum
17736 typedef enum TEX_FORMAT_COMP {
17744  * TEX_MAX_ANISO_RATIO enum
17747 typedef enum TEX_MAX_ANISO_RATIO {
17759  * TEX_MIP_FILTER enum
17762 typedef enum TEX_MIP_FILTER {
17770  * TEX_REQUEST_SIZE enum
17773 typedef enum TEX_REQUEST_SIZE {
17781  * TEX_SAMPLER_TYPE enum
17784 typedef enum TEX_SAMPLER_TYPE {
17790  * TEX_XY_FILTER enum
17793 typedef enum TEX_XY_FILTER {
17801  * TEX_Z_FILTER enum
17804 typedef enum TEX_Z_FILTER {
17812  * TVX_TYPE enum
17815 typedef enum TVX_TYPE {
17827  * TA_TC_ADDR_MODES enum
17830 typedef enum TA_TC_ADDR_MODES {
17841  * TA_TC_REQ_MODES enum
17844 typedef enum TA_TC_REQ_MODES {
17856  * TCP_CACHE_POLICIES enum
17859 typedef enum TCP_CACHE_POLICIES {
17867  * TCP_CACHE_STORE_POLICIES enum
17870 typedef enum TCP_CACHE_STORE_POLICIES {
17876  * TCP_DSM_DATA_SEL enum
17879 typedef enum TCP_DSM_DATA_SEL {
17887  * TCP_DSM_INJECT_SEL enum
17890 typedef enum TCP_DSM_INJECT_SEL {
17898  * TCP_DSM_SINGLE_WRITE enum
17901 typedef enum TCP_DSM_SINGLE_WRITE {
17907  * TCP_OPCODE_TYPE enum
17910 typedef enum TCP_OPCODE_TYPE {
17922  * TCP_PERFCOUNT_SELECT enum
17925 typedef enum TCP_PERFCOUNT_SELECT {
17992  * TCP_WATCH_MODES enum
17995 typedef enum TCP_WATCH_MODES {
18007  * TD_PERFCOUNT_SEL enum
18010 typedef enum TD_PERFCOUNT_SEL {
18206  * GL2A_PERF_SEL enum
18209 typedef enum GL2A_PERF_SEL {
18320  * GL2C_PERF_SEL enum
18323 typedef enum GL2C_PERF_SEL {
18589  * GRBM_PERF_SEL enum
18592 typedef enum GRBM_PERF_SEL {
18635  * GRBM_SE0_PERF_SEL enum
18638 typedef enum GRBM_SE0_PERF_SEL {
18660  * GRBM_SE1_PERF_SEL enum
18663 typedef enum GRBM_SE1_PERF_SEL {
18685  * GRBM_SE2_PERF_SEL enum
18688 typedef enum GRBM_SE2_PERF_SEL {
18710  * GRBM_SE3_PERF_SEL enum
18713 typedef enum GRBM_SE3_PERF_SEL {
18735  * GRBM_SE4_PERF_SEL enum
18738 typedef enum GRBM_SE4_PERF_SEL {
18760  * GRBM_SE5_PERF_SEL enum
18763 typedef enum GRBM_SE5_PERF_SEL {
18785  * GRBM_SE6_PERF_SEL enum
18788 typedef enum GRBM_SE6_PERF_SEL {
18810  * GRBM_SE7_PERF_SEL enum
18813 typedef enum GRBM_SE7_PERF_SEL {
18835  * PIPE_COMPAT_LEVEL enum
18838 typedef enum PIPE_COMPAT_LEVEL {
18850  * CPC_LATENCY_STATS_SEL enum
18853 typedef enum CPC_LATENCY_STATS_SEL {
18866  * CPC_PERFCOUNT_SEL enum
18869 typedef enum CPC_PERFCOUNT_SEL {
18918  * CPF_LATENCY_STATS_SEL enum
18921 typedef enum CPF_LATENCY_STATS_SEL {
18937  * CPF_PERFCOUNTWINDOW_SEL enum
18940 typedef enum CPF_PERFCOUNTWINDOW_SEL {
18949  * CPF_PERFCOUNT_SEL enum
18952 typedef enum CPF_PERFCOUNT_SEL {
18997  * CPF_SCRATCH_REG_ATOMIC_OP enum
19000 typedef enum CPF_SCRATCH_REG_ATOMIC_OP {
19012  * CPG_LATENCY_STATS_SEL enum
19015 typedef enum CPG_LATENCY_STATS_SEL {
19037  * CPG_PERFCOUNTWINDOW_SEL enum
19040 typedef enum CPG_PERFCOUNTWINDOW_SEL {
19075  * CPG_PERFCOUNT_SEL enum
19078 typedef enum CPG_PERFCOUNT_SEL {
19163  * CP_ALPHA_TAG_RAM_SEL enum
19166 typedef enum CP_ALPHA_TAG_RAM_SEL {
19174  * CP_DDID_CNTL_MODE enum
19177 typedef enum CP_DDID_CNTL_MODE {
19183  * CP_DDID_CNTL_SIZE enum
19186 typedef enum CP_DDID_CNTL_SIZE {
19192  * CP_DDID_CNTL_VMID_SEL enum
19195 typedef enum CP_DDID_CNTL_VMID_SEL {
19201  * CP_ME_ID enum
19204 typedef enum CP_ME_ID {
19212  * CP_PERFMON_ENABLE_MODE enum
19215 typedef enum CP_PERFMON_ENABLE_MODE {
19223  * CP_PERFMON_STATE enum
19226 typedef enum CP_PERFMON_STATE {
19236  * CP_PIPE_ID enum
19239 typedef enum CP_PIPE_ID {
19247  * CP_RING_ID enum
19250 typedef enum CP_RING_ID {
19258  * SPM_PERFMON_STATE enum
19261 typedef enum SPM_PERFMON_STATE {
19361  * SX_BLEND_OPT enum
19364 typedef enum SX_BLEND_OPT {
19376  * SX_DOWNCONVERT_FORMAT enum
19379 typedef enum SX_DOWNCONVERT_FORMAT {
19397  * SX_OPT_COMB_FCN enum
19400 typedef enum SX_OPT_COMB_FCN {
19412  * SX_PERFCOUNTER_VALS enum
19415 typedef enum SX_PERFCOUNTER_VALS {
19505  * CompareFrag enum
19508 typedef enum CompareFrag {
19520  * ConservativeZExport enum
19523 typedef enum ConservativeZExport {
19531  * DFSMFlushEvents enum
19534 typedef enum DFSMFlushEvents {
19549  * DbMemArbWatermarks enum
19552 typedef enum DbMemArbWatermarks {
19564  * DbPRTFaultBehavior enum
19567 typedef enum DbPRTFaultBehavior {
19575  * DbPSLControl enum
19578 typedef enum DbPSLControl {
19586  * ForceControl enum
19589 typedef enum ForceControl {
19597  * OreoMode enum
19600 typedef enum OreoMode {
19608  * PerfCounter_Vals enum
19611 typedef enum PerfCounter_Vals {
19964  * PixelPipeCounterId enum
19967 typedef enum PixelPipeCounterId {
19979  * PixelPipeStride enum
19982 typedef enum PixelPipeStride {
19990  * RingCounterControl enum
19993 typedef enum RingCounterControl {
20000  * StencilOp enum
20003 typedef enum StencilOp {
20023  * ZLimitSumm enum
20026 typedef enum ZLimitSumm {
20034  * ZModeForce enum
20037 typedef enum ZModeForce {
20045  * ZOrder enum
20048 typedef enum ZOrder {
20056  * ZSamplePosition enum
20059 typedef enum ZSamplePosition {
20065  * ZpassControl enum
20068 typedef enum ZpassControl {
20079  * SU_PERFCNT_SEL enum
20082 typedef enum SU_PERFCNT_SEL {
20366  * PH_PERFCNT_SEL enum
20369 typedef enum PH_PERFCNT_SEL {
21397  * PhSPIstatusMode enum
21400 typedef enum PhSPIstatusMode {
21411  * RMIPerfSel enum
21414 typedef enum RMIPerfSel {
21424  * GCRPerfSel enum
21427 typedef enum GCRPerfSel {
21577  * UTCL1PerfSel enum
21580 typedef enum UTCL1PerfSel {
21611  * IH_CLIENT_TYPE enum
21614 typedef enum IH_CLIENT_TYPE {
21622  * IH_INTERFACE_TYPE enum
21625 typedef enum IH_INTERFACE_TYPE {
21631  * IH_PERF_SEL enum
21634 typedef enum IH_PERF_SEL {
22041  * IH_RING_ID enum
22044 typedef enum IH_RING_ID {
22052  * IH_VF_RB_SELECT enum
22055 typedef enum IH_VF_RB_SELECT {
22067  * SEM_PERF_SEL enum
22070 typedef enum SEM_PERF_SEL {
22259  * LSDMA_PERF_SEL enum
22262 typedef enum LSDMA_PERF_SEL {
22397  * EFC_SURFACE_PIXEL_FORMAT enum
22400 typedef enum EFC_SURFACE_PIXEL_FORMAT {