Lines Matching +full:0 +full:x00000012
37 static const struct IP_BASE ACP_BASE ={ { { { 0x02403800, 0x00480000, 0, 0, 0 } },
38 { { 0, 0, 0, 0, 0 } },
39 { { 0, 0, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0 } },
42 { { 0, 0, 0, 0, 0 } },
43 { { 0, 0, 0, 0, 0 } } } };
44 static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x02408C00, 0, 0, 0 } },
45 { { 0, 0, 0, 0, 0 } },
46 { { 0, 0, 0, 0, 0 } },
47 { { 0, 0, 0, 0, 0 } },
48 { { 0, 0, 0, 0, 0 } },
49 { { 0, 0, 0, 0, 0 } },
50 { { 0, 0, 0, 0, 0 } } } };
51 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017E00, 0 } },
52 { { 0, 0, 0, 0, 0 } },
53 { { 0, 0, 0, 0, 0 } },
54 { { 0, 0, 0, 0, 0 } },
55 { { 0, 0, 0, 0, 0 } },
56 { { 0, 0, 0, 0, 0 } },
57 { { 0, 0, 0, 0, 0 } } } };
58 static const struct IP_BASE DBGU_IO0_BASE ={ { { { 0x000001E0, 0x0240B400, 0, 0, 0 } },
59 { { 0, 0, 0, 0, 0 } },
60 { { 0, 0, 0, 0, 0 } },
61 { { 0, 0, 0, 0, 0 } },
62 { { 0, 0, 0, 0, 0 } },
63 { { 0, 0, 0, 0, 0 } },
64 { { 0, 0, 0, 0, 0 } } } };
65 static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } },
66 { { 0, 0, 0, 0, 0 } },
67 { { 0, 0, 0, 0, 0 } },
68 { { 0, 0, 0, 0, 0 } },
69 { { 0, 0, 0, 0, 0 } },
70 { { 0, 0, 0, 0, 0 } },
71 { { 0, 0, 0, 0, 0 } } } };
72 static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } },
73 { { 0, 0, 0, 0, 0 } },
74 { { 0, 0, 0, 0, 0 } },
75 { { 0, 0, 0, 0, 0 } },
76 { { 0, 0, 0, 0, 0 } },
77 { { 0, 0, 0, 0, 0 } },
78 { { 0, 0, 0, 0, 0 } } } };
79 static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x024…
80 { { 0, 0, 0, 0, 0 } },
81 { { 0, 0, 0, 0, 0 } },
82 { { 0, 0, 0, 0, 0 } },
83 { { 0, 0, 0, 0, 0 } },
84 { { 0, 0, 0, 0, 0 } },
85 { { 0, 0, 0, 0, 0 } } } };
86 static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02…
87 { { 0, 0, 0, 0, 0 } },
88 { { 0, 0, 0, 0, 0 } },
89 { { 0, 0, 0, 0, 0 } },
90 { { 0, 0, 0, 0, 0 } },
91 { { 0, 0, 0, 0, 0 } },
92 { { 0, 0, 0, 0, 0 } } } };
93 static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } },
94 { { 0, 0, 0, 0, 0 } },
95 { { 0, 0, 0, 0, 0 } },
96 { { 0, 0, 0, 0, 0 } },
97 { { 0, 0, 0, 0, 0 } },
98 { { 0, 0, 0, 0, 0 } },
99 { { 0, 0, 0, 0, 0 } } } };
100 static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0x02402C00, 0, 0 } },
101 { { 0, 0, 0, 0, 0 } },
102 { { 0, 0, 0, 0, 0 } },
103 { { 0, 0, 0, 0, 0 } },
104 { { 0, 0, 0, 0, 0 } },
105 { { 0, 0, 0, 0, 0 } },
106 { { 0, 0, 0, 0, 0 } } } };
107 static const struct IP_BASE HDA_BASE ={ { { { 0x02404800, 0x004C0000, 0, 0, 0 } },
108 { { 0, 0, 0, 0, 0 } },
109 { { 0, 0, 0, 0, 0 } },
110 { { 0, 0, 0, 0, 0 } },
111 { { 0, 0, 0, 0, 0 } },
112 { { 0, 0, 0, 0, 0 } },
113 { { 0, 0, 0, 0, 0 } } } };
114 static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } },
115 { { 0, 0, 0, 0, 0 } },
116 { { 0, 0, 0, 0, 0 } },
117 { { 0, 0, 0, 0, 0 } },
118 { { 0, 0, 0, 0, 0 } },
119 { { 0, 0, 0, 0, 0 } },
120 { { 0, 0, 0, 0, 0 } } } };
121 static const struct IP_BASE IOHC0_BASE ={ { { { 0x00010000, 0x02406000, 0x04EC0000, 0, 0 } },
122 { { 0, 0, 0, 0, 0 } },
123 { { 0, 0, 0, 0, 0 } },
124 { { 0, 0, 0, 0, 0 } },
125 { { 0, 0, 0, 0, 0 } },
126 { { 0, 0, 0, 0, 0 } },
127 { { 0, 0, 0, 0, 0 } } } };
128 static const struct IP_BASE ISP_BASE ={ { { { 0x00018000, 0x0240B000, 0, 0, 0 } },
129 { { 0, 0, 0, 0, 0 } },
130 { { 0, 0, 0, 0, 0 } },
131 { { 0, 0, 0, 0, 0 } },
132 { { 0, 0, 0, 0, 0 } },
133 { { 0, 0, 0, 0, 0 } },
134 { { 0, 0, 0, 0, 0 } } } };
135 static const struct IP_BASE L2IMU0_BASE ={ { { { 0x00007DC0, 0x02407000, 0x00900000, 0x04FC0000, 0x…
136 { { 0, 0, 0, 0, 0 } },
137 { { 0, 0, 0, 0, 0 } },
138 { { 0, 0, 0, 0, 0 } },
139 { { 0, 0, 0, 0, 0 } },
140 { { 0, 0, 0, 0, 0 } },
141 { { 0, 0, 0, 0, 0 } } } };
142 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
143 { { 0, 0, 0, 0, 0 } },
144 { { 0, 0, 0, 0, 0 } },
145 { { 0, 0, 0, 0, 0 } },
146 { { 0, 0, 0, 0, 0 } },
147 { { 0, 0, 0, 0, 0 } },
148 { { 0, 0, 0, 0, 0 } } } };
149 static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E…
150 { { 0, 0, 0, 0, 0 } },
151 { { 0, 0, 0, 0, 0 } },
152 { { 0, 0, 0, 0, 0 } },
153 { { 0, 0, 0, 0, 0 } },
154 { { 0, 0, 0, 0, 0 } },
155 { { 0, 0, 0, 0, 0 } } } };
156 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x02400400, 0x00E80000, 0x00EC0000, 0x00F…
157 { { 0, 0, 0, 0, 0 } },
158 { { 0, 0, 0, 0, 0 } },
159 { { 0, 0, 0, 0, 0 } },
160 { { 0, 0, 0, 0, 0 } },
161 { { 0, 0, 0, 0, 0 } },
162 { { 0, 0, 0, 0, 0 } } } };
163 static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0…
164 { { 0, 0, 0, 0, 0 } },
165 { { 0, 0, 0, 0, 0 } },
166 { { 0, 0, 0, 0, 0 } },
167 { { 0, 0, 0, 0, 0 } },
168 { { 0, 0, 0, 0, 0 } },
169 { { 0, 0, 0, 0, 0 } } } };
170 static const struct IP_BASE DCN_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
171 { { 0, 0, 0, 0, 0 } },
172 { { 0, 0, 0, 0, 0 } },
173 { { 0, 0, 0, 0, 0 } },
174 { { 0, 0, 0, 0, 0 } } } };
175 static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } },
176 { { 0, 0, 0, 0, 0 } },
177 { { 0, 0, 0, 0, 0 } },
178 { { 0, 0, 0, 0, 0 } },
179 { { 0, 0, 0, 0, 0 } },
180 { { 0, 0, 0, 0, 0 } },
181 { { 0, 0, 0, 0, 0 } } } };
182 static const struct IP_BASE PCIE0_BASE ={ { { { 0x02411800, 0x04440000, 0, 0, 0 } },
183 { { 0, 0, 0, 0, 0 } },
184 { { 0, 0, 0, 0, 0 } },
185 { { 0, 0, 0, 0, 0 } },
186 { { 0, 0, 0, 0, 0 } },
187 { { 0, 0, 0, 0, 0 } },
188 { { 0, 0, 0, 0, 0 } } } };
189 static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0x0240A800, 0, 0, 0 } },
190 { { 0, 0, 0, 0, 0 } },
191 { { 0, 0, 0, 0, 0 } },
192 { { 0, 0, 0, 0, 0 } },
193 { { 0, 0, 0, 0, 0 } },
194 { { 0, 0, 0, 0, 0 } },
195 { { 0, 0, 0, 0, 0 } } } };
196 static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0 }…
197 { { 0, 0, 0, 0, 0 } },
198 { { 0, 0, 0, 0, 0 } },
199 { { 0, 0, 0, 0, 0 } },
200 { { 0, 0, 0, 0, 0 } },
201 { { 0, 0, 0, 0, 0 } },
202 { { 0, 0, 0, 0, 0 } } } };
203 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } },
204 { { 0, 0, 0, 0, 0 } },
205 { { 0, 0, 0, 0, 0 } },
206 { { 0, 0, 0, 0, 0 } },
207 { { 0, 0, 0, 0, 0 } },
208 { { 0, 0, 0, 0, 0 } },
209 { { 0, 0, 0, 0, 0 } } } };
210 static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } },
211 { { 0x00054000, 0x02425C00, 0, 0, 0 } },
212 { { 0, 0, 0, 0, 0 } },
213 { { 0, 0, 0, 0, 0 } },
214 { { 0, 0, 0, 0, 0 } },
215 { { 0, 0, 0, 0, 0 } },
216 { { 0, 0, 0, 0, 0 } } } };
217 static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } },
218 { { 0, 0, 0, 0, 0 } },
219 { { 0, 0, 0, 0, 0 } },
220 { { 0, 0, 0, 0, 0 } },
221 { { 0, 0, 0, 0, 0 } },
222 { { 0, 0, 0, 0, 0 } },
223 { { 0, 0, 0, 0, 0 } } } };
224 static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } },
225 { { 0, 0, 0, 0, 0 } },
226 { { 0, 0, 0, 0, 0 } },
227 { { 0, 0, 0, 0, 0 } },
228 { { 0, 0, 0, 0, 0 } },
229 { { 0, 0, 0, 0, 0 } },
230 { { 0, 0, 0, 0, 0 } } } };
233 #define ACP_BASE__INST0_SEG0 0x02403800
234 #define ACP_BASE__INST0_SEG1 0x00480000
235 #define ACP_BASE__INST0_SEG2 0
236 #define ACP_BASE__INST0_SEG3 0
237 #define ACP_BASE__INST0_SEG4 0
239 #define ACP_BASE__INST1_SEG0 0
240 #define ACP_BASE__INST1_SEG1 0
241 #define ACP_BASE__INST1_SEG2 0
242 #define ACP_BASE__INST1_SEG3 0
243 #define ACP_BASE__INST1_SEG4 0
245 #define ACP_BASE__INST2_SEG0 0
246 #define ACP_BASE__INST2_SEG1 0
247 #define ACP_BASE__INST2_SEG2 0
248 #define ACP_BASE__INST2_SEG3 0
249 #define ACP_BASE__INST2_SEG4 0
251 #define ACP_BASE__INST3_SEG0 0
252 #define ACP_BASE__INST3_SEG1 0
253 #define ACP_BASE__INST3_SEG2 0
254 #define ACP_BASE__INST3_SEG3 0
255 #define ACP_BASE__INST3_SEG4 0
257 #define ACP_BASE__INST4_SEG0 0
258 #define ACP_BASE__INST4_SEG1 0
259 #define ACP_BASE__INST4_SEG2 0
260 #define ACP_BASE__INST4_SEG3 0
261 #define ACP_BASE__INST4_SEG4 0
263 #define ACP_BASE__INST5_SEG0 0
264 #define ACP_BASE__INST5_SEG1 0
265 #define ACP_BASE__INST5_SEG2 0
266 #define ACP_BASE__INST5_SEG3 0
267 #define ACP_BASE__INST5_SEG4 0
269 #define ACP_BASE__INST6_SEG0 0
270 #define ACP_BASE__INST6_SEG1 0
271 #define ACP_BASE__INST6_SEG2 0
272 #define ACP_BASE__INST6_SEG3 0
273 #define ACP_BASE__INST6_SEG4 0
275 #define ATHUB_BASE__INST0_SEG0 0x00000C20
276 #define ATHUB_BASE__INST0_SEG1 0x02408C00
277 #define ATHUB_BASE__INST0_SEG2 0
278 #define ATHUB_BASE__INST0_SEG3 0
279 #define ATHUB_BASE__INST0_SEG4 0
281 #define ATHUB_BASE__INST1_SEG0 0
282 #define ATHUB_BASE__INST1_SEG1 0
283 #define ATHUB_BASE__INST1_SEG2 0
284 #define ATHUB_BASE__INST1_SEG3 0
285 #define ATHUB_BASE__INST1_SEG4 0
287 #define ATHUB_BASE__INST2_SEG0 0
288 #define ATHUB_BASE__INST2_SEG1 0
289 #define ATHUB_BASE__INST2_SEG2 0
290 #define ATHUB_BASE__INST2_SEG3 0
291 #define ATHUB_BASE__INST2_SEG4 0
293 #define ATHUB_BASE__INST3_SEG0 0
294 #define ATHUB_BASE__INST3_SEG1 0
295 #define ATHUB_BASE__INST3_SEG2 0
296 #define ATHUB_BASE__INST3_SEG3 0
297 #define ATHUB_BASE__INST3_SEG4 0
299 #define ATHUB_BASE__INST4_SEG0 0
300 #define ATHUB_BASE__INST4_SEG1 0
301 #define ATHUB_BASE__INST4_SEG2 0
302 #define ATHUB_BASE__INST4_SEG3 0
303 #define ATHUB_BASE__INST4_SEG4 0
305 #define ATHUB_BASE__INST5_SEG0 0
306 #define ATHUB_BASE__INST5_SEG1 0
307 #define ATHUB_BASE__INST5_SEG2 0
308 #define ATHUB_BASE__INST5_SEG3 0
309 #define ATHUB_BASE__INST5_SEG4 0
311 #define ATHUB_BASE__INST6_SEG0 0
312 #define ATHUB_BASE__INST6_SEG1 0
313 #define ATHUB_BASE__INST6_SEG2 0
314 #define ATHUB_BASE__INST6_SEG3 0
315 #define ATHUB_BASE__INST6_SEG4 0
317 #define CLK_BASE__INST0_SEG0 0x00016C00
318 #define CLK_BASE__INST0_SEG1 0x00016E00
319 #define CLK_BASE__INST0_SEG2 0x00017000
320 #define CLK_BASE__INST0_SEG3 0x00017E00
321 #define CLK_BASE__INST0_SEG4 0
323 #define CLK_BASE__INST1_SEG0 0
324 #define CLK_BASE__INST1_SEG1 0
325 #define CLK_BASE__INST1_SEG2 0
326 #define CLK_BASE__INST1_SEG3 0
327 #define CLK_BASE__INST1_SEG4 0
329 #define CLK_BASE__INST2_SEG0 0
330 #define CLK_BASE__INST2_SEG1 0
331 #define CLK_BASE__INST2_SEG2 0
332 #define CLK_BASE__INST2_SEG3 0
333 #define CLK_BASE__INST2_SEG4 0
335 #define CLK_BASE__INST3_SEG0 0
336 #define CLK_BASE__INST3_SEG1 0
337 #define CLK_BASE__INST3_SEG2 0
338 #define CLK_BASE__INST3_SEG3 0
339 #define CLK_BASE__INST3_SEG4 0
341 #define CLK_BASE__INST4_SEG0 0
342 #define CLK_BASE__INST4_SEG1 0
343 #define CLK_BASE__INST4_SEG2 0
344 #define CLK_BASE__INST4_SEG3 0
345 #define CLK_BASE__INST4_SEG4 0
347 #define CLK_BASE__INST5_SEG0 0
348 #define CLK_BASE__INST5_SEG1 0
349 #define CLK_BASE__INST5_SEG2 0
350 #define CLK_BASE__INST5_SEG3 0
351 #define CLK_BASE__INST5_SEG4 0
353 #define CLK_BASE__INST6_SEG0 0
354 #define CLK_BASE__INST6_SEG1 0
355 #define CLK_BASE__INST6_SEG2 0
356 #define CLK_BASE__INST6_SEG3 0
357 #define CLK_BASE__INST6_SEG4 0
359 #define DBGU_IO0_BASE__INST0_SEG0 0x000001E0
360 #define DBGU_IO0_BASE__INST0_SEG1 0x0240B400
361 #define DBGU_IO0_BASE__INST0_SEG2 0
362 #define DBGU_IO0_BASE__INST0_SEG3 0
363 #define DBGU_IO0_BASE__INST0_SEG4 0
365 #define DBGU_IO0_BASE__INST1_SEG0 0
366 #define DBGU_IO0_BASE__INST1_SEG1 0
367 #define DBGU_IO0_BASE__INST1_SEG2 0
368 #define DBGU_IO0_BASE__INST1_SEG3 0
369 #define DBGU_IO0_BASE__INST1_SEG4 0
371 #define DBGU_IO0_BASE__INST2_SEG0 0
372 #define DBGU_IO0_BASE__INST2_SEG1 0
373 #define DBGU_IO0_BASE__INST2_SEG2 0
374 #define DBGU_IO0_BASE__INST2_SEG3 0
375 #define DBGU_IO0_BASE__INST2_SEG4 0
377 #define DBGU_IO0_BASE__INST3_SEG0 0
378 #define DBGU_IO0_BASE__INST3_SEG1 0
379 #define DBGU_IO0_BASE__INST3_SEG2 0
380 #define DBGU_IO0_BASE__INST3_SEG3 0
381 #define DBGU_IO0_BASE__INST3_SEG4 0
383 #define DBGU_IO0_BASE__INST4_SEG0 0
384 #define DBGU_IO0_BASE__INST4_SEG1 0
385 #define DBGU_IO0_BASE__INST4_SEG2 0
386 #define DBGU_IO0_BASE__INST4_SEG3 0
387 #define DBGU_IO0_BASE__INST4_SEG4 0
389 #define DBGU_IO0_BASE__INST5_SEG0 0
390 #define DBGU_IO0_BASE__INST5_SEG1 0
391 #define DBGU_IO0_BASE__INST5_SEG2 0
392 #define DBGU_IO0_BASE__INST5_SEG3 0
393 #define DBGU_IO0_BASE__INST5_SEG4 0
395 #define DBGU_IO0_BASE__INST6_SEG0 0
396 #define DBGU_IO0_BASE__INST6_SEG1 0
397 #define DBGU_IO0_BASE__INST6_SEG2 0
398 #define DBGU_IO0_BASE__INST6_SEG3 0
399 #define DBGU_IO0_BASE__INST6_SEG4 0
401 #define DF_BASE__INST0_SEG0 0x00007000
402 #define DF_BASE__INST0_SEG1 0x0240B800
403 #define DF_BASE__INST0_SEG2 0
404 #define DF_BASE__INST0_SEG3 0
405 #define DF_BASE__INST0_SEG4 0
407 #define DF_BASE__INST1_SEG0 0
408 #define DF_BASE__INST1_SEG1 0
409 #define DF_BASE__INST1_SEG2 0
410 #define DF_BASE__INST1_SEG3 0
411 #define DF_BASE__INST1_SEG4 0
413 #define DF_BASE__INST2_SEG0 0
414 #define DF_BASE__INST2_SEG1 0
415 #define DF_BASE__INST2_SEG2 0
416 #define DF_BASE__INST2_SEG3 0
417 #define DF_BASE__INST2_SEG4 0
419 #define DF_BASE__INST3_SEG0 0
420 #define DF_BASE__INST3_SEG1 0
421 #define DF_BASE__INST3_SEG2 0
422 #define DF_BASE__INST3_SEG3 0
423 #define DF_BASE__INST3_SEG4 0
425 #define DF_BASE__INST4_SEG0 0
426 #define DF_BASE__INST4_SEG1 0
427 #define DF_BASE__INST4_SEG2 0
428 #define DF_BASE__INST4_SEG3 0
429 #define DF_BASE__INST4_SEG4 0
431 #define DF_BASE__INST5_SEG0 0
432 #define DF_BASE__INST5_SEG1 0
433 #define DF_BASE__INST5_SEG2 0
434 #define DF_BASE__INST5_SEG3 0
435 #define DF_BASE__INST5_SEG4 0
437 #define DF_BASE__INST6_SEG0 0
438 #define DF_BASE__INST6_SEG1 0
439 #define DF_BASE__INST6_SEG2 0
440 #define DF_BASE__INST6_SEG3 0
441 #define DF_BASE__INST6_SEG4 0
443 #define DIO_BASE__INST0_SEG0 0x02404000
444 #define DIO_BASE__INST0_SEG1 0
445 #define DIO_BASE__INST0_SEG2 0
446 #define DIO_BASE__INST0_SEG3 0
447 #define DIO_BASE__INST0_SEG4 0
449 #define DIO_BASE__INST1_SEG0 0
450 #define DIO_BASE__INST1_SEG1 0
451 #define DIO_BASE__INST1_SEG2 0
452 #define DIO_BASE__INST1_SEG3 0
453 #define DIO_BASE__INST1_SEG4 0
455 #define DIO_BASE__INST2_SEG0 0
456 #define DIO_BASE__INST2_SEG1 0
457 #define DIO_BASE__INST2_SEG2 0
458 #define DIO_BASE__INST2_SEG3 0
459 #define DIO_BASE__INST2_SEG4 0
461 #define DIO_BASE__INST3_SEG0 0
462 #define DIO_BASE__INST3_SEG1 0
463 #define DIO_BASE__INST3_SEG2 0
464 #define DIO_BASE__INST3_SEG3 0
465 #define DIO_BASE__INST3_SEG4 0
467 #define DIO_BASE__INST4_SEG0 0
468 #define DIO_BASE__INST4_SEG1 0
469 #define DIO_BASE__INST4_SEG2 0
470 #define DIO_BASE__INST4_SEG3 0
471 #define DIO_BASE__INST4_SEG4 0
473 #define DIO_BASE__INST5_SEG0 0
474 #define DIO_BASE__INST5_SEG1 0
475 #define DIO_BASE__INST5_SEG2 0
476 #define DIO_BASE__INST5_SEG3 0
477 #define DIO_BASE__INST5_SEG4 0
479 #define DIO_BASE__INST6_SEG0 0
480 #define DIO_BASE__INST6_SEG1 0
481 #define DIO_BASE__INST6_SEG2 0
482 #define DIO_BASE__INST6_SEG3 0
483 #define DIO_BASE__INST6_SEG4 0
485 #define DMU_BASE__INST0_SEG0 0x00000012
486 #define DMU_BASE__INST0_SEG1 0x000000C0
487 #define DMU_BASE__INST0_SEG2 0x000034C0
488 #define DMU_BASE__INST0_SEG3 0x00009000
489 #define DMU_BASE__INST0_SEG4 0x02403C00
491 #define DMU_BASE__INST1_SEG0 0
492 #define DMU_BASE__INST1_SEG1 0
493 #define DMU_BASE__INST1_SEG2 0
494 #define DMU_BASE__INST1_SEG3 0
495 #define DMU_BASE__INST1_SEG4 0
497 #define DMU_BASE__INST2_SEG0 0
498 #define DMU_BASE__INST2_SEG1 0
499 #define DMU_BASE__INST2_SEG2 0
500 #define DMU_BASE__INST2_SEG3 0
501 #define DMU_BASE__INST2_SEG4 0
503 #define DMU_BASE__INST3_SEG0 0
504 #define DMU_BASE__INST3_SEG1 0
505 #define DMU_BASE__INST3_SEG2 0
506 #define DMU_BASE__INST3_SEG3 0
507 #define DMU_BASE__INST3_SEG4 0
509 #define DMU_BASE__INST4_SEG0 0
510 #define DMU_BASE__INST4_SEG1 0
511 #define DMU_BASE__INST4_SEG2 0
512 #define DMU_BASE__INST4_SEG3 0
513 #define DMU_BASE__INST4_SEG4 0
515 #define DMU_BASE__INST5_SEG0 0
516 #define DMU_BASE__INST5_SEG1 0
517 #define DMU_BASE__INST5_SEG2 0
518 #define DMU_BASE__INST5_SEG3 0
519 #define DMU_BASE__INST5_SEG4 0
521 #define DMU_BASE__INST6_SEG0 0
522 #define DMU_BASE__INST6_SEG1 0
523 #define DMU_BASE__INST6_SEG2 0
524 #define DMU_BASE__INST6_SEG3 0
525 #define DMU_BASE__INST6_SEG4 0
527 #define DPCS_BASE__INST0_SEG0 0x00000012
528 #define DPCS_BASE__INST0_SEG1 0x000000C0
529 #define DPCS_BASE__INST0_SEG2 0x000034C0
530 #define DPCS_BASE__INST0_SEG3 0x00009000
531 #define DPCS_BASE__INST0_SEG4 0x02403C00
533 #define DPCS_BASE__INST1_SEG0 0
534 #define DPCS_BASE__INST1_SEG1 0
535 #define DPCS_BASE__INST1_SEG2 0
536 #define DPCS_BASE__INST1_SEG3 0
537 #define DPCS_BASE__INST1_SEG4 0
539 #define DPCS_BASE__INST2_SEG0 0
540 #define DPCS_BASE__INST2_SEG1 0
541 #define DPCS_BASE__INST2_SEG2 0
542 #define DPCS_BASE__INST2_SEG3 0
543 #define DPCS_BASE__INST2_SEG4 0
545 #define DPCS_BASE__INST3_SEG0 0
546 #define DPCS_BASE__INST3_SEG1 0
547 #define DPCS_BASE__INST3_SEG2 0
548 #define DPCS_BASE__INST3_SEG3 0
549 #define DPCS_BASE__INST3_SEG4 0
551 #define DPCS_BASE__INST4_SEG0 0
552 #define DPCS_BASE__INST4_SEG1 0
553 #define DPCS_BASE__INST4_SEG2 0
554 #define DPCS_BASE__INST4_SEG3 0
555 #define DPCS_BASE__INST4_SEG4 0
557 #define DPCS_BASE__INST5_SEG0 0
558 #define DPCS_BASE__INST5_SEG1 0
559 #define DPCS_BASE__INST5_SEG2 0
560 #define DPCS_BASE__INST5_SEG3 0
561 #define DPCS_BASE__INST5_SEG4 0
563 #define DPCS_BASE__INST6_SEG0 0
564 #define DPCS_BASE__INST6_SEG1 0
565 #define DPCS_BASE__INST6_SEG2 0
566 #define DPCS_BASE__INST6_SEG3 0
567 #define DPCS_BASE__INST6_SEG4 0
569 #define FUSE_BASE__INST0_SEG0 0x00017400
570 #define FUSE_BASE__INST0_SEG1 0x02401400
571 #define FUSE_BASE__INST0_SEG2 0
572 #define FUSE_BASE__INST0_SEG3 0
573 #define FUSE_BASE__INST0_SEG4 0
575 #define FUSE_BASE__INST1_SEG0 0
576 #define FUSE_BASE__INST1_SEG1 0
577 #define FUSE_BASE__INST1_SEG2 0
578 #define FUSE_BASE__INST1_SEG3 0
579 #define FUSE_BASE__INST1_SEG4 0
581 #define FUSE_BASE__INST2_SEG0 0
582 #define FUSE_BASE__INST2_SEG1 0
583 #define FUSE_BASE__INST2_SEG2 0
584 #define FUSE_BASE__INST2_SEG3 0
585 #define FUSE_BASE__INST2_SEG4 0
587 #define FUSE_BASE__INST3_SEG0 0
588 #define FUSE_BASE__INST3_SEG1 0
589 #define FUSE_BASE__INST3_SEG2 0
590 #define FUSE_BASE__INST3_SEG3 0
591 #define FUSE_BASE__INST3_SEG4 0
593 #define FUSE_BASE__INST4_SEG0 0
594 #define FUSE_BASE__INST4_SEG1 0
595 #define FUSE_BASE__INST4_SEG2 0
596 #define FUSE_BASE__INST4_SEG3 0
597 #define FUSE_BASE__INST4_SEG4 0
599 #define FUSE_BASE__INST5_SEG0 0
600 #define FUSE_BASE__INST5_SEG1 0
601 #define FUSE_BASE__INST5_SEG2 0
602 #define FUSE_BASE__INST5_SEG3 0
603 #define FUSE_BASE__INST5_SEG4 0
605 #define FUSE_BASE__INST6_SEG0 0
606 #define FUSE_BASE__INST6_SEG1 0
607 #define FUSE_BASE__INST6_SEG2 0
608 #define FUSE_BASE__INST6_SEG3 0
609 #define FUSE_BASE__INST6_SEG4 0
611 #define GC_BASE__INST0_SEG0 0x00002000
612 #define GC_BASE__INST0_SEG1 0x0000A000
613 #define GC_BASE__INST0_SEG2 0x02402C00
614 #define GC_BASE__INST0_SEG3 0
615 #define GC_BASE__INST0_SEG4 0
617 #define GC_BASE__INST1_SEG0 0
618 #define GC_BASE__INST1_SEG1 0
619 #define GC_BASE__INST1_SEG2 0
620 #define GC_BASE__INST1_SEG3 0
621 #define GC_BASE__INST1_SEG4 0
623 #define GC_BASE__INST2_SEG0 0
624 #define GC_BASE__INST2_SEG1 0
625 #define GC_BASE__INST2_SEG2 0
626 #define GC_BASE__INST2_SEG3 0
627 #define GC_BASE__INST2_SEG4 0
629 #define GC_BASE__INST3_SEG0 0
630 #define GC_BASE__INST3_SEG1 0
631 #define GC_BASE__INST3_SEG2 0
632 #define GC_BASE__INST3_SEG3 0
633 #define GC_BASE__INST3_SEG4 0
635 #define GC_BASE__INST4_SEG0 0
636 #define GC_BASE__INST4_SEG1 0
637 #define GC_BASE__INST4_SEG2 0
638 #define GC_BASE__INST4_SEG3 0
639 #define GC_BASE__INST4_SEG4 0
641 #define GC_BASE__INST5_SEG0 0
642 #define GC_BASE__INST5_SEG1 0
643 #define GC_BASE__INST5_SEG2 0
644 #define GC_BASE__INST5_SEG3 0
645 #define GC_BASE__INST5_SEG4 0
647 #define GC_BASE__INST6_SEG0 0
648 #define GC_BASE__INST6_SEG1 0
649 #define GC_BASE__INST6_SEG2 0
650 #define GC_BASE__INST6_SEG3 0
651 #define GC_BASE__INST6_SEG4 0
653 #define HDA_BASE__INST0_SEG0 0x02404800
654 #define HDA_BASE__INST0_SEG1 0x004C0000
655 #define HDA_BASE__INST0_SEG2 0
656 #define HDA_BASE__INST0_SEG3 0
657 #define HDA_BASE__INST0_SEG4 0
659 #define HDA_BASE__INST1_SEG0 0
660 #define HDA_BASE__INST1_SEG1 0
661 #define HDA_BASE__INST1_SEG2 0
662 #define HDA_BASE__INST1_SEG3 0
663 #define HDA_BASE__INST1_SEG4 0
665 #define HDA_BASE__INST2_SEG0 0
666 #define HDA_BASE__INST2_SEG1 0
667 #define HDA_BASE__INST2_SEG2 0
668 #define HDA_BASE__INST2_SEG3 0
669 #define HDA_BASE__INST2_SEG4 0
671 #define HDA_BASE__INST3_SEG0 0
672 #define HDA_BASE__INST3_SEG1 0
673 #define HDA_BASE__INST3_SEG2 0
674 #define HDA_BASE__INST3_SEG3 0
675 #define HDA_BASE__INST3_SEG4 0
677 #define HDA_BASE__INST4_SEG0 0
678 #define HDA_BASE__INST4_SEG1 0
679 #define HDA_BASE__INST4_SEG2 0
680 #define HDA_BASE__INST4_SEG3 0
681 #define HDA_BASE__INST4_SEG4 0
683 #define HDA_BASE__INST5_SEG0 0
684 #define HDA_BASE__INST5_SEG1 0
685 #define HDA_BASE__INST5_SEG2 0
686 #define HDA_BASE__INST5_SEG3 0
687 #define HDA_BASE__INST5_SEG4 0
689 #define HDA_BASE__INST6_SEG0 0
690 #define HDA_BASE__INST6_SEG1 0
691 #define HDA_BASE__INST6_SEG2 0
692 #define HDA_BASE__INST6_SEG3 0
693 #define HDA_BASE__INST6_SEG4 0
695 #define HDP_BASE__INST0_SEG0 0x00000F20
696 #define HDP_BASE__INST0_SEG1 0x0240A400
697 #define HDP_BASE__INST0_SEG2 0
698 #define HDP_BASE__INST0_SEG3 0
699 #define HDP_BASE__INST0_SEG4 0
701 #define HDP_BASE__INST1_SEG0 0
702 #define HDP_BASE__INST1_SEG1 0
703 #define HDP_BASE__INST1_SEG2 0
704 #define HDP_BASE__INST1_SEG3 0
705 #define HDP_BASE__INST1_SEG4 0
707 #define HDP_BASE__INST2_SEG0 0
708 #define HDP_BASE__INST2_SEG1 0
709 #define HDP_BASE__INST2_SEG2 0
710 #define HDP_BASE__INST2_SEG3 0
711 #define HDP_BASE__INST2_SEG4 0
713 #define HDP_BASE__INST3_SEG0 0
714 #define HDP_BASE__INST3_SEG1 0
715 #define HDP_BASE__INST3_SEG2 0
716 #define HDP_BASE__INST3_SEG3 0
717 #define HDP_BASE__INST3_SEG4 0
719 #define HDP_BASE__INST4_SEG0 0
720 #define HDP_BASE__INST4_SEG1 0
721 #define HDP_BASE__INST4_SEG2 0
722 #define HDP_BASE__INST4_SEG3 0
723 #define HDP_BASE__INST4_SEG4 0
725 #define HDP_BASE__INST5_SEG0 0
726 #define HDP_BASE__INST5_SEG1 0
727 #define HDP_BASE__INST5_SEG2 0
728 #define HDP_BASE__INST5_SEG3 0
729 #define HDP_BASE__INST5_SEG4 0
731 #define HDP_BASE__INST6_SEG0 0
732 #define HDP_BASE__INST6_SEG1 0
733 #define HDP_BASE__INST6_SEG2 0
734 #define HDP_BASE__INST6_SEG3 0
735 #define HDP_BASE__INST6_SEG4 0
737 #define IOHC0_BASE__INST0_SEG0 0x00010000
738 #define IOHC0_BASE__INST0_SEG1 0x02406000
739 #define IOHC0_BASE__INST0_SEG2 0x04EC0000
740 #define IOHC0_BASE__INST0_SEG3 0
741 #define IOHC0_BASE__INST0_SEG4 0
743 #define IOHC0_BASE__INST1_SEG0 0
744 #define IOHC0_BASE__INST1_SEG1 0
745 #define IOHC0_BASE__INST1_SEG2 0
746 #define IOHC0_BASE__INST1_SEG3 0
747 #define IOHC0_BASE__INST1_SEG4 0
749 #define IOHC0_BASE__INST2_SEG0 0
750 #define IOHC0_BASE__INST2_SEG1 0
751 #define IOHC0_BASE__INST2_SEG2 0
752 #define IOHC0_BASE__INST2_SEG3 0
753 #define IOHC0_BASE__INST2_SEG4 0
755 #define IOHC0_BASE__INST3_SEG0 0
756 #define IOHC0_BASE__INST3_SEG1 0
757 #define IOHC0_BASE__INST3_SEG2 0
758 #define IOHC0_BASE__INST3_SEG3 0
759 #define IOHC0_BASE__INST3_SEG4 0
761 #define IOHC0_BASE__INST4_SEG0 0
762 #define IOHC0_BASE__INST4_SEG1 0
763 #define IOHC0_BASE__INST4_SEG2 0
764 #define IOHC0_BASE__INST4_SEG3 0
765 #define IOHC0_BASE__INST4_SEG4 0
767 #define IOHC0_BASE__INST5_SEG0 0
768 #define IOHC0_BASE__INST5_SEG1 0
769 #define IOHC0_BASE__INST5_SEG2 0
770 #define IOHC0_BASE__INST5_SEG3 0
771 #define IOHC0_BASE__INST5_SEG4 0
773 #define IOHC0_BASE__INST6_SEG0 0
774 #define IOHC0_BASE__INST6_SEG1 0
775 #define IOHC0_BASE__INST6_SEG2 0
776 #define IOHC0_BASE__INST6_SEG3 0
777 #define IOHC0_BASE__INST6_SEG4 0
779 #define ISP_BASE__INST0_SEG0 0x00018000
780 #define ISP_BASE__INST0_SEG1 0x0240B000
781 #define ISP_BASE__INST0_SEG2 0
782 #define ISP_BASE__INST0_SEG3 0
783 #define ISP_BASE__INST0_SEG4 0
785 #define ISP_BASE__INST1_SEG0 0
786 #define ISP_BASE__INST1_SEG1 0
787 #define ISP_BASE__INST1_SEG2 0
788 #define ISP_BASE__INST1_SEG3 0
789 #define ISP_BASE__INST1_SEG4 0
791 #define ISP_BASE__INST2_SEG0 0
792 #define ISP_BASE__INST2_SEG1 0
793 #define ISP_BASE__INST2_SEG2 0
794 #define ISP_BASE__INST2_SEG3 0
795 #define ISP_BASE__INST2_SEG4 0
797 #define ISP_BASE__INST3_SEG0 0
798 #define ISP_BASE__INST3_SEG1 0
799 #define ISP_BASE__INST3_SEG2 0
800 #define ISP_BASE__INST3_SEG3 0
801 #define ISP_BASE__INST3_SEG4 0
803 #define ISP_BASE__INST4_SEG0 0
804 #define ISP_BASE__INST4_SEG1 0
805 #define ISP_BASE__INST4_SEG2 0
806 #define ISP_BASE__INST4_SEG3 0
807 #define ISP_BASE__INST4_SEG4 0
809 #define ISP_BASE__INST5_SEG0 0
810 #define ISP_BASE__INST5_SEG1 0
811 #define ISP_BASE__INST5_SEG2 0
812 #define ISP_BASE__INST5_SEG3 0
813 #define ISP_BASE__INST5_SEG4 0
815 #define ISP_BASE__INST6_SEG0 0
816 #define ISP_BASE__INST6_SEG1 0
817 #define ISP_BASE__INST6_SEG2 0
818 #define ISP_BASE__INST6_SEG3 0
819 #define ISP_BASE__INST6_SEG4 0
821 #define L2IMU0_BASE__INST0_SEG0 0x00007DC0
822 #define L2IMU0_BASE__INST0_SEG1 0x02407000
823 #define L2IMU0_BASE__INST0_SEG2 0x00900000
824 #define L2IMU0_BASE__INST0_SEG3 0x04FC0000
825 #define L2IMU0_BASE__INST0_SEG4 0x055C0000
827 #define L2IMU0_BASE__INST1_SEG0 0
828 #define L2IMU0_BASE__INST1_SEG1 0
829 #define L2IMU0_BASE__INST1_SEG2 0
830 #define L2IMU0_BASE__INST1_SEG3 0
831 #define L2IMU0_BASE__INST1_SEG4 0
833 #define L2IMU0_BASE__INST2_SEG0 0
834 #define L2IMU0_BASE__INST2_SEG1 0
835 #define L2IMU0_BASE__INST2_SEG2 0
836 #define L2IMU0_BASE__INST2_SEG3 0
837 #define L2IMU0_BASE__INST2_SEG4 0
839 #define L2IMU0_BASE__INST3_SEG0 0
840 #define L2IMU0_BASE__INST3_SEG1 0
841 #define L2IMU0_BASE__INST3_SEG2 0
842 #define L2IMU0_BASE__INST3_SEG3 0
843 #define L2IMU0_BASE__INST3_SEG4 0
845 #define L2IMU0_BASE__INST4_SEG0 0
846 #define L2IMU0_BASE__INST4_SEG1 0
847 #define L2IMU0_BASE__INST4_SEG2 0
848 #define L2IMU0_BASE__INST4_SEG3 0
849 #define L2IMU0_BASE__INST4_SEG4 0
851 #define L2IMU0_BASE__INST5_SEG0 0
852 #define L2IMU0_BASE__INST5_SEG1 0
853 #define L2IMU0_BASE__INST5_SEG2 0
854 #define L2IMU0_BASE__INST5_SEG3 0
855 #define L2IMU0_BASE__INST5_SEG4 0
857 #define L2IMU0_BASE__INST6_SEG0 0
858 #define L2IMU0_BASE__INST6_SEG1 0
859 #define L2IMU0_BASE__INST6_SEG2 0
860 #define L2IMU0_BASE__INST6_SEG3 0
861 #define L2IMU0_BASE__INST6_SEG4 0
863 #define MMHUB_BASE__INST0_SEG0 0x0001A000
864 #define MMHUB_BASE__INST0_SEG1 0x02408800
865 #define MMHUB_BASE__INST0_SEG2 0
866 #define MMHUB_BASE__INST0_SEG3 0
867 #define MMHUB_BASE__INST0_SEG4 0
869 #define MMHUB_BASE__INST1_SEG0 0
870 #define MMHUB_BASE__INST1_SEG1 0
871 #define MMHUB_BASE__INST1_SEG2 0
872 #define MMHUB_BASE__INST1_SEG3 0
873 #define MMHUB_BASE__INST1_SEG4 0
875 #define MMHUB_BASE__INST2_SEG0 0
876 #define MMHUB_BASE__INST2_SEG1 0
877 #define MMHUB_BASE__INST2_SEG2 0
878 #define MMHUB_BASE__INST2_SEG3 0
879 #define MMHUB_BASE__INST2_SEG4 0
881 #define MMHUB_BASE__INST3_SEG0 0
882 #define MMHUB_BASE__INST3_SEG1 0
883 #define MMHUB_BASE__INST3_SEG2 0
884 #define MMHUB_BASE__INST3_SEG3 0
885 #define MMHUB_BASE__INST3_SEG4 0
887 #define MMHUB_BASE__INST4_SEG0 0
888 #define MMHUB_BASE__INST4_SEG1 0
889 #define MMHUB_BASE__INST4_SEG2 0
890 #define MMHUB_BASE__INST4_SEG3 0
891 #define MMHUB_BASE__INST4_SEG4 0
893 #define MMHUB_BASE__INST5_SEG0 0
894 #define MMHUB_BASE__INST5_SEG1 0
895 #define MMHUB_BASE__INST5_SEG2 0
896 #define MMHUB_BASE__INST5_SEG3 0
897 #define MMHUB_BASE__INST5_SEG4 0
899 #define MMHUB_BASE__INST6_SEG0 0
900 #define MMHUB_BASE__INST6_SEG1 0
901 #define MMHUB_BASE__INST6_SEG2 0
902 #define MMHUB_BASE__INST6_SEG3 0
903 #define MMHUB_BASE__INST6_SEG4 0
905 #define MP0_BASE__INST0_SEG0 0x00016000
906 #define MP0_BASE__INST0_SEG1 0x0243FC00
907 #define MP0_BASE__INST0_SEG2 0x00DC0000
908 #define MP0_BASE__INST0_SEG3 0x00E00000
909 #define MP0_BASE__INST0_SEG4 0x00E40000
911 #define MP0_BASE__INST1_SEG0 0
912 #define MP0_BASE__INST1_SEG1 0
913 #define MP0_BASE__INST1_SEG2 0
914 #define MP0_BASE__INST1_SEG3 0
915 #define MP0_BASE__INST1_SEG4 0
917 #define MP0_BASE__INST2_SEG0 0
918 #define MP0_BASE__INST2_SEG1 0
919 #define MP0_BASE__INST2_SEG2 0
920 #define MP0_BASE__INST2_SEG3 0
921 #define MP0_BASE__INST2_SEG4 0
923 #define MP0_BASE__INST3_SEG0 0
924 #define MP0_BASE__INST3_SEG1 0
925 #define MP0_BASE__INST3_SEG2 0
926 #define MP0_BASE__INST3_SEG3 0
927 #define MP0_BASE__INST3_SEG4 0
929 #define MP0_BASE__INST4_SEG0 0
930 #define MP0_BASE__INST4_SEG1 0
931 #define MP0_BASE__INST4_SEG2 0
932 #define MP0_BASE__INST4_SEG3 0
933 #define MP0_BASE__INST4_SEG4 0
935 #define MP0_BASE__INST5_SEG0 0
936 #define MP0_BASE__INST5_SEG1 0
937 #define MP0_BASE__INST5_SEG2 0
938 #define MP0_BASE__INST5_SEG3 0
939 #define MP0_BASE__INST5_SEG4 0
941 #define MP0_BASE__INST6_SEG0 0
942 #define MP0_BASE__INST6_SEG1 0
943 #define MP0_BASE__INST6_SEG2 0
944 #define MP0_BASE__INST6_SEG3 0
945 #define MP0_BASE__INST6_SEG4 0
947 #define MP1_BASE__INST0_SEG0 0x00016200
948 #define MP1_BASE__INST0_SEG1 0x02400400
949 #define MP1_BASE__INST0_SEG2 0x00E80000
950 #define MP1_BASE__INST0_SEG3 0x00EC0000
951 #define MP1_BASE__INST0_SEG4 0x00F00000
953 #define MP1_BASE__INST1_SEG0 0
954 #define MP1_BASE__INST1_SEG1 0
955 #define MP1_BASE__INST1_SEG2 0
956 #define MP1_BASE__INST1_SEG3 0
957 #define MP1_BASE__INST1_SEG4 0
959 #define MP1_BASE__INST2_SEG0 0
960 #define MP1_BASE__INST2_SEG1 0
961 #define MP1_BASE__INST2_SEG2 0
962 #define MP1_BASE__INST2_SEG3 0
963 #define MP1_BASE__INST2_SEG4 0
965 #define MP1_BASE__INST3_SEG0 0
966 #define MP1_BASE__INST3_SEG1 0
967 #define MP1_BASE__INST3_SEG2 0
968 #define MP1_BASE__INST3_SEG3 0
969 #define MP1_BASE__INST3_SEG4 0
971 #define MP1_BASE__INST4_SEG0 0
972 #define MP1_BASE__INST4_SEG1 0
973 #define MP1_BASE__INST4_SEG2 0
974 #define MP1_BASE__INST4_SEG3 0
975 #define MP1_BASE__INST4_SEG4 0
977 #define MP1_BASE__INST5_SEG0 0
978 #define MP1_BASE__INST5_SEG1 0
979 #define MP1_BASE__INST5_SEG2 0
980 #define MP1_BASE__INST5_SEG3 0
981 #define MP1_BASE__INST5_SEG4 0
983 #define MP1_BASE__INST6_SEG0 0
984 #define MP1_BASE__INST6_SEG1 0
985 #define MP1_BASE__INST6_SEG2 0
986 #define MP1_BASE__INST6_SEG3 0
987 #define MP1_BASE__INST6_SEG4 0
989 #define NBIF0_BASE__INST0_SEG0 0x00000000
990 #define NBIF0_BASE__INST0_SEG1 0x00000014
991 #define NBIF0_BASE__INST0_SEG2 0x00000D20
992 #define NBIF0_BASE__INST0_SEG3 0x00010400
993 #define NBIF0_BASE__INST0_SEG4 0x0241B000
995 #define NBIF0_BASE__INST1_SEG0 0
996 #define NBIF0_BASE__INST1_SEG1 0
997 #define NBIF0_BASE__INST1_SEG2 0
998 #define NBIF0_BASE__INST1_SEG3 0
999 #define NBIF0_BASE__INST1_SEG4 0
1001 #define NBIF0_BASE__INST2_SEG0 0
1002 #define NBIF0_BASE__INST2_SEG1 0
1003 #define NBIF0_BASE__INST2_SEG2 0
1004 #define NBIF0_BASE__INST2_SEG3 0
1005 #define NBIF0_BASE__INST2_SEG4 0
1007 #define NBIF0_BASE__INST3_SEG0 0
1008 #define NBIF0_BASE__INST3_SEG1 0
1009 #define NBIF0_BASE__INST3_SEG2 0
1010 #define NBIF0_BASE__INST3_SEG3 0
1011 #define NBIF0_BASE__INST3_SEG4 0
1013 #define NBIF0_BASE__INST4_SEG0 0
1014 #define NBIF0_BASE__INST4_SEG1 0
1015 #define NBIF0_BASE__INST4_SEG2 0
1016 #define NBIF0_BASE__INST4_SEG3 0
1017 #define NBIF0_BASE__INST4_SEG4 0
1019 #define NBIF0_BASE__INST5_SEG0 0
1020 #define NBIF0_BASE__INST5_SEG1 0
1021 #define NBIF0_BASE__INST5_SEG2 0
1022 #define NBIF0_BASE__INST5_SEG3 0
1023 #define NBIF0_BASE__INST5_SEG4 0
1025 #define NBIF0_BASE__INST6_SEG0 0
1026 #define NBIF0_BASE__INST6_SEG1 0
1027 #define NBIF0_BASE__INST6_SEG2 0
1028 #define NBIF0_BASE__INST6_SEG3 0
1029 #define NBIF0_BASE__INST6_SEG4 0
1031 #define OSSSYS_BASE__INST0_SEG0 0x000010A0
1032 #define OSSSYS_BASE__INST0_SEG1 0x0240A000
1033 #define OSSSYS_BASE__INST0_SEG2 0
1034 #define OSSSYS_BASE__INST0_SEG3 0
1035 #define OSSSYS_BASE__INST0_SEG4 0
1037 #define OSSSYS_BASE__INST1_SEG0 0
1038 #define OSSSYS_BASE__INST1_SEG1 0
1039 #define OSSSYS_BASE__INST1_SEG2 0
1040 #define OSSSYS_BASE__INST1_SEG3 0
1041 #define OSSSYS_BASE__INST1_SEG4 0
1043 #define OSSSYS_BASE__INST2_SEG0 0
1044 #define OSSSYS_BASE__INST2_SEG1 0
1045 #define OSSSYS_BASE__INST2_SEG2 0
1046 #define OSSSYS_BASE__INST2_SEG3 0
1047 #define OSSSYS_BASE__INST2_SEG4 0
1049 #define OSSSYS_BASE__INST3_SEG0 0
1050 #define OSSSYS_BASE__INST3_SEG1 0
1051 #define OSSSYS_BASE__INST3_SEG2 0
1052 #define OSSSYS_BASE__INST3_SEG3 0
1053 #define OSSSYS_BASE__INST3_SEG4 0
1055 #define OSSSYS_BASE__INST4_SEG0 0
1056 #define OSSSYS_BASE__INST4_SEG1 0
1057 #define OSSSYS_BASE__INST4_SEG2 0
1058 #define OSSSYS_BASE__INST4_SEG3 0
1059 #define OSSSYS_BASE__INST4_SEG4 0
1061 #define OSSSYS_BASE__INST5_SEG0 0
1062 #define OSSSYS_BASE__INST5_SEG1 0
1063 #define OSSSYS_BASE__INST5_SEG2 0
1064 #define OSSSYS_BASE__INST5_SEG3 0
1065 #define OSSSYS_BASE__INST5_SEG4 0
1067 #define OSSSYS_BASE__INST6_SEG0 0
1068 #define OSSSYS_BASE__INST6_SEG1 0
1069 #define OSSSYS_BASE__INST6_SEG2 0
1070 #define OSSSYS_BASE__INST6_SEG3 0
1071 #define OSSSYS_BASE__INST6_SEG4 0
1073 #define PCIE0_BASE__INST0_SEG0 0x02411800
1074 #define PCIE0_BASE__INST0_SEG1 0x04440000
1075 #define PCIE0_BASE__INST0_SEG2 0
1076 #define PCIE0_BASE__INST0_SEG3 0
1077 #define PCIE0_BASE__INST0_SEG4 0
1079 #define PCIE0_BASE__INST1_SEG0 0
1080 #define PCIE0_BASE__INST1_SEG1 0
1081 #define PCIE0_BASE__INST1_SEG2 0
1082 #define PCIE0_BASE__INST1_SEG3 0
1083 #define PCIE0_BASE__INST1_SEG4 0
1085 #define PCIE0_BASE__INST2_SEG0 0
1086 #define PCIE0_BASE__INST2_SEG1 0
1087 #define PCIE0_BASE__INST2_SEG2 0
1088 #define PCIE0_BASE__INST2_SEG3 0
1089 #define PCIE0_BASE__INST2_SEG4 0
1091 #define PCIE0_BASE__INST3_SEG0 0
1092 #define PCIE0_BASE__INST3_SEG1 0
1093 #define PCIE0_BASE__INST3_SEG2 0
1094 #define PCIE0_BASE__INST3_SEG3 0
1095 #define PCIE0_BASE__INST3_SEG4 0
1097 #define PCIE0_BASE__INST4_SEG0 0
1098 #define PCIE0_BASE__INST4_SEG1 0
1099 #define PCIE0_BASE__INST4_SEG2 0
1100 #define PCIE0_BASE__INST4_SEG3 0
1101 #define PCIE0_BASE__INST4_SEG4 0
1103 #define PCIE0_BASE__INST5_SEG0 0
1104 #define PCIE0_BASE__INST5_SEG1 0
1105 #define PCIE0_BASE__INST5_SEG2 0
1106 #define PCIE0_BASE__INST5_SEG3 0
1107 #define PCIE0_BASE__INST5_SEG4 0
1109 #define PCIE0_BASE__INST6_SEG0 0
1110 #define PCIE0_BASE__INST6_SEG1 0
1111 #define PCIE0_BASE__INST6_SEG2 0
1112 #define PCIE0_BASE__INST6_SEG3 0
1113 #define PCIE0_BASE__INST6_SEG4 0
1115 #define SDMA0_BASE__INST0_SEG0 0x00001260
1116 #define SDMA0_BASE__INST0_SEG1 0x0240A800
1117 #define SDMA0_BASE__INST0_SEG2 0
1118 #define SDMA0_BASE__INST0_SEG3 0
1119 #define SDMA0_BASE__INST0_SEG4 0
1121 #define SDMA0_BASE__INST1_SEG0 0
1122 #define SDMA0_BASE__INST1_SEG1 0
1123 #define SDMA0_BASE__INST1_SEG2 0
1124 #define SDMA0_BASE__INST1_SEG3 0
1125 #define SDMA0_BASE__INST1_SEG4 0
1127 #define SDMA0_BASE__INST2_SEG0 0
1128 #define SDMA0_BASE__INST2_SEG1 0
1129 #define SDMA0_BASE__INST2_SEG2 0
1130 #define SDMA0_BASE__INST2_SEG3 0
1131 #define SDMA0_BASE__INST2_SEG4 0
1133 #define SDMA0_BASE__INST3_SEG0 0
1134 #define SDMA0_BASE__INST3_SEG1 0
1135 #define SDMA0_BASE__INST3_SEG2 0
1136 #define SDMA0_BASE__INST3_SEG3 0
1137 #define SDMA0_BASE__INST3_SEG4 0
1139 #define SDMA0_BASE__INST4_SEG0 0
1140 #define SDMA0_BASE__INST4_SEG1 0
1141 #define SDMA0_BASE__INST4_SEG2 0
1142 #define SDMA0_BASE__INST4_SEG3 0
1143 #define SDMA0_BASE__INST4_SEG4 0
1145 #define SDMA0_BASE__INST5_SEG0 0
1146 #define SDMA0_BASE__INST5_SEG1 0
1147 #define SDMA0_BASE__INST5_SEG2 0
1148 #define SDMA0_BASE__INST5_SEG3 0
1149 #define SDMA0_BASE__INST5_SEG4 0
1151 #define SDMA0_BASE__INST6_SEG0 0
1152 #define SDMA0_BASE__INST6_SEG1 0
1153 #define SDMA0_BASE__INST6_SEG2 0
1154 #define SDMA0_BASE__INST6_SEG3 0
1155 #define SDMA0_BASE__INST6_SEG4 0
1157 #define SMUIO_BASE__INST0_SEG0 0x00016800
1158 #define SMUIO_BASE__INST0_SEG1 0x00016A00
1159 #define SMUIO_BASE__INST0_SEG2 0x02401000
1160 #define SMUIO_BASE__INST0_SEG3 0x00440000
1161 #define SMUIO_BASE__INST0_SEG4 0
1163 #define SMUIO_BASE__INST1_SEG0 0
1164 #define SMUIO_BASE__INST1_SEG1 0
1165 #define SMUIO_BASE__INST1_SEG2 0
1166 #define SMUIO_BASE__INST1_SEG3 0
1167 #define SMUIO_BASE__INST1_SEG4 0
1169 #define SMUIO_BASE__INST2_SEG0 0
1170 #define SMUIO_BASE__INST2_SEG1 0
1171 #define SMUIO_BASE__INST2_SEG2 0
1172 #define SMUIO_BASE__INST2_SEG3 0
1173 #define SMUIO_BASE__INST2_SEG4 0
1175 #define SMUIO_BASE__INST3_SEG0 0
1176 #define SMUIO_BASE__INST3_SEG1 0
1177 #define SMUIO_BASE__INST3_SEG2 0
1178 #define SMUIO_BASE__INST3_SEG3 0
1179 #define SMUIO_BASE__INST3_SEG4 0
1181 #define SMUIO_BASE__INST4_SEG0 0
1182 #define SMUIO_BASE__INST4_SEG1 0
1183 #define SMUIO_BASE__INST4_SEG2 0
1184 #define SMUIO_BASE__INST4_SEG3 0
1185 #define SMUIO_BASE__INST4_SEG4 0
1187 #define SMUIO_BASE__INST5_SEG0 0
1188 #define SMUIO_BASE__INST5_SEG1 0
1189 #define SMUIO_BASE__INST5_SEG2 0
1190 #define SMUIO_BASE__INST5_SEG3 0
1191 #define SMUIO_BASE__INST5_SEG4 0
1193 #define SMUIO_BASE__INST6_SEG0 0
1194 #define SMUIO_BASE__INST6_SEG1 0
1195 #define SMUIO_BASE__INST6_SEG2 0
1196 #define SMUIO_BASE__INST6_SEG3 0
1197 #define SMUIO_BASE__INST6_SEG4 0
1199 #define THM_BASE__INST0_SEG0 0x00016600
1200 #define THM_BASE__INST0_SEG1 0x02400C00
1201 #define THM_BASE__INST0_SEG2 0
1202 #define THM_BASE__INST0_SEG3 0
1203 #define THM_BASE__INST0_SEG4 0
1205 #define THM_BASE__INST1_SEG0 0
1206 #define THM_BASE__INST1_SEG1 0
1207 #define THM_BASE__INST1_SEG2 0
1208 #define THM_BASE__INST1_SEG3 0
1209 #define THM_BASE__INST1_SEG4 0
1211 #define THM_BASE__INST2_SEG0 0
1212 #define THM_BASE__INST2_SEG1 0
1213 #define THM_BASE__INST2_SEG2 0
1214 #define THM_BASE__INST2_SEG3 0
1215 #define THM_BASE__INST2_SEG4 0
1217 #define THM_BASE__INST3_SEG0 0
1218 #define THM_BASE__INST3_SEG1 0
1219 #define THM_BASE__INST3_SEG2 0
1220 #define THM_BASE__INST3_SEG3 0
1221 #define THM_BASE__INST3_SEG4 0
1223 #define THM_BASE__INST4_SEG0 0
1224 #define THM_BASE__INST4_SEG1 0
1225 #define THM_BASE__INST4_SEG2 0
1226 #define THM_BASE__INST4_SEG3 0
1227 #define THM_BASE__INST4_SEG4 0
1229 #define THM_BASE__INST5_SEG0 0
1230 #define THM_BASE__INST5_SEG1 0
1231 #define THM_BASE__INST5_SEG2 0
1232 #define THM_BASE__INST5_SEG3 0
1233 #define THM_BASE__INST5_SEG4 0
1235 #define THM_BASE__INST6_SEG0 0
1236 #define THM_BASE__INST6_SEG1 0
1237 #define THM_BASE__INST6_SEG2 0
1238 #define THM_BASE__INST6_SEG3 0
1239 #define THM_BASE__INST6_SEG4 0
1241 #define UMC_BASE__INST0_SEG0 0x00014000
1242 #define UMC_BASE__INST0_SEG1 0x02425800
1243 #define UMC_BASE__INST0_SEG2 0
1244 #define UMC_BASE__INST0_SEG3 0
1245 #define UMC_BASE__INST0_SEG4 0
1247 #define UMC_BASE__INST1_SEG0 0x00054000
1248 #define UMC_BASE__INST1_SEG1 0x02425C00
1249 #define UMC_BASE__INST1_SEG2 0
1250 #define UMC_BASE__INST1_SEG3 0
1251 #define UMC_BASE__INST1_SEG4 0
1253 #define UMC_BASE__INST2_SEG0 0
1254 #define UMC_BASE__INST2_SEG1 0
1255 #define UMC_BASE__INST2_SEG2 0
1256 #define UMC_BASE__INST2_SEG3 0
1257 #define UMC_BASE__INST2_SEG4 0
1259 #define UMC_BASE__INST3_SEG0 0
1260 #define UMC_BASE__INST3_SEG1 0
1261 #define UMC_BASE__INST3_SEG2 0
1262 #define UMC_BASE__INST3_SEG3 0
1263 #define UMC_BASE__INST3_SEG4 0
1265 #define UMC_BASE__INST4_SEG0 0
1266 #define UMC_BASE__INST4_SEG1 0
1267 #define UMC_BASE__INST4_SEG2 0
1268 #define UMC_BASE__INST4_SEG3 0
1269 #define UMC_BASE__INST4_SEG4 0
1271 #define UMC_BASE__INST5_SEG0 0
1272 #define UMC_BASE__INST5_SEG1 0
1273 #define UMC_BASE__INST5_SEG2 0
1274 #define UMC_BASE__INST5_SEG3 0
1275 #define UMC_BASE__INST5_SEG4 0
1277 #define UMC_BASE__INST6_SEG0 0
1278 #define UMC_BASE__INST6_SEG1 0
1279 #define UMC_BASE__INST6_SEG2 0
1280 #define UMC_BASE__INST6_SEG3 0
1281 #define UMC_BASE__INST6_SEG4 0
1283 #define USB0_BASE__INST0_SEG0 0x0242A800
1284 #define USB0_BASE__INST0_SEG1 0x05B00000
1285 #define USB0_BASE__INST0_SEG2 0
1286 #define USB0_BASE__INST0_SEG3 0
1287 #define USB0_BASE__INST0_SEG4 0
1289 #define USB0_BASE__INST1_SEG0 0
1290 #define USB0_BASE__INST1_SEG1 0
1291 #define USB0_BASE__INST1_SEG2 0
1292 #define USB0_BASE__INST1_SEG3 0
1293 #define USB0_BASE__INST1_SEG4 0
1295 #define USB0_BASE__INST2_SEG0 0
1296 #define USB0_BASE__INST2_SEG1 0
1297 #define USB0_BASE__INST2_SEG2 0
1298 #define USB0_BASE__INST2_SEG3 0
1299 #define USB0_BASE__INST2_SEG4 0
1301 #define USB0_BASE__INST3_SEG0 0
1302 #define USB0_BASE__INST3_SEG1 0
1303 #define USB0_BASE__INST3_SEG2 0
1304 #define USB0_BASE__INST3_SEG3 0
1305 #define USB0_BASE__INST3_SEG4 0
1307 #define USB0_BASE__INST4_SEG0 0
1308 #define USB0_BASE__INST4_SEG1 0
1309 #define USB0_BASE__INST4_SEG2 0
1310 #define USB0_BASE__INST4_SEG3 0
1311 #define USB0_BASE__INST4_SEG4 0
1313 #define USB0_BASE__INST5_SEG0 0
1314 #define USB0_BASE__INST5_SEG1 0
1315 #define USB0_BASE__INST5_SEG2 0
1316 #define USB0_BASE__INST5_SEG3 0
1317 #define USB0_BASE__INST5_SEG4 0
1319 #define USB0_BASE__INST6_SEG0 0
1320 #define USB0_BASE__INST6_SEG1 0
1321 #define USB0_BASE__INST6_SEG2 0
1322 #define USB0_BASE__INST6_SEG3 0
1323 #define USB0_BASE__INST6_SEG4 0
1325 #define UVD0_BASE__INST0_SEG0 0x00007800
1326 #define UVD0_BASE__INST0_SEG1 0x00007E00
1327 #define UVD0_BASE__INST0_SEG2 0x02403000
1328 #define UVD0_BASE__INST0_SEG3 0
1329 #define UVD0_BASE__INST0_SEG4 0
1331 #define UVD0_BASE__INST1_SEG0 0
1332 #define UVD0_BASE__INST1_SEG1 0
1333 #define UVD0_BASE__INST1_SEG2 0
1334 #define UVD0_BASE__INST1_SEG3 0
1335 #define UVD0_BASE__INST1_SEG4 0
1337 #define UVD0_BASE__INST2_SEG0 0
1338 #define UVD0_BASE__INST2_SEG1 0
1339 #define UVD0_BASE__INST2_SEG2 0
1340 #define UVD0_BASE__INST2_SEG3 0
1341 #define UVD0_BASE__INST2_SEG4 0
1343 #define UVD0_BASE__INST3_SEG0 0
1344 #define UVD0_BASE__INST3_SEG1 0
1345 #define UVD0_BASE__INST3_SEG2 0
1346 #define UVD0_BASE__INST3_SEG3 0
1347 #define UVD0_BASE__INST3_SEG4 0
1349 #define UVD0_BASE__INST4_SEG0 0
1350 #define UVD0_BASE__INST4_SEG1 0
1351 #define UVD0_BASE__INST4_SEG2 0
1352 #define UVD0_BASE__INST4_SEG3 0
1353 #define UVD0_BASE__INST4_SEG4 0
1355 #define UVD0_BASE__INST5_SEG0 0
1356 #define UVD0_BASE__INST5_SEG1 0
1357 #define UVD0_BASE__INST5_SEG2 0
1358 #define UVD0_BASE__INST5_SEG3 0
1359 #define UVD0_BASE__INST5_SEG4 0
1361 #define UVD0_BASE__INST6_SEG0 0
1362 #define UVD0_BASE__INST6_SEG1 0
1363 #define UVD0_BASE__INST6_SEG2 0
1364 #define UVD0_BASE__INST6_SEG3 0
1365 #define UVD0_BASE__INST6_SEG4 0
1367 #define DCN_BASE__INST0_SEG0 0x00000012
1368 #define DCN_BASE__INST0_SEG1 0x000000C0
1369 #define DCN_BASE__INST0_SEG2 0x000034C0
1370 #define DCN_BASE__INST0_SEG3 0
1371 #define DCN_BASE__INST0_SEG4 0
1373 #define DCN_BASE__INST1_SEG0 0
1374 #define DCN_BASE__INST1_SEG1 0
1375 #define DCN_BASE__INST1_SEG2 0
1376 #define DCN_BASE__INST1_SEG3 0
1377 #define DCN_BASE__INST1_SEG4 0
1379 #define DCN_BASE__INST2_SEG0 0
1380 #define DCN_BASE__INST2_SEG1 0
1381 #define DCN_BASE__INST2_SEG2 0
1382 #define DCN_BASE__INST2_SEG3 0
1383 #define DCN_BASE__INST2_SEG4 0
1385 #define DCN_BASE__INST3_SEG0 0
1386 #define DCN_BASE__INST3_SEG1 0
1387 #define DCN_BASE__INST3_SEG2 0
1388 #define DCN_BASE__INST3_SEG3 0
1389 #define DCN_BASE__INST3_SEG4 0
1391 #define DCN_BASE__INST4_SEG0 0
1392 #define DCN_BASE__INST4_SEG1 0
1393 #define DCN_BASE__INST4_SEG2 0
1394 #define DCN_BASE__INST4_SEG3 0
1395 #define DCN_BASE__INST4_SEG4 0