Lines Matching +full:tras +full:- +full:max +full:- +full:ns
6 * Description header file of general definitions for OS and pre-OS video drivers
31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the chan…
115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/
116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication
202 #define BIOS_VERSION_PREFIX "ATOMBIOSBK-AMD"
245 …tom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
604 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
605 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
636 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
637 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
688 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip
689 …eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without A…
715 /* gpio_id pre-define id for multiple usage */
726 …/* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; …
728 /* Thermal interrupt output->system thermal chip GPIO pin */
736 … included in the structure is calcualted by using the (whole structure size - the header size)/siz…
742 * VBIOS/PRE-OS always reserve a FB region at the top of frame buffer. driver should not write
745 * if (pre-NV1X) atom data table firmwareInfoTable version < 3.3:
749 * update start_address_in_kb = total_mem_size_in_kb - used_by_firmware_in_kb;
753 * driver reservation start address = (start_address_in_kb - used_by_driver_in_kb)
756 * used_by_firmware_in_kb = total reserved size for pf-vf info exchange and
761 * driver reservation start address = (total_mem_size_in_kb - used_by_driver_in_kb)
767 * start_address_in_kb = total_mem_size_in_kb - used_by_firmware_in_kb;
772 * driver reservation start address = start_address_in_kb - used_by_driver_in_kb
775 * allocate it reservation any place as long as it does overlap pre-OS FW reservation area
852 …uint32_t connector_max_speed; // connector Max speed attribute, it sets 8100 in Mhz when DP connec…
868 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type.
879 …ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-e…
893 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin
950 …bility on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2…
1041 … in the structure is calculated by using the (whole structure size - the header size- number_of_pa…
1050 // (whole structure size - the header size- number_of_path)/size of atom_display_object_path
1191 …orst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.…
1192 …uint32_t max_sr_exit_lat; // Worst case memory self refresh exit time, units of 100ns of ns (0.1u…
1193 … Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us)
1262 …orst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.…
1264 // Worst case memory self refresh exit time, units of 100ns of ns (0.1us)
1266 …// Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1…
1308 EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 = (0x03 << 2) //Parade DP->HDMI recoverter chip
1357 struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max
1358 struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max
1661 …char optionName[29]; //max length of string is 28chars + '\0'. Current design is for …
1732 //memorytype DMI Type 17 offset 12h - Memory Type
1753 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM
2535 …uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple step…
2536 …uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple step…
2618 …uint16_t maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple step…
2619 …uint16_t maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple step…
2678 uint32_t memorychannelenabled; // for dram use only, max 32 channels enabled bit mask.
2706 …uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple step…
2707 …uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple step…
2785 uint8_t LedPin3; // GPIO number for LedPin[3] - PCIE GEN Speed
2786 uint8_t LedPin4; // GPIO number for LedPin[4] - PMFW Error Status
2824 …uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when enter…
2901 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask.
3222 …uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 m…
3345 …uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 m…
3414 uint8_t tRAS; member
3543 …VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage…
3544 …VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> ato…
3545 …VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_vol…
3546 …VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_vo…
3558 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data
4061 …PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disab…
4062 …PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set…
4063 …PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set…
4064 …PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set…
4105 …DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disab…
4106 …DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set…
4107 …DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set…
4108 …DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set…
4314 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
4354 …uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "D…
4359 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,