Lines Matching +full:dc +full:- +full:to +full:- +full:dc
2 * Copyright 2012-2023 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
108 // for example, 1080p -> 8K is 4.0, or 4000 raw value
116 // for example, 8K -> 1080p is 0.25, or 250 raw value
128 * DOC: color-management-caps
132 * Modules/color calculates various color operations which are translated to
133 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
136 * decide mapping to HW block based on logical capabilities.
140 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
156 * struct dpp_color_caps - color pipeline capabilities for display pipe and
161 * just plain 256-entry lookup
170 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes
171 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT
172 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
192 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and
201 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
213 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks
245 * max video plane width that can be safely assumed to be always
283 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height
293 /* Conservative limit for DCC cases which require ODM4:1 to support*/
327 //These bitfields to be used starting with DCN 3.0
369 * going to be done during the call.
373 * ISR safe on windows. Currently fast update will only be used to flip surface
377 * re-programming however do not affect bandwidth consumption or clock
379 * that do not require us to run bw_calcs happen. These are in/out transfer func
381 * This update can be done at ISR, but we want to minimize how often this happens.
383 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
386 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
389 * underscan we don't expect to see this call at all.
393 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
395 UPDATE_TYPE_FULL, /* may need to shuffle resources */
399 struct dc;
404 bool (*get_dcc_compression_cap)(const struct dc *dc,
407 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context);
420 /* Structure to hold configuration flags set by dm at dc creation. */
510 INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams
511 INGAME_FAMS_DISABLE, // disable in-game fams
512 INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display
513 …INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR s…
517 * enum pipe_split_policy - Pipe split strategy supported by DCN
519 * This enum is used to define the pipe split policy supported by DCN. By
520 * default, DC favors MPC_SPLIT_DYNAMIC.
524 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the
525 * pipe in order to bring the best trade-off between performance and
531 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not
537 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to
539 * user connects to a second display, DC will avoid pipe split.
557 DCN_PWR_STATE_UNKNOWN = -1,
572 * struct dc_clocks - DC pipe clocks
607 * DC has a mechanism that leverage the variable refresh rate to switch
608 * memory clock in cases that we have a large latency to achieve the
609 * memory clock change and a short vblank window. DC has some
610 * requirements to enable this feature, and this field describes if the
643 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
644 dm_get_timestamp(dc->ctx) : 0
647 if (dc->debug.bw_val_profile.enable) \
648 dc->debug.bw_val_profile.total_count++
651 if (dc->debug.bw_val_profile.enable) { \
653 voltage_level_tick = dm_get_timestamp(dc->ctx); \
654 dc->debug.bw_val_profile.skip_ ## status ## _count++; \
658 if (dc->debug.bw_val_profile.enable) \
659 voltage_level_tick = dm_get_timestamp(dc->ctx)
662 if (dc->debug.bw_val_profile.enable) \
663 watermark_tick = dm_get_timestamp(dc->ctx)
666 if (dc->debug.bw_val_profile.enable) { \
667 end_tick = dm_get_timestamp(dc->ctx); \
668 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
669 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
671 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
672 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
775 * 15-2: reserved
776 * 31-16: timeout in ms
849 * struct dc_debug_options - DC debug struct
851 * This struct provides a simple mechanism for developers to change some
853 * This can be very handy to narrow down whether some specific feature is
946 /* This forces a hard min on the DCFCLK requested to SMU/PP
960 /* TODO - remove once tested */
1067 /* Generic structure that can be used to query properties of DC. More fields
1130 struct dc *dc_create(const struct dc_init_data *init_params);
1131 void dc_hardware_init(struct dc *dc);
1133 int dc_get_vmid_use_vector(struct dc *dc);
1134 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
1136 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
1137 void dc_init_callbacks(struct dc *dc,
1139 void dc_deinit_callbacks(struct dc *dc);
1140 void dc_destroy(struct dc **dc);
1214 uint32_t rmu_mux_num:3; /*index of mux to use*/
1335 /* private to DC core */
1344 /* private to dc_surface.c */
1385 /* used to temporarily backup plane states of a stream during
1386 * dc update. The reason is that plane states are overwritten
1387 * with surface updates in dc update. Once they are overwritten
1388 * current state is no longer valid. We want to temporarily
1390 * a valid current state during dc update.
1397 struct dc { struct
1431 /* Require to optimize clocks and bandwidth for added/removed planes */
1437 /* Require to maintain clocks and bandwidth for UEFI enabled HW */
1463 struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack
1511 * Color Transformations for pre-blend MCM (Shaper, 3DLUT, 1DLUT)
1537 struct dc *dc);
1542 * struct dc_validation_set - Struct to store surface/stream associations for validation
1561 bool dc_validate_boot_timing(const struct dc *dc,
1565 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
1569 enum dc_status dc_validate_with_context(struct dc *dc,
1583 struct dc *dc,
1588 struct dc *dc, bool acquire,
1593 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
1603 * Set up streams and links associated to drive sinks
1610 enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params);
1613 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc,
1618 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
1622 /* The function returns minimum bandwidth required to drive a given timing
1623 * return - minimum required timing bandwidth in kbps.
1632 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
1650 * If there is no link and local sink, this variable should be set to
1651 * false. Otherwise, it should be set to true; usually, the function
1652 * core_link_enable_stream sets this field to true.
1659 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */
1666 * which expects the same link settings to be used every retry on a link loss.
1667 * This flag is used to skip the fallback when link loss occurs during automation.
1696 * For links with fixed mapping to DIG, this is not changed after dc_link
1703 /* Pending/Current test pattern are only used to perform and track
1705 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern,
1706 * to perform specific lane adjust overrides before setting certain
1709 * pending_test_pattern will be invalid or contain a non-PHY test pattern
1711 * set pattern/set lane adjust to transition between override state(s).
1725 /* Private to DC core */
1727 const struct dc *dc; member
1736 * encoder to display endpoint assignments.
1782 …bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered d…
1794 * Use dc_get_caps() to get number of links.
1796 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);
1799 bool dc_get_edp_link_panel_inst(const struct dc *dc,
1803 /* Return an array of link pointers to edp links. */
1804 void dc_get_edp_links(const struct dc *dc,
1808 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,
1815 * to establish a proper connection between TX and RX. So it is always
1816 * recommended to call this function as the first link operation upon HPD event
1819 * to be reset to off for all currently enabled streams to the link. It is DM's
1820 * responsibility to serialize detection and DPMS updates.
1822 * @reason - Indicate which event triggers this detection. dc may customize
1824 * return false - if detection is not fully completed. This could happen when
1826 * completed (detection has been delegated to dm mst manager ie.
1827 * link->connection_type == dc_connection_mst_branch when returning false).
1828 * return true - detection is completed, link has been fully updated with latest
1836 * added to the link. The interface creates a remote sink and associates it with
1840 * @dc_link - link the remote sink will be added to.
1841 * @edid - byte array of EDID raw data.
1842 * @len - size of the edid in byte
1843 * @init_data -
1852 * @link - link the sink should be removed from
1853 * @sink - sink to be removed.
1865 /* determine if there is a sink connected to the link
1867 * @type - dc_connection_single if connected, dc_connection_none otherwise.
1868 * return - false if an unexpected error occurs, true otherwise.
1879 * return - true HPD is asserted (HPD high), false otherwise (HPD low)
1889 * @link - The link the HPD pin is associated with.
1890 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq
1891 * handler once after no HPD change has been detected within dc default HPD
1894 * toggles have stopped. Then HPD event will be queued to irq handler once after
1895 * dc default HPD filtering interval since last HPD event.
1897 * @enable = false - disable hardware HPD filter. HPD event will be queued
1898 * immediately to irq handler after no HPD change has been detected within
1904 * @link_index - index to a link with ddc in i2c mode
1905 * @cmd - i2c command structure
1906 * return - true if success, false otherwise.
1909 struct dc *dc,
1914 * @link_index - index to a link with ddc in i2c mode
1915 * @cmd - i2c command structure
1916 * return - true if success, false otherwise.
1919 struct dc *dc,
1923 /* Attempt to transfer the given aux payload. This function does not perform
1924 * retries or handle error states. The reply is returned in the payload->reply
1926 * transferred,or -1 on a failure.
1933 struct dc *dc,
1941 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD).
1943 * TODO - When defer_handling is true the function will have a different purpose.
1948 * true - Downstream port status changed. DM should call DC to do the
1950 * false - no change in Downstream port status. No further action required
1959 /* handle DP Link loss sequence and try to recover RX link loss with best
1965 * return true - hpd rx irq should be handled.
1966 * return false - it is safe to ignore hpd rx irq event
1971 * @link - link the hpd irq data associated with
1972 * @hpd_irq_dpcd_data - input hpd irq data
1973 * return - true if hpd irq data indicates a link lost
1979 * @link - link where the hpd irq data should be read from
1980 * @irq_data - output hpd irq data
1981 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data
1989 * function when it is resuming from S3 power state to previously connected links.
1991 * TODO - in the future we should consider to expand link resume interface to
1992 * support clearing previous rx states. So we don't have to rely on dm to call
1999 * NOTE: this should only be called if DM chooses not to call dc_link_detect but
2000 * still wants to reset MST topology on an unplug event */
2006 * return - total effective link bandwidth in kbps.
2013 * @dc: pointer to dc of the dm calling this
2014 * @map: a dc link resource snapshot defined internally to dc.
2016 * DM needs to capture a snapshot of current link resource allocation mapping
2021 * is lost after driver is loaded next time. The snapshot is used in order to
2022 * restore link resource to its previous state so user will get consistent
2026 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map);
2029 * @dc: pointer to dc of the dm calling this
2030 * @map: a dc link resource snapshot defined internally to dc.
2032 * DM needs to call this function after initial link detection on boot and
2033 * before first commit streams to restore link resource allocation state
2038 * is lost after driver is loaded next time. The snapshot is used in order to
2039 * restore link resource to its previous state so user will get consistent
2043 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map);
2045 /* TODO: this is not meant to be exposed to DM. Should switch to stream update
2046 * interface i.e stream_update->dsc_config
2050 /* translate a raw link rate data to bandwidth in kbps */
2051 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw);
2054 * @link - current detected link
2055 * @req_bw - requested bandwidth in kbps
2056 * @link_settings - returned most optimal link settings that can fit the
2058 * return - false if link can't support requested bandwidth, true if link
2074 * @link - a link with DP RX connection
2075 * return - if stream is committed to this link with MST signal type, type of
2076 * channel coding format dc will choose.
2084 * @link - a link with DP RX connection
2085 * return - max dp link settings the link can enable.
2093 * @link - a link with DP RX connection
2094 * return - highest encoding format link supports.
2099 * to a link with dp connector signal type.
2100 * @link - a link with dp connector signal type
2101 * return - true if connected, false otherwise
2105 /* Force DP lane settings update to main-link video signal and notify the change
2106 * to DP RX via DPCD. This is a debug interface used for video signal integrity
2110 * @lt_settings - a container structure with desired hw_lane_settings
2112 void dc_link_set_drive_settings(struct dc *dc,
2117 * test or debugging purpose. The test pattern will remain until next un-plug.
2119 * @link - active link with DP signal output enabled.
2120 * @test_pattern - desired test pattern to output.
2121 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern.
2122 * @test_pattern_color_space - for video test pattern choose a desired color
2124 * @p_link_settings - For PHY pattern choose a desired link settings
2125 * @p_custom_pattern - some test pattern will require a custom input to
2126 * customize some pattern details. Otherwise keep it to NULL.
2127 * @cust_pattern_size - size of the custom pattern input.
2138 /* Force DP link settings to always use a specific value until reboot to a
2140 * switch to desired link settings immediately. This is a debug interface to
2143 void dc_link_set_preferred_link_settings(struct dc *dc,
2147 /* Force DP link to customize a specific link training behavior by overriding to
2148 * standard DP specs defined protocol. This is a debug interface to trouble shoot
2152 * @link_settings - if not NULL, force preferred link settings to the link.
2153 * @lt_override - a set of override pointers. If any pointer is none NULL, dc
2155 * passed in, dc resets previous overrides.
2159 void dc_link_set_preferred_training_settings(struct dc *dc,
2165 /* return - true if FEC is supported with connected DP RX, false otherwise */
2168 /* query FEC enablement policy to determine if FEC will be enabled by dc during
2170 * return - true if FEC should be enabled, false otherwise.
2180 /* Force DP RX to update its power state.
2181 * NOTE: this interface doesn't update dp main-link. Calling this function will
2182 * cause DP TX main-link and DP RX power states out of sync. DM has to restore
2185 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power
2190 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite
2191 * current value read from extended receiver cap from 02200h - 0220Fh.
2193 * field, this interface is a workaround to revert link back to use base caps.
2209 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */
2233 * Communicate with DMUB to allow or disallow Panel Replay on the specified link:
2235 * @link: pointer to the dc_link struct instance
2237 * @wait: state transition need to wait the active set completed.
2239 * @power_opts: set power optimazation parameters to DMUB.
2254 /* Determine if dp trace has been initialized to reflect upto date result *
2255 * return - true if trace is initialized and has valid data. False dp trace
2260 /* Query a dp trace flag to indicate if the current dp trace data has been
2266 /* Set dp trace flag to indicate whether DM has already logged the current dp
2267 * trace data. DM can set is_logged to true upon logging and check
2268 * dc_dp_trace_is_logged before logging to avoid logging the same result twice.
2276 * @in_detection - true to get link training end time stamp of last link
2277 * training in detection sequence. false to get link training end time stamp
2283 /* Get how many link training attempts dc has done with latest sequence.
2284 * @in_detection - true to get link training count of last link
2285 * training in detection sequence. false to get link training count of last link
2298 * Send a request from DP-Tx requesting to allocate BW remotely after
2302 * @link: pointer to the dc_link struct instance
2303 * @req_bw: The requested bw in Kbyte to allocated
2313 * @link: pointer to the dc_link struct instance
2324 * Plug => Try to allocate max bw from timing parameters supported by the sink
2325 * Unplug => de-allocate bw
2327 * @link: pointer to the dc_link struct instance
2336 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed
2339 * @dc: pointer to dc struct
2340 * @stream: pointer to all possible streams
2345 bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams,
2348 /* Sink Interfaces - A sink corresponds to a display output device */
2353 // 8 byte port ID -> ELD.PortID
2355 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
2357 // 2 byte product code -> ELD.ProductCode
2401 /* private to DC core */
2407 /* private to dc_sink.c */
2409 // sink structure to be logically cloneable up to (but not including)
2435 struct dc *dc,
2438 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
2439 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
2441 struct dc *dc, uint32_t link_index);
2443 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);
2448 struct dc *dc,
2450 void dc_resume(struct dc *dc);
2452 void dc_power_down_on_boot(struct dc *dc);
2461 bool dc_is_dmcu_initialized(struct dc *dc);
2463 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_…
2464 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
2466 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc,
2472 #define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __fu… argument
2473 #define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__) argument
2475 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name);
2476 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name);
2477 bool dc_dmub_is_ips_idle_state(struct dc *dc);
2479 /* set min and max memory clock to lowest and highest DPM level, respectively */
2480 void dc_unlock_memory_clock_frequency(struct dc *dc);
2482 /* set min memory clock to the min required for current mode, max to maxDPM */
2483 void dc_lock_memory_clock_frequency(struct dc *dc);
2485 /* set soft max for memclk, to be used for AC/DC switching clock limitations */
2486 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
2489 void dc_hardware_release(struct dc *dc);
2492 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc);
2494 bool dc_set_psr_allow_active(struct dc *dc, bool enable);
2496 bool dc_set_replay_allow_active(struct dc *dc, bool active);
2498 bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips);
2500 void dc_z10_restore(const struct dc *dc);
2501 void dc_z10_save_init(struct dc *dc);
2503 bool dc_is_dmub_outbox_supported(struct dc *dc);
2504 bool dc_enable_dmub_notifications(struct dc *dc);
2507 struct dc *dc,
2511 void dc_enable_dmub_outbox(struct dc *dc);
2513 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
2517 /* Get dc link index from dpia port index */
2518 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
2521 bool dc_process_dmub_set_config_async(struct dc *dc,
2526 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
2531 void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tp…
2533 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,
2536 void dc_print_dmub_diagnostic_data(const struct dc *dc);
2538 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties);
2550 void dc_disable_accelerated_mode(struct dc *dc);