Lines Matching defs:dc_debug_options
856 struct dc_debug_options { struct
857 bool native422_support;
858 bool disable_dsc;
859 enum visual_confirm visual_confirm;
860 int visual_confirm_rect_height;
862 bool sanity_checks;
863 bool max_disp_clk;
864 bool surface_trace;
865 bool timing_trace;
866 bool clock_trace;
867 bool validation_trace;
868 bool bandwidth_calcs_trace;
869 int max_downscale_src_width;
872 bool disable_stutter;
873 bool use_max_lb;
874 enum dcc_option disable_dcc;
880 enum pipe_split_policy pipe_split_policy;
881 bool force_single_disp_pipe_split;
882 bool voltage_align_fclk;
883 bool disable_min_fclk;
885 bool disable_dfs_bypass;
886 bool disable_dpp_power_gate;
887 bool disable_hubp_power_gate;
888 bool disable_dsc_power_gate;
889 bool disable_optc_power_gate;
890 bool disable_hpo_power_gate;
891 int dsc_min_slice_height_override;
892 int dsc_bpp_increment_div;
893 bool disable_pplib_wm_range;
894 enum wm_report_mode pplib_wm_report_mode;
895 unsigned int min_disp_clk_khz;
896 unsigned int min_dpp_clk_khz;
897 unsigned int min_dram_clk_khz;
898 int sr_exit_time_dpm0_ns;
899 int sr_enter_plus_exit_time_dpm0_ns;
900 int sr_exit_time_ns;
901 int sr_enter_plus_exit_time_ns;
902 int sr_exit_z8_time_ns;
903 int sr_enter_plus_exit_z8_time_ns;
904 int urgent_latency_ns;
905 uint32_t underflow_assert_delay_us;
906 int percent_of_ideal_drambw;
907 int dram_clock_change_latency_ns;
908 bool optimized_watermark;
909 int always_scale;
910 bool disable_pplib_clock_request;
911 bool disable_clock_gate;
912 bool disable_mem_low_power;
913 bool pstate_enabled;
914 bool disable_dmcu;
915 bool force_abm_enable;
916 bool disable_stereo_support;
917 bool vsr_support;
918 bool performance_trace;
919 bool az_endpoint_mute_only;
920 bool always_use_regamma;
921 bool recovery_enabled;
922 bool avoid_vbios_exec_table;
923 bool scl_reset_length10;
924 bool hdmi20_disable;
925 bool skip_detection_link_training;
926 uint32_t edid_read_retry_times;
927 unsigned int force_odm_combine; //bit vector based on otg inst
928 unsigned int seamless_boot_odm_combine;
929 unsigned int force_odm_combine_4to1; //bit vector based on otg inst
930 int minimum_z8_residency_time;
931 int minimum_z10_residency_time;
932 bool disable_z9_mpc;
933 unsigned int force_fclk_khz;
934 bool enable_tri_buf;
935 bool ips_disallow_entry;
936 bool dmub_offload_enabled;
937 bool dmcub_emulation;
938 bool disable_idle_power_optimizations;
939 unsigned int mall_size_override;
940 unsigned int mall_additional_timer_percent;
941 bool mall_error_as_fatal;
942 bool dmub_command_table; /* for testing only */
943 struct dc_bw_validation_profile bw_val_profile;
944 bool disable_fec;
945 bool disable_48mhz_pwrdwn;
949 unsigned int force_min_dcfclk_mhz;
950 int dwb_fi_phase;
951 bool disable_timing_sync;
952 bool cm_in_bypass;
953 int force_clock_mode;/*every mode change.*/
955 bool disable_dram_clock_change_vactive_support;
956 bool validate_dml_output;
957 bool enable_dmcub_surface_flip;
958 bool usbc_combo_phy_reset_wa;
959 bool enable_dram_clock_change_one_display_vactive;
961 bool legacy_dp2_lt;
962 bool set_mst_en_for_sst;
963 bool disable_uhbr;
964 bool force_dp2_lt_fallback_method;
965 bool ignore_cable_id;
966 union mem_low_power_enable_options enable_mem_low_power;
967 union root_clock_optimization_options root_clock_optimization;
968 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating;
969 bool hpo_optimization;
970 bool force_vblank_alignment;
973 bool enable_dmub_aux_for_legacy_ddc;
974 bool disable_fams;
975 enum in_game_fams_config disable_fams_gaming;
977 uint8_t fec_enable_delay_in100us;
978 bool enable_driver_sequence_debug;
979 enum det_size crb_alloc_policy;
980 int crb_alloc_policy_min_disp_count;
981 bool disable_z10;
982 bool enable_z9_disable_interface;
983 bool psr_skip_crtc_disable;
984 uint32_t ips_skip_crtc_disable_mask;
985 union dpia_debug_options dpia_debug;
986 bool disable_fixed_vs_aux_timeout_wa;
987 uint32_t fixed_vs_aux_delay_config_wa;
988 bool force_disable_subvp;
989 bool force_subvp_mclk_switch;
990 bool allow_sw_cursor_fallback;
991 unsigned int force_subvp_num_ways;
992 unsigned int force_mall_ss_num_ways;
993 bool alloc_extra_way_for_cursor;
994 uint32_t subvp_extra_lines;
995 bool force_usr_allow;
997 bool disable_dtb_ref_clk_switch;
998 bool extended_blank_optimization;
999 union aux_wake_wa_options aux_wake_wa;
1000 uint32_t mst_start_top_delay;
1001 uint8_t psr_power_use_phy_fsm;
1002 enum dml_hostvm_override_opts dml_hostvm_override;
1003 bool dml_disallow_alternate_prefetch_modes;
1004 bool use_legacy_soc_bb_mechanism;
1005 bool exit_idle_opt_for_cursor_updates;
1006 bool using_dml2;
1007 bool enable_single_display_2to1_odm_policy;
1008 bool enable_double_buffered_dsc_pg_support;
1009 bool enable_dp_dig_pixel_rate_div_policy;
1010 bool using_dml21;
1011 enum lttpr_mode lttpr_mode_override;
1012 unsigned int dsc_delay_factor_wa_x1000;
1013 unsigned int min_prefetch_in_strobe_ns;
1014 bool disable_unbounded_requesting;
1015 bool dig_fifo_off_in_blank;
1016 bool override_dispclk_programming;
1017 bool otg_crc_db;
1018 bool disallow_dispclk_dppclk_ds;
1019 bool disable_fpo_optimizations;
1020 bool support_eDP1_5;
1021 uint32_t fpo_vactive_margin_us;
1022 bool disable_fpo_vactive;
1023 bool disable_boot_optimizations;
1024 bool override_odm_optimization;
1025 bool minimize_dispclk_using_odm;
1026 bool disable_subvp_high_refresh;
1027 bool disable_dp_plus_plus_wa;
1028 uint32_t fpo_vactive_min_active_margin_us;
1029 uint32_t fpo_vactive_max_blank_us;
1030 bool enable_hpo_pg_support;
1031 bool enable_legacy_fast_update;
1032 bool disable_dc_mode_overwrite;
1033 bool replay_skip_crtc_disabled;
1034 bool ignore_pg;/*do nothing, let pmfw control it*/
1035 bool psp_disabled_wa;
1036 unsigned int ips2_eval_delay_us;
1037 unsigned int ips2_entry_delay_us;
1038 bool optimize_ips_handshake;
1039 bool disable_dmub_reallow_idle;
1040 bool disable_timeout;
1041 bool disable_extblankadj;
1042 bool enable_idle_reg_checks;
1043 unsigned int static_screen_wait_frames;
1044 uint32_t pwm_freq;
1045 bool force_chroma_subsampling_1tap;
1046 unsigned int dcc_meta_propagation_delay_us;
1047 bool disable_422_left_edge_pixel;
1048 bool dml21_force_pstate_method;
1049 uint32_t dml21_force_pstate_method_values[MAX_PIPES];
1050 uint32_t dml21_disable_pstate_method_mask;
1051 union dmub_fams2_global_feature_config fams2_config;
1052 bool enable_legacy_clock_update;
1053 unsigned int force_cositing;
1054 unsigned int disable_spl;
1055 unsigned int force_easf;
1056 unsigned int force_sharpness;
1057 unsigned int force_sharpness_level;
1058 unsigned int force_lls;
1059 bool notify_dpia_hr_bw;
1060 bool enable_ips_visual_confirm;
1061 unsigned int sharpen_policy;
1062 unsigned int scale_to_sharpness_policy;
1063 bool skip_full_updated_if_possible;