Lines Matching refs:acrtc
264 struct amdgpu_crtc *acrtc = NULL; in dm_vblank_get_counter() local
269 acrtc = adev->mode_info.crtcs[crtc]; in dm_vblank_get_counter()
271 if (!acrtc->dm_irq_params.stream) { in dm_vblank_get_counter()
277 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); in dm_vblank_get_counter()
284 struct amdgpu_crtc *acrtc = NULL; in dm_crtc_get_scanoutpos() local
290 acrtc = adev->mode_info.crtcs[crtc]; in dm_crtc_get_scanoutpos()
292 if (!acrtc->dm_irq_params.stream) { in dm_crtc_get_scanoutpos()
305 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, in dm_crtc_get_scanoutpos()
534 struct amdgpu_crtc *acrtc; in dm_vupdate_high_irq() local
541 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); in dm_vupdate_high_irq()
543 if (acrtc) { in dm_vupdate_high_irq()
544 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); in dm_vupdate_high_irq()
545 drm_dev = acrtc->base.dev; in dm_vupdate_high_irq()
546 vblank = drm_crtc_vblank_crtc(&acrtc->base); in dm_vupdate_high_irq()
551 trace_amdgpu_refresh_rate_track(acrtc->base.index, in dm_vupdate_high_irq()
558 "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, in dm_vupdate_high_irq()
568 amdgpu_dm_crtc_handle_vblank(acrtc); in dm_vupdate_high_irq()
571 if (acrtc->dm_irq_params.stream && in dm_vupdate_high_irq()
576 acrtc->dm_irq_params.stream, in dm_vupdate_high_irq()
577 &acrtc->dm_irq_params.vrr_params); in dm_vupdate_high_irq()
581 acrtc->dm_irq_params.stream, in dm_vupdate_high_irq()
582 &acrtc->dm_irq_params.vrr_params.adjust); in dm_vupdate_high_irq()
601 struct amdgpu_crtc *acrtc; in dm_crtc_high_irq() local
605 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); in dm_crtc_high_irq()
606 if (!acrtc) in dm_crtc_high_irq()
609 if (acrtc->wb_conn) { in dm_crtc_high_irq()
610 spin_lock_irqsave(&acrtc->wb_conn->job_lock, flags); in dm_crtc_high_irq()
612 if (acrtc->wb_pending) { in dm_crtc_high_irq()
613 job = list_first_entry_or_null(&acrtc->wb_conn->job_queue, in dm_crtc_high_irq()
616 acrtc->wb_pending = false; in dm_crtc_high_irq()
617 spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags); in dm_crtc_high_irq()
621 struct dc_stream_state *stream = acrtc->dm_irq_params.stream; in dm_crtc_high_irq()
629 drm_writeback_signal_completion(acrtc->wb_conn, 0); in dm_crtc_high_irq()
631 acrtc->dm_irq_params.stream, 0); in dm_crtc_high_irq()
634 spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags); in dm_crtc_high_irq()
637 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); in dm_crtc_high_irq()
640 "crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id, in dm_crtc_high_irq()
641 vrr_active, acrtc->dm_irq_params.active_planes); in dm_crtc_high_irq()
650 amdgpu_dm_crtc_handle_vblank(acrtc); in dm_crtc_high_irq()
656 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); in dm_crtc_high_irq()
664 if (acrtc->dm_irq_params.stream && in dm_crtc_high_irq()
665 acrtc->dm_irq_params.vrr_params.supported && in dm_crtc_high_irq()
666 acrtc->dm_irq_params.freesync_config.state == in dm_crtc_high_irq()
669 acrtc->dm_irq_params.stream, in dm_crtc_high_irq()
670 &acrtc->dm_irq_params.vrr_params); in dm_crtc_high_irq()
672 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream, in dm_crtc_high_irq()
673 &acrtc->dm_irq_params.vrr_params.adjust); in dm_crtc_high_irq()
687 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED && in dm_crtc_high_irq()
688 acrtc->dm_irq_params.active_planes == 0) { in dm_crtc_high_irq()
689 if (acrtc->event) { in dm_crtc_high_irq()
690 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event); in dm_crtc_high_irq()
691 acrtc->event = NULL; in dm_crtc_high_irq()
692 drm_crtc_vblank_put(&acrtc->base); in dm_crtc_high_irq()
694 acrtc->pflip_status = AMDGPU_FLIP_NONE; in dm_crtc_high_irq()
712 struct amdgpu_crtc *acrtc; in dm_dcn_vertical_interrupt0_high_irq() local
714 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0); in dm_dcn_vertical_interrupt0_high_irq()
716 if (!acrtc) in dm_dcn_vertical_interrupt0_high_irq()
719 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base); in dm_dcn_vertical_interrupt0_high_irq()
2849 struct amdgpu_crtc *acrtc; in dm_gpureset_toggle_interrupts() local
2854 acrtc = get_crtc_by_otg_inst( in dm_gpureset_toggle_interrupts()
2857 if (acrtc && state->stream_status[i].plane_count != 0) { in dm_gpureset_toggle_interrupts()
2858 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; in dm_gpureset_toggle_interrupts()
2865 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state))) in dm_gpureset_toggle_interrupts()
2866 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true); in dm_gpureset_toggle_interrupts()
2868 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false); in dm_gpureset_toggle_interrupts()
2873 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; in dm_gpureset_toggle_interrupts()
8356 struct amdgpu_crtc *acrtc, in manage_dm_interrupts() argument
8368 acrtc->crtc_id); in manage_dm_interrupts()
8392 drm_crtc_vblank_on_config(&acrtc->base, in manage_dm_interrupts()
8416 drm_crtc_vblank_off(&acrtc->base); in manage_dm_interrupts()
8421 struct amdgpu_crtc *acrtc) in dm_update_pflip_irq_state() argument
8424 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); in dm_update_pflip_irq_state()
8572 struct amdgpu_crtc *acrtc, in remove_stream() argument
8577 acrtc->otg_inst = -1; in remove_stream()
8578 acrtc->enabled = false; in remove_stream()
8581 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) in prepare_flip_isr() argument
8584 assert_spin_locked(&acrtc->base.dev->event_lock); in prepare_flip_isr()
8585 WARN_ON(acrtc->event); in prepare_flip_isr()
8587 acrtc->event = acrtc->base.state->event; in prepare_flip_isr()
8590 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; in prepare_flip_isr()
8593 acrtc->base.state->event = NULL; in prepare_flip_isr()
8595 drm_dbg_state(acrtc->base.dev, in prepare_flip_isr()
8597 acrtc->crtc_id); in prepare_flip_isr()
8610 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); in update_freesync_state_on_stream() local
8628 vrr_params = acrtc->dm_irq_params.vrr_params; in update_freesync_state_on_stream()
8680 acrtc->dm_irq_params.vrr_params = vrr_params; in update_freesync_state_on_stream()
8703 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); in update_stream_irq_parameters() local
8717 vrr_params = acrtc->dm_irq_params.vrr_params; in update_stream_irq_parameters()
8748 acrtc->dm_irq_params.freesync_config = config; in update_stream_irq_parameters()
8749 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; in update_stream_irq_parameters()
8750 acrtc->dm_irq_params.vrr_params = vrr_params; in update_stream_irq_parameters()
9440 struct amdgpu_crtc *acrtc; in amdgpu_dm_commit_streams() local
9451 acrtc = to_amdgpu_crtc(dm_old_con_state->base.crtc); in amdgpu_dm_commit_streams()
9452 if (acrtc) in amdgpu_dm_commit_streams()
9453 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); in amdgpu_dm_commit_streams()
9455 if (!acrtc || !acrtc->wb_enabled) in amdgpu_dm_commit_streams()
9461 acrtc->wb_enabled = false; in amdgpu_dm_commit_streams()
9466 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); in amdgpu_dm_commit_streams() local
9473 manage_dm_interrupts(adev, acrtc, NULL); in amdgpu_dm_commit_streams()
9482 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); in amdgpu_dm_commit_streams() local
9489 acrtc->crtc_id, in amdgpu_dm_commit_streams()
9522 acrtc->crtc_id, acrtc); in amdgpu_dm_commit_streams()
9542 acrtc->base.base.id); in amdgpu_dm_commit_streams()
9547 remove_stream(adev, acrtc, dm_old_crtc_state->stream); in amdgpu_dm_commit_streams()
9551 acrtc->enabled = true; in amdgpu_dm_commit_streams()
9552 acrtc->hw_mode = new_crtc_state->mode; in amdgpu_dm_commit_streams()
9559 acrtc->crtc_id, acrtc); in amdgpu_dm_commit_streams()
9562 remove_stream(adev, acrtc, dm_old_crtc_state->stream); in amdgpu_dm_commit_streams()
9588 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); in amdgpu_dm_commit_streams() local
9602 dm_new_crtc_state->stream, acrtc); in amdgpu_dm_commit_streams()
9604 acrtc->otg_inst = status->primary_otg_inst; in amdgpu_dm_commit_streams()
9629 struct amdgpu_crtc *acrtc; in dm_set_writeback() local
9641 acrtc = to_amdgpu_crtc(wb_conn->encoder.crtc); in dm_set_writeback()
9642 if (!acrtc) { in dm_set_writeback()
9674 wb_info->dwb_params.cnv_params.src_width = acrtc->base.mode.crtc_hdisplay; in dm_set_writeback()
9675 wb_info->dwb_params.cnv_params.src_height = acrtc->base.mode.crtc_vdisplay; in dm_set_writeback()
9676 wb_info->dwb_params.dest_width = acrtc->base.mode.crtc_hdisplay; in dm_set_writeback()
9677 wb_info->dwb_params.dest_height = acrtc->base.mode.crtc_vdisplay; in dm_set_writeback()
9716 acrtc->wb_pending = true; in dm_set_writeback()
9717 acrtc->wb_conn = wb_conn; in dm_set_writeback()
9759 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); in amdgpu_dm_atomic_commit_tail() local
9791 if (acrtc) { in amdgpu_dm_atomic_commit_tail()
9792 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); in amdgpu_dm_atomic_commit_tail()
9793 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); in amdgpu_dm_atomic_commit_tail()
9815 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); in amdgpu_dm_atomic_commit_tail() local
9824 if (acrtc) { in amdgpu_dm_atomic_commit_tail()
9825 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); in amdgpu_dm_atomic_commit_tail()
9826 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); in amdgpu_dm_atomic_commit_tail()
9884 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); in amdgpu_dm_atomic_commit_tail() local
9893 if (acrtc) { in amdgpu_dm_atomic_commit_tail()
9894 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); in amdgpu_dm_atomic_commit_tail()
9895 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); in amdgpu_dm_atomic_commit_tail()
9899 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) in amdgpu_dm_atomic_commit_tail()
9978 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); in amdgpu_dm_atomic_commit_tail() local
9994 cur_crc_src = acrtc->dm_irq_params.crc_src; in amdgpu_dm_atomic_commit_tail()
10002 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; in amdgpu_dm_atomic_commit_tail()
10003 manage_dm_interrupts(adev, acrtc, dm_new_crtc_state); in amdgpu_dm_atomic_commit_tail()
10020 acrtc->dm_irq_params.window_param.update_win = true; in amdgpu_dm_atomic_commit_tail()
10026 acrtc->dm_irq_params.window_param.skip_frame_cnt = 2; in amdgpu_dm_atomic_commit_tail()
10053 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); in amdgpu_dm_atomic_commit_tail() local
10061 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); in amdgpu_dm_atomic_commit_tail()
10066 if (acrtc->wb_enabled) in amdgpu_dm_atomic_commit_tail()
10072 acrtc->wb_enabled = true; in amdgpu_dm_atomic_commit_tail()
10385 struct amdgpu_crtc *acrtc = NULL; in dm_update_crtc_state() local
10395 acrtc = to_amdgpu_crtc(crtc); in dm_update_crtc_state()
10433 __func__, acrtc->base.base.id); in dm_update_crtc_state()
10481 acrtc->crtc_id, in dm_update_crtc_state()
11717 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); in amdgpu_dm_atomic_check() local
11720 if (!acrtc || drm_atomic_crtc_needs_modeset( in amdgpu_dm_atomic_check()
11721 drm_atomic_get_new_crtc_state(state, &acrtc->base))) in amdgpu_dm_atomic_check()