66 	uint32_t se_mask[KFD_MAX_NUM_SE] = {0};  in update_cu_mask()
76 	m->compute_static_thread_mgmt_se0 = se_mask[0];  in update_cu_mask()
169 	memset(m, 0, sizeof(struct v9_mqd));  in init_mqd()
171 	m->header = 0xC0310800;  in init_mqd()
173 	m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;  in init_mqd()
174 	m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;  in init_mqd()
175 	m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;  in init_mqd()
176 	m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;  in init_mqd()
177 	m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF;  in init_mqd()
178 	m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF;  in init_mqd()
179 	m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF;  in init_mqd()
180 	m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF;  in init_mqd()
183 			0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;  in init_mqd()
232 	uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);  in load_mqd()
236 					  wptr_shift, 0, mms, 0);  in load_mqd()
249 	pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);  in update_mqd()
262 	pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",  in update_mqd()
272 	 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit  in update_mqd()
273 	 * more than (EOP entry count - 1) so a queue size of 0x800 dwords  in update_mqd()
274 	 * is safe, giving a maximum field value of 0xA.  in update_mqd()
276 	 * Also, do calculation only if EOP is used (size > 0), otherwise  in update_mqd()
281 		min(0xA, order_base_2(q->eop_ring_buffer_size / 4) - 1) : 0;  in update_mqd()
288 	m->cp_hqd_iq_timer = 0;  in update_mqd()
301 		m->cp_hqd_ctx_save_control = 0;  in update_mqd()
305 		update_cu_mask(mm, mqd, minfo, 0);  in update_mqd()
326 	m->queue_doorbell_id0 = 0;  in check_preemption_failed()
328 	return kfd_check_hiq_mqd_doorbell_id(mm->dev, doorbell_id, 0);  in check_preemption_failed()
364 	return 0;  in get_wave_state()
412 	pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",  in restore_mqd()
415 	qp->is_active = 0;  in restore_mqd()
444 	err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, 0);  in destroy_hiq_mqd()
459 	memset(m, 0, sizeof(struct v9_sdma_mqd));  in init_mqd_sdma()
468 #define SDMA_RLC_DUMMY_DEFAULT 0xf
530 	qp->is_active = 0;  in restore_mqd_sdma()
538 	int xcc = 0;  in init_mqd_hiq_v9_4_3()  local
540 	uint64_t xcc_gart_addr = 0;  in init_mqd_hiq_v9_4_3()
542 	memset(&xcc_mqd_mem_obj, 0x0, sizeof(struct kfd_mem_obj));  in init_mqd_hiq_v9_4_3()
544 	for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) {  in init_mqd_hiq_v9_4_3()
545 		kfd_get_hiq_xcc_mqd(mm->dev, &xcc_mqd_mem_obj, xcc);  in init_mqd_hiq_v9_4_3()
556 		if (xcc == 0) {  in init_mqd_hiq_v9_4_3()
557 			/* Set no_update_rptr = 0 in Master XCC */  in init_mqd_hiq_v9_4_3()
572 	int xcc_id, err, inst = 0;  in hiq_load_mqd_kiq_v9_4_3()
582 			pr_debug("Failed to load HIQ MQD for XCC: %d\n", inst);  in hiq_load_mqd_kiq_v9_4_3()
596 	int xcc_id, err, inst = 0;  in destroy_hiq_mqd_v9_4_3()
609 			pr_debug("Destroy HIQ MQD failed for xcc: %d\n", inst);  in destroy_hiq_mqd_v9_4_3()
622 	int inst = 0, xcc_id;  in check_preemption_failed_v9_4_3()
630 		m->queue_doorbell_id0 = 0;  in check_preemption_failed_v9_4_3()
641 	xcc_mqd_mem_obj->gtt_mem = (offset == 0) ?  in get_xcc_mqd()
653 	int xcc = 0;  in init_mqd_v9_4_3()  local
655 	uint64_t xcc_gart_addr = 0;  in init_mqd_v9_4_3()
660 	memset(&xcc_mqd_mem_obj, 0x0, sizeof(struct kfd_mem_obj));  in init_mqd_v9_4_3()
661 	for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) {  in init_mqd_v9_4_3()
662 		get_xcc_mqd(mqd_mem_obj, &xcc_mqd_mem_obj, offset*xcc);  in init_mqd_v9_4_3()
669 		 * Update the CWSR address for each XCC if CWSR is enabled  in init_mqd_v9_4_3()
676 				(xcc * q->ctx_save_restore_area_size);  in init_mqd_v9_4_3()
687 					(local_xcc_start + xcc) %  in init_mqd_v9_4_3()
690 			switch (xcc) {  in init_mqd_v9_4_3()
691 			case 0:  in init_mqd_v9_4_3()
692 				/* Master XCC */  in init_mqd_v9_4_3()
701 			m->compute_current_logic_xcc_id = 0;  in init_mqd_v9_4_3()
702 			m->compute_tg_chunk_size = 0;  in init_mqd_v9_4_3()
706 		if (xcc == 0) {  in init_mqd_v9_4_3()
718 	int xcc = 0;  in update_mqd_v9_4_3()  local
721 	for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) {  in update_mqd_v9_4_3()
722 		m = get_mqd(mqd + size * xcc);  in update_mqd_v9_4_3()
725 		update_cu_mask(mm, m, minfo, xcc);  in update_mqd_v9_4_3()
728 			switch (xcc) {  in update_mqd_v9_4_3()
729 			case 0:  in update_mqd_v9_4_3()
730 				/* Master XCC */  in update_mqd_v9_4_3()
740 			m->compute_current_logic_xcc_id = 0;  in update_mqd_v9_4_3()
741 			m->compute_tg_chunk_size = 0;  in update_mqd_v9_4_3()
752 	int xcc_id, err, inst = 0;  in destroy_mqd_v9_4_3()
766 			pr_debug("Destroy MQD failed for xcc: %d\n", inst);  in destroy_mqd_v9_4_3()
780 	uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);  in load_mqd_v9_4_3()
782 	int xcc_id, err, inst = 0;  in load_mqd_v9_4_3()
790 			(uint32_t __user *)p->write_ptr, wptr_shift, 0, mms,  in load_mqd_v9_4_3()
793 			pr_debug("Load MQD failed for xcc: %d\n", inst);  in load_mqd_v9_4_3()
808 	int xcc, err = 0;  in get_wave_state_v9_4_3()  local
812 	u32 tmp_ctl_stack_used_size = 0, tmp_save_area_used_size = 0;  in get_wave_state_v9_4_3()
814 	for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) {  in get_wave_state_v9_4_3()
815 		xcc_mqd = mqd + mqd_stride_size * xcc;  in get_wave_state_v9_4_3()
817 					q->ctx_save_restore_area_size * xcc);  in get_wave_state_v9_4_3()
827 		 * ctl_stack_used_size and save_area_used_size of XCC 0 when  in get_wave_state_v9_4_3()
829 		 * For multi XCC, user-space would have to look at the header  in get_wave_state_v9_4_3()
833 		if (xcc == 0) {  in get_wave_state_v9_4_3()
848 	return 0;  in debugfs_show_mqd()
855 	return 0;  in debugfs_show_mqd_sdma()