Lines Matching +full:8 +full:m
47 struct v12_compute_mqd *m; in update_cu_mask() local
56 m = get_mqd(mqd); in update_cu_mask()
57 m->compute_static_thread_mgmt_se0 = se_mask[0]; in update_cu_mask()
58 m->compute_static_thread_mgmt_se1 = se_mask[1]; in update_cu_mask()
59 m->compute_static_thread_mgmt_se2 = se_mask[2]; in update_cu_mask()
60 m->compute_static_thread_mgmt_se3 = se_mask[3]; in update_cu_mask()
61 m->compute_static_thread_mgmt_se4 = se_mask[4]; in update_cu_mask()
62 m->compute_static_thread_mgmt_se5 = se_mask[5]; in update_cu_mask()
63 m->compute_static_thread_mgmt_se6 = se_mask[6]; in update_cu_mask()
64 m->compute_static_thread_mgmt_se7 = se_mask[7]; in update_cu_mask()
67 m->compute_static_thread_mgmt_se0, in update_cu_mask()
68 m->compute_static_thread_mgmt_se1, in update_cu_mask()
69 m->compute_static_thread_mgmt_se2, in update_cu_mask()
70 m->compute_static_thread_mgmt_se3, in update_cu_mask()
71 m->compute_static_thread_mgmt_se4, in update_cu_mask()
72 m->compute_static_thread_mgmt_se5, in update_cu_mask()
73 m->compute_static_thread_mgmt_se6, in update_cu_mask()
74 m->compute_static_thread_mgmt_se7); in update_cu_mask()
77 static void set_priority(struct v12_compute_mqd *m, struct queue_properties *q) in set_priority() argument
79 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; in set_priority()
80 m->cp_hqd_queue_priority = q->priority; in set_priority()
103 struct v12_compute_mqd *m; in init_mqd() local
105 m = (struct v12_compute_mqd *) mqd_mem_obj->cpu_ptr; in init_mqd()
108 memset(m, 0, PAGE_SIZE); in init_mqd()
110 m->header = 0xC0310800; in init_mqd()
111 m->compute_pipelinestat_enable = 1; in init_mqd()
112 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; in init_mqd()
113 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; in init_mqd()
114 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; in init_mqd()
115 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; in init_mqd()
116 m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF; in init_mqd()
117 m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF; in init_mqd()
118 m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF; in init_mqd()
119 m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF; in init_mqd()
121 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | in init_mqd()
124 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; in init_mqd()
126 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
127 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
129 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | in init_mqd()
136 m->cp_hqd_hq_status0 = 1 << 14; in init_mqd()
139 m->cp_hqd_hq_status0 |= 1 << 29; in init_mqd()
142 m->cp_hqd_aql_control = in init_mqd()
147 m->cp_hqd_persistent_state |= in init_mqd()
149 m->cp_hqd_ctx_save_base_addr_lo = in init_mqd()
151 m->cp_hqd_ctx_save_base_addr_hi = in init_mqd()
153 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; in init_mqd()
154 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; in init_mqd()
155 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; in init_mqd()
156 m->cp_hqd_wg_state_offset = q->ctl_stack_size; in init_mqd()
159 *mqd = m; in init_mqd()
162 mm->update_mqd(mm, m, q, NULL); in init_mqd()
183 struct v12_compute_mqd *m; in update_mqd() local
185 m = get_mqd(mqd); in update_mqd()
187 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in update_mqd()
188 m->cp_hqd_pq_control |= in update_mqd()
190 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; in update_mqd()
191 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
193 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
194 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
196 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd()
197 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd()
198 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd()
199 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd()
201 m->cp_hqd_pq_doorbell_control = in update_mqd()
205 m->cp_hqd_pq_doorbell_control); in update_mqd()
207 m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT; in update_mqd()
211 * is constrained by per-SE EOP done signal count, which is 8-bit. in update_mqd()
216 m->cp_hqd_eop_control = min(0xA, in update_mqd()
218 m->cp_hqd_eop_base_addr_lo = in update_mqd()
219 lower_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
220 m->cp_hqd_eop_base_addr_hi = in update_mqd()
221 upper_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
223 m->cp_hqd_iq_timer = 0; in update_mqd()
225 m->cp_hqd_vmid = q->vmid; in update_mqd()
229 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
232 m->cp_hqd_pq_doorbell_control |= in update_mqd()
236 m->cp_hqd_ctx_save_control = 0; in update_mqd()
239 set_priority(m, q); in update_mqd()
246 struct v12_compute_mqd *m = (struct v12_compute_mqd *)mqd; in check_preemption_failed() local
248 return kfd_check_hiq_mqd_doorbell_id(mm->dev, m->queue_doorbell_id0, 0); in check_preemption_failed()
257 struct v12_compute_mqd *m; in get_wave_state() local
260 m = get_mqd(mqd); in get_wave_state()
263 * is written forwards. Both starts from m->cp_hqd_cntl_stack_size. in get_wave_state()
264 * Current position is at m->cp_hqd_cntl_stack_offset and in get_wave_state()
265 * m->cp_hqd_wg_state_offset, respectively. in get_wave_state()
267 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - in get_wave_state()
268 m->cp_hqd_cntl_stack_offset; in get_wave_state()
269 *save_area_used_size = m->cp_hqd_wg_state_offset - in get_wave_state()
270 m->cp_hqd_cntl_stack_size; in get_wave_state()
279 header.wave_state_offset = m->cp_hqd_wg_state_offset; in get_wave_state()
280 header.control_stack_offset = m->cp_hqd_cntl_stack_offset; in get_wave_state()
292 struct v12_compute_mqd *m; in init_mqd_hiq() local
296 m = get_mqd(*mqd); in init_mqd_hiq()
298 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
306 struct v12_sdma_mqd *m; in init_mqd_sdma() local
308 m = (struct v12_sdma_mqd *) mqd_mem_obj->cpu_ptr; in init_mqd_sdma()
310 memset(m, 0, sizeof(struct v12_sdma_mqd)); in init_mqd_sdma()
312 *mqd = m; in init_mqd_sdma()
316 mm->update_mqd(mm, m, q, NULL); in init_mqd_sdma()
325 struct v12_sdma_mqd *m; in update_mqd_sdma() local
327 m = get_sdma_mqd(mqd); in update_mqd_sdma()
328 m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) in update_mqd_sdma()
335 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
336 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
337 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
338 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
339 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd_sdma()
340 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd_sdma()
341 m->sdmax_rlcx_doorbell_offset = in update_mqd_sdma()
344 m->sdmax_rlcx_sched_cntl = (amdgpu_sdma_phase_quantum in update_mqd_sdma()
348 m->sdma_engine_id = q->sdma_engine_id; in update_mqd_sdma()
349 m->sdma_queue_id = q->sdma_queue_id; in update_mqd_sdma()
351 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; in update_mqd_sdma()
358 static int debugfs_show_mqd(struct seq_file *m, void *data) in debugfs_show_mqd() argument
360 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, in debugfs_show_mqd()
365 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) in debugfs_show_mqd_sdma() argument
367 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, in debugfs_show_mqd_sdma()