Lines Matching +full:8 +full:m
47 struct v11_compute_mqd *m; in update_cu_mask() local
55 m = get_mqd(mqd); in update_cu_mask()
61 m->compute_static_thread_mgmt_se0 = wa_mask; in update_cu_mask()
62 m->compute_static_thread_mgmt_se1 = wa_mask; in update_cu_mask()
63 m->compute_static_thread_mgmt_se2 = wa_mask; in update_cu_mask()
64 m->compute_static_thread_mgmt_se3 = wa_mask; in update_cu_mask()
65 m->compute_static_thread_mgmt_se4 = wa_mask; in update_cu_mask()
66 m->compute_static_thread_mgmt_se5 = wa_mask; in update_cu_mask()
67 m->compute_static_thread_mgmt_se6 = wa_mask; in update_cu_mask()
68 m->compute_static_thread_mgmt_se7 = wa_mask; in update_cu_mask()
76 m->compute_static_thread_mgmt_se0 = se_mask[0]; in update_cu_mask()
77 m->compute_static_thread_mgmt_se1 = se_mask[1]; in update_cu_mask()
78 m->compute_static_thread_mgmt_se2 = se_mask[2]; in update_cu_mask()
79 m->compute_static_thread_mgmt_se3 = se_mask[3]; in update_cu_mask()
80 m->compute_static_thread_mgmt_se4 = se_mask[4]; in update_cu_mask()
81 m->compute_static_thread_mgmt_se5 = se_mask[5]; in update_cu_mask()
82 m->compute_static_thread_mgmt_se6 = se_mask[6]; in update_cu_mask()
83 m->compute_static_thread_mgmt_se7 = se_mask[7]; in update_cu_mask()
86 m->compute_static_thread_mgmt_se0, in update_cu_mask()
87 m->compute_static_thread_mgmt_se1, in update_cu_mask()
88 m->compute_static_thread_mgmt_se2, in update_cu_mask()
89 m->compute_static_thread_mgmt_se3, in update_cu_mask()
90 m->compute_static_thread_mgmt_se4, in update_cu_mask()
91 m->compute_static_thread_mgmt_se5, in update_cu_mask()
92 m->compute_static_thread_mgmt_se6, in update_cu_mask()
93 m->compute_static_thread_mgmt_se7); in update_cu_mask()
96 static void set_priority(struct v11_compute_mqd *m, struct queue_properties *q) in set_priority() argument
98 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; in set_priority()
99 m->cp_hqd_queue_priority = q->priority; in set_priority()
128 struct v11_compute_mqd *m; in init_mqd() local
132 m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr; in init_mqd()
140 memset(m, 0, size); in init_mqd()
142 m->header = 0xC0310800; in init_mqd()
143 m->compute_pipelinestat_enable = 1; in init_mqd()
145 m->compute_static_thread_mgmt_se0 = wa_mask; in init_mqd()
146 m->compute_static_thread_mgmt_se1 = wa_mask; in init_mqd()
147 m->compute_static_thread_mgmt_se2 = wa_mask; in init_mqd()
148 m->compute_static_thread_mgmt_se3 = wa_mask; in init_mqd()
149 m->compute_static_thread_mgmt_se4 = wa_mask; in init_mqd()
150 m->compute_static_thread_mgmt_se5 = wa_mask; in init_mqd()
151 m->compute_static_thread_mgmt_se6 = wa_mask; in init_mqd()
152 m->compute_static_thread_mgmt_se7 = wa_mask; in init_mqd()
154 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | in init_mqd()
157 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; in init_mqd()
159 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
160 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
162 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | in init_mqd()
169 m->cp_hqd_hq_status0 = 1 << 14; in init_mqd()
176 m->cp_hqd_hq_status0 |= 1 << 29; in init_mqd()
179 m->cp_hqd_aql_control = in init_mqd()
184 m->cp_hqd_persistent_state |= in init_mqd()
186 m->cp_hqd_ctx_save_base_addr_lo = in init_mqd()
188 m->cp_hqd_ctx_save_base_addr_hi = in init_mqd()
190 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; in init_mqd()
191 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; in init_mqd()
192 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; in init_mqd()
193 m->cp_hqd_wg_state_offset = q->ctl_stack_size; in init_mqd()
196 *mqd = m; in init_mqd()
199 mm->update_mqd(mm, m, q, NULL); in init_mqd()
220 struct v11_compute_mqd *m; in update_mqd() local
222 m = get_mqd(mqd); in update_mqd()
224 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in update_mqd()
225 m->cp_hqd_pq_control |= in update_mqd()
227 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; in update_mqd()
228 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
230 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
231 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
233 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd()
234 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd()
235 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd()
236 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd()
238 m->cp_hqd_pq_doorbell_control = in update_mqd()
242 m->cp_hqd_pq_doorbell_control); in update_mqd()
244 m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT; in update_mqd()
248 * is constrained by per-SE EOP done signal count, which is 8-bit. in update_mqd()
253 m->cp_hqd_eop_control = min(0xA, in update_mqd()
255 m->cp_hqd_eop_base_addr_lo = in update_mqd()
256 lower_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
257 m->cp_hqd_eop_base_addr_hi = in update_mqd()
258 upper_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
260 m->cp_hqd_iq_timer = 0; in update_mqd()
262 m->cp_hqd_vmid = q->vmid; in update_mqd()
266 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
269 m->cp_hqd_pq_doorbell_control |= in update_mqd()
273 m->cp_hqd_ctx_save_control = 0; in update_mqd()
276 set_priority(m, q); in update_mqd()
283 struct v11_compute_mqd *m = (struct v11_compute_mqd *)mqd; in check_preemption_failed() local
285 return kfd_check_hiq_mqd_doorbell_id(mm->dev, m->queue_doorbell_id0, 0); in check_preemption_failed()
294 struct v11_compute_mqd *m; in get_wave_state() local
297 m = get_mqd(mqd); in get_wave_state()
300 * is written forwards. Both starts from m->cp_hqd_cntl_stack_size. in get_wave_state()
301 * Current position is at m->cp_hqd_cntl_stack_offset and in get_wave_state()
302 * m->cp_hqd_wg_state_offset, respectively. in get_wave_state()
304 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - in get_wave_state()
305 m->cp_hqd_cntl_stack_offset; in get_wave_state()
306 *save_area_used_size = m->cp_hqd_wg_state_offset - in get_wave_state()
307 m->cp_hqd_cntl_stack_size; in get_wave_state()
316 header.wave_state.wave_state_offset = m->cp_hqd_wg_state_offset; in get_wave_state()
317 header.wave_state.control_stack_offset = m->cp_hqd_cntl_stack_offset; in get_wave_state()
327 struct v11_compute_mqd *m; in checkpoint_mqd() local
329 m = get_mqd(mqd); in checkpoint_mqd()
331 memcpy(mqd_dst, m, sizeof(struct v11_compute_mqd)); in checkpoint_mqd()
341 struct v11_compute_mqd *m; in restore_mqd() local
343 m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr; in restore_mqd()
346 memcpy(m, mqd_src, sizeof(*m)); in restore_mqd()
348 *mqd = m; in restore_mqd()
352 m->cp_hqd_pq_doorbell_control = in restore_mqd()
356 m->cp_hqd_pq_doorbell_control); in restore_mqd()
366 struct v11_compute_mqd *m; in init_mqd_hiq() local
370 m = get_mqd(*mqd); in init_mqd_hiq()
372 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
381 struct v11_compute_mqd *m; in destroy_hiq_mqd() local
384 m = get_mqd(mqd); in destroy_hiq_mqd()
386 doorbell_off = m->cp_hqd_pq_doorbell_control >> in destroy_hiq_mqd()
400 struct v11_sdma_mqd *m; in init_mqd_sdma() local
403 m = (struct v11_sdma_mqd *) mqd_mem_obj->cpu_ptr; in init_mqd_sdma()
410 memset(m, 0, size); in init_mqd_sdma()
411 *mqd = m; in init_mqd_sdma()
415 mm->update_mqd(mm, m, q, NULL); in init_mqd_sdma()
424 struct v11_sdma_mqd *m; in update_mqd_sdma() local
426 m = get_sdma_mqd(mqd); in update_mqd_sdma()
427 m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) in update_mqd_sdma()
434 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
435 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
436 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
437 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
438 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd_sdma()
439 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd_sdma()
440 m->sdmax_rlcx_doorbell_offset = in update_mqd_sdma()
443 m->sdmax_rlcx_sched_cntl = (amdgpu_sdma_phase_quantum in update_mqd_sdma()
447 m->sdma_engine_id = q->sdma_engine_id; in update_mqd_sdma()
448 m->sdma_queue_id = q->sdma_queue_id; in update_mqd_sdma()
449 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; in update_mqd_sdma()
456 static int debugfs_show_mqd(struct seq_file *m, void *data) in debugfs_show_mqd() argument
458 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, in debugfs_show_mqd()
463 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) in debugfs_show_mqd_sdma() argument
465 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, in debugfs_show_mqd_sdma()