40  * The 44-bit packet is mapped as {context_id1[7:0],context_id0[31:0]} plus
44  * Encoding type (0 = Auto, 1 = Wave, 2 = Error)
49  * - context_id0[24:0]
51  * Auto - only context_id0[8:0] is used, which reports various interrupts
52  * generated by SQG.  The rest is 0.
53  * Wave - user data sent from m0 via S_SENDMSG (context_id0[23:0])
54  * Error - Error Type (context_id0[24:21]), Error Details (context_id0[20:0])
57  * S_SENDMSG and Errors.  These are 0 for Auto.
61 	SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0,
67 	SQ_INTERRUPT_ERROR_TYPE_EDC_FUE = 0x0,
74 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE__SHIFT		0
85 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_MASK		0x00000001
86 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__WLT_MASK				0x00000002
87 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_BUF_FULL_MASK	0x00000004
88 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__REG_TIMESTAMP_MASK		0x00000008
89 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__CMD_TIMESTAMP_MASK		0x00000010
90 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__HOST_CMD_OVERFLOW_MASK		0x00000020
91 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__HOST_REG_OVERFLOW_MASK		0x00000040
92 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__IMMED_OVERFLOW_MASK		0x00000080
93 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_UTC_ERROR_MASK	0x00000100
94 #define SQ_INTERRUPT_WORD_AUTO_CTXID1__ENCODING_MASK			0x000000c0
97 #define SQ_INTERRUPT_WORD_WAVE_CTXID0__DATA__SHIFT	0
101 #define SQ_INTERRUPT_WORD_WAVE_CTXID1__SIMD_ID__SHIFT	0
105 #define SQ_INTERRUPT_WORD_WAVE_CTXID0__DATA_MASK	0x00ffffff /* [23:0] */
106 #define SQ_INTERRUPT_WORD_WAVE_CTXID0__SH_ID_MASK	0x02000000 /* [25] */
107 #define SQ_INTERRUPT_WORD_WAVE_CTXID0__PRIV_MASK	0x04000000 /* [26] */
108 #define SQ_INTERRUPT_WORD_WAVE_CTXID0__WAVE_ID_MASK	0xf8000000 /* [31:27] */
109 #define SQ_INTERRUPT_WORD_WAVE_CTXID1__SIMD_ID_MASK	0x00000003 /* [33:32] */
110 #define SQ_INTERRUPT_WORD_WAVE_CTXID1__WGP_ID_MASK	0x0000003c /* [37:34] */
111 #define SQ_INTERRUPT_WORD_WAVE_CTXID1__ENCODING_MASK	0x000000c0 /* [39:38] */
114 #define SQ_INTERRUPT_WORD_ERROR_CTXID0__DETAIL__SHIFT	0
119 #define SQ_INTERRUPT_WORD_ERROR_CTXID1__SIMD_ID__SHIFT	0
123 #define SQ_INTERRUPT_WORD_ERROR_CTXID0__DETAIL_MASK	0x001fffff /* [20:0] */
124 #define SQ_INTERRUPT_WORD_ERROR_CTXID0__TYPE_MASK	0x01e00000 /* [24:21] */
125 #define SQ_INTERRUPT_WORD_ERROR_CTXID0__SH_ID_MASK	0x02000000 /* [25] */
126 #define SQ_INTERRUPT_WORD_ERROR_CTXID0__PRIV_MASK	0x04000000 /* [26] */
127 #define SQ_INTERRUPT_WORD_ERROR_CTXID0__WAVE_ID_MASK	0xf8000000 /* [31:27] */
128 #define SQ_INTERRUPT_WORD_ERROR_CTXID1__SIMD_ID_MASK	0x00000003 /* [33:32] */
129 #define SQ_INTERRUPT_WORD_ERROR_CTXID1__WGP_ID_MASK	0x0000003c /* [37:34] */
130 #define SQ_INTERRUPT_WORD_ERROR_CTXID1__ENCODING_MASK	0x000000c0 /* [39:38] */
138 #define KFD_CTXID0_TRAP_CODE_MASK	0xfffc00
139 #define KFD_CTXID0_CP_BAD_OP_ECODE_MASK	0x3ffffff
140 #define KFD_CTXID0_DOORBELL_ID_MASK	0x0003ff
169 		"sq_intr: inst, data 0x%08x, sh %d, priv %d, wave_id %d, simd_id %d, wgp_id %d\n",  in print_sq_intr_info_inst()
181 		"sq_intr: error, detail 0x%08x, type %d, sh %d, priv %d, wave_id %d, simd_id %d, wgp_id %d\n",  in print_sq_intr_info_error()
194 	enum amdgpu_ras_block block = 0;  in event_interrupt_poison_consumption_v11()
196 	uint32_t reset = 0;  in event_interrupt_poison_consumption_v11()
258 	pr_debug("client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n",  in event_interrupt_isr_v11()
261 		 data[0], data[1], data[2], data[3],  in event_interrupt_isr_v11()
265 	if (WARN_ONCE(pasid == 0, "Bug: No PASID in KFD interrupt"))  in event_interrupt_isr_v11()
288 	struct kfd_vm_fault_info info = {0};  in event_interrupt_wq_v11()
307 			(uint64_t)(ih_ring_entry[5] & 0xf) << 32;  in event_interrupt_wq_v11()
308 		info.prot_valid = ring_id & 0x08;  in event_interrupt_wq_v11()
309 		info.prot_read  = ring_id & 0x10;  in event_interrupt_wq_v11()
310 		info.prot_write = ring_id & 0x20;  in event_interrupt_wq_v11()
312 		memset(&exception_data, 0, sizeof(exception_data));  in event_interrupt_wq_v11()
315 		exception_data.failure.NotPresent = info.prot_valid ? 1 : 0;  in event_interrupt_wq_v11()
316 		exception_data.failure.NoExecute = info.prot_exec ? 1 : 0;  in event_interrupt_wq_v11()
317 		exception_data.failure.ReadOnly = info.prot_write ? 1 : 0;  in event_interrupt_wq_v11()
318 		exception_data.failure.imprecise = 0;  in event_interrupt_wq_v11()
338 				NULL, 0);  in event_interrupt_wq_v11()
344 			kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28);  in event_interrupt_wq_v11()
365 						NULL, 0)))  in event_interrupt_wq_v11()
382 			kfd_signal_event_interrupt(pasid, context_id0 & 0xffffff, 24);  in event_interrupt_wq_v11()