amd/amdkfd/kfd_flat_memory.c

97  * The GPUVM_Base/GPUVM_Limit defines the aperture in the 64b space where we
115  * this case the GPUVM aperture (red) is defined and if a pointer falls in this
116  * aperture, we subtract the GPUVM_Base address and set the ATC bit to zero
150  * “Spare” aperture (APE1)
152  * We use the GPUVM aperture to differentiate ATC vs. GPUVM, but we also use
154  * config tables for setting cache policies. The “spare” (APE1) aperture is
156  * The default aperture isn’t an actual base/limit aperture; it is just the
163  * General Aperture definitions and rules
165  * An aperture register definition consists of a Base, Limit, Mtype, and
166  * usually an ATC bit indicating which translation tables that aperture uses.
167  * In all cases (for SUA and DUA apertures discussed later), aperture base
174  * The base and limit are considered inclusive to an aperture so being
175  * inside an aperture means (address >= Base) AND (address <= Limit).
178  * For example a load_dword_x4 that starts in one aperture and ends in another,
195  * space (defined by the aperture) for S_LOAD and FLAT_* ops.
196  * There is no spare (APE1) aperture for HSA32 mode.
202  * the default aperture is GPUVM (ATC==0) and not ATC space.
216  * the base/limit is “in” the aperture. For both HSA64 and GPUVM SUA modes,
227  * that fall in the private aperture are expanded as a function of the
230  * or ATC space. The addresses that fall in the shared aperture are
249  * Aperture Definitions for SUA and DUA
251  * The interpretation of the aperture register definitions for a given
302  * The aperture sizes are still 4GB implicitly.
304  * A GPUVM aperture is not applicable on GFXv9.
309 /* User mode manages most of the SVM aperture address space. The low
321 	 * aperture shouldn't be 0  in kfd_init_apertures_vi()
326 	/* dGPUs: SVM aperture starting at 0  in kfd_init_apertures_vi()