Lines Matching full:v0
533 // Save v0 by itself since it requires only two SGPRs.
538 global_store_dword_addtid v0, [s_save_ttmps_lo, s_save_ttmps_hi] V_COHERENCE
539 v_mov_b32 v0, 0x0
556 v_writelane_b32 v0, ttmp4, 0x4
557 v_writelane_b32 v0, ttmp5, 0x5
558 v_writelane_b32 v0, ttmp6, 0x6
559 v_writelane_b32 v0, ttmp7, 0x7
560 v_writelane_b32 v0, ttmp8, 0x8
561 v_writelane_b32 v0, ttmp9, 0x9
562 v_writelane_b32 v0, ttmp10, 0xA
563 v_writelane_b32 v0, ttmp11, 0xB
564 v_writelane_b32 v0, ttmp13, 0xD
565 v_writelane_b32 v0, exec_lo, 0xE
566 v_writelane_b32 v0, exec_hi, 0xF
570 global_store_dword_addtid v0, [s_save_ttmps_lo, s_save_ttmps_hi] inst_offset:0x40 V_COHERENCE
571 v_readlane_b32 ttmp14, v0, 0xE
572 v_readlane_b32 ttmp15, v0, 0xF
620 write_vgprs_to_mem_with_sqc_w32(v0, 4, s_save_buf_rsrc0, s_save_mem_offset)
627 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE
629 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:128
630 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:128*2
631 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:128*3
643 write_vgprs_to_mem_with_sqc_w64(v0, 4, s_save_buf_rsrc0, s_save_mem_offset)
650 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE
652 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:256
653 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:256*2
654 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:256*3
668 v_mov_b32 v0, 0x0 //Offset[31:0] from buffer resource
729 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE
772 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE
793 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE
838 //load 0~63*4(byte address) to vgpr v0
839 v_mbcnt_lo_u32_b32 v0, -1, 0
840 v_mbcnt_hi_u32_b32 v0, -1, v0
841 v_mul_u32_u24 v0, 4, v0
855 ds_read_b32 v1, v0
861 v_add_nc_u32 v0, v0, 128 //mem offset increased by 128 bytes
875 ds_read_b32 v1, v0
877 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE
881 v_add_nc_u32 v0, v0, 128 //mem offset increased by 128 bytes
893 ds_read_b32 v1, v0
899 v_add_nc_u32 v0, v0, 256 //mem offset increased by 256 bytes
913 ds_read_b32 v1, v0
915 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE
919 v_add_nc_u32 v0, v0, 256 //mem offset increased by 256 bytes
962 v_movrels_b32 v0, v0 //v0 = v[0+m0]
967 write_vgprs_to_mem_with_sqc_w32(v0, 4, s_save_buf_rsrc0, s_save_mem_offset)
977 v_movrels_b32 v0, v0 //v0 = v[0+m0]
982 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE
983 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:128
984 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:128*2
985 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:128*3
1007 v_movrels_b32 v0, v0 //v0 = v[0+m0]
1012 write_vgprs_to_mem_with_sqc_w64(v0, 4, s_save_buf_rsrc0, s_save_mem_offset)
1022 v_movrels_b32 v0, v0 //v0 = v[0+m0]
1027 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE
1028 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:256
1029 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:256*2
1030 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:256*3
1054 v_movrels_b32 v0, v0
1056 write_vgprs_to_mem_with_sqc_w64(v0, 1, s_save_buf_rsrc0, s_save_mem_offset)
1066 v_movrels_b32 v0, v0 //v0 = v[0+m0]
1067 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE
1131 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW
1133 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset
1135 ds_store_addtid_b32 v0
1145 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW
1147 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset
1149 ds_store_addtid_b32 v0
1182 …s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be th…
1189 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE
1190 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE offset:128
1191 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE offset:128*2
1192 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE offset:128*3
1194 v_movreld_b32 v0, v0 //v[0+m0] = v0
1201 s_cbranch_scc1 L_RESTORE_VGPR_WAVE32_LOOP //VGPR restore (except v0) is complete?
1203 /* VGPR restore on v0 */
1204 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE
1205 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE offset:128
1206 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE offset:128*2
1207 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE offset:128*3
1216 …s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v4, v0 will be th…
1223 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE
1224 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE offset:256
1225 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE offset:256*2
1226 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE offset:256*3
1228 v_movreld_b32 v0, v0 //v[0+m0] = v0
1235 s_cbranch_scc1 L_RESTORE_VGPR_WAVE64_LOOP //VGPR restore (except v0) is complete?
1249 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE
1251 v_movreld_b32 v0, v0 //v[0+m0] = v0
1255 s_cbranch_scc1 L_RESTORE_SHARED_VGPR_WAVE64_LOOP //VGPR restore (except v0) is complete?
1257 s_mov_b32 exec_hi, 0xFFFFFFFF //restore back exec_hi before restoring V0!!
1259 /* VGPR restore on v0 */
1261 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE
1262 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE offset:256
1263 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE offset:256*2
1264 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE offset:256*3