Lines Matching defs:var
72 var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006 label
73 var SQ_WAVE_STATUS_HALT_MASK = 0x2000 label
74 var SQ_WAVE_STATUS_ECC_ERR_MASK = 0x20000 label
75 var SQ_WAVE_STATUS_TRAP_EN_SHIFT = 6 label
76 var SQ_WAVE_IB_STS2_WAVE64_SHIFT = 11 label
77 var SQ_WAVE_IB_STS2_WAVE64_SIZE = 1 label
78 var SQ_WAVE_LDS_ALLOC_GRANULARITY = 8 label
79 var S_STATUS_HWREG = HW_REG_STATUS label
80 var S_STATUS_ALWAYS_CLEAR_MASK = SQ_WAVE_STATUS_SPI_PRIO_MASK|SQ_WAVE_STATUS_ECC_ERR_MASK label
81 var S_STATUS_HALT_MASK = SQ_WAVE_STATUS_HALT_MASK label
82 var S_SAVE_PC_HI_TRAP_ID_MASK = 0x00FF0000 label
83 var S_SAVE_PC_HI_HT_MASK = 0x01000000 label
85 var SQ_WAVE_STATE_PRIV_BARRIER_COMPLETE_MASK = 0x4 label
86 var SQ_WAVE_STATE_PRIV_SCC_SHIFT = 9 label
87 var SQ_WAVE_STATE_PRIV_SYS_PRIO_MASK = 0xC00 label
88 var SQ_WAVE_STATE_PRIV_HALT_MASK = 0x4000 label
89 var SQ_WAVE_STATE_PRIV_POISON_ERR_MASK = 0x8000 label
90 var SQ_WAVE_STATE_PRIV_POISON_ERR_SHIFT = 15 label
91 var SQ_WAVE_STATUS_WAVE64_SHIFT = 29 label
92 var SQ_WAVE_STATUS_WAVE64_SIZE = 1 label
93 var SQ_WAVE_LDS_ALLOC_GRANULARITY = 9 label
94 var S_STATUS_HWREG = HW_REG_WAVE_STATE_PRIV label
95 var S_STATUS_ALWAYS_CLEAR_MASK = SQ_WAVE_STATE_PRIV_SYS_PRIO_MASK|SQ_WAVE_STATE_PRIV_POISON_ERR_M… label
96 var S_STATUS_HALT_MASK = SQ_WAVE_STATE_PRIV_HALT_MASK label
97 var S_SAVE_PC_HI_TRAP_ID_MASK = 0xF0000000 label
100 var SQ_WAVE_STATUS_NO_VGPRS_SHIFT = 24 label
101 var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 label
102 var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 label
103 var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 8 label
104 var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT = 24 label
105 var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE = 4 label
108 var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 8 label
110 var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 12 label
114 var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400 label
115 var SQ_WAVE_TRAPSTS_EXCP_MASK = 0x1FF label
116 var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT = 10 label
117 var SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK = 0x80 label
118 var SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT = 7 label
119 var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100 label
120 var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8 label
121 var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK = 0x800 label
122 var SQ_WAVE_TRAPSTS_ILLEGAL_INST_SHIFT = 11 label
123 var SQ_WAVE_TRAPSTS_EXCP_HI_MASK = 0x7000 label
125 var SQ_WAVE_TRAPSTS_HOST_TRAP_SHIFT = 16 label
126 var SQ_WAVE_TRAPSTS_WAVE_START_MASK = 0x20000 label
127 var SQ_WAVE_TRAPSTS_WAVE_START_SHIFT = 17 label
128 var SQ_WAVE_TRAPSTS_WAVE_END_MASK = 0x40000 label
129 var SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK = 0x100000 label
131 var SQ_WAVE_TRAPSTS_XNACK_ERROR_MASK = 0x10000000 label
133 var SQ_WAVE_MODE_EXCP_EN_SHIFT = 12 label
134 var SQ_WAVE_MODE_EXCP_EN_ADDR_WATCH_SHIFT = 19 label
136 var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT = 15 label
137 var SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT = 25 label
138 var SQ_WAVE_IB_STS_REPLAY_W64H_MASK = 0x02000000 label
139 var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK = 0x003F8000 label
141 var SQ_WAVE_MODE_DEBUG_EN_MASK = 0x800 label
143 var S_TRAPSTS_RESTORE_PART_1_SIZE = SQ_WAVE_TRAPSTS_SAVECTX_SHIFT label
144 var S_TRAPSTS_RESTORE_PART_2_SHIFT = SQ_WAVE_TRAPSTS_ILLEGAL_INST_SHIFT label
147 var S_TRAPSTS_NON_MASKABLE_EXCP_MASK = SQ_WAVE_TRAPSTS_MEM_VIOL_MASK|SQ_WAVE_TRAPSTS_ILLEGAL_INST_… label
148 var S_TRAPSTS_RESTORE_PART_2_SIZE = 32 - S_TRAPSTS_RESTORE_PART_2_SHIFT label
149 var S_TRAPSTS_RESTORE_PART_3_SHIFT = 0 label
150 var S_TRAPSTS_RESTORE_PART_3_SIZE = 0 label
156 SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK
157 var S_TRAPSTS_RESTORE_PART_2_SIZE = SQ_WAVE_TRAPSTS_HOST_TRAP_SHIFT - SQ_WAVE_TRAPSTS_ILLEGAL_INST… label
158 var S_TRAPSTS_RESTORE_PART_3_SHIFT = SQ_WAVE_TRAPSTS_WAVE_START_SHIFT label
159 var S_TRAPSTS_RESTORE_PART_3_SIZE = 32 - S_TRAPSTS_RESTORE_PART_3_SHIFT label
161 var S_TRAPSTS_HWREG = HW_REG_TRAPSTS label
162 var S_TRAPSTS_SAVE_CONTEXT_MASK = SQ_WAVE_TRAPSTS_SAVECTX_MASK label
163 var S_TRAPSTS_SAVE_CONTEXT_SHIFT = SQ_WAVE_TRAPSTS_SAVECTX_SHIFT label
165 var SQ_WAVE_EXCP_FLAG_PRIV_ADDR_WATCH_MASK = 0xF label
166 var SQ_WAVE_EXCP_FLAG_PRIV_MEM_VIOL_MASK = 0x10 label
167 var SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_SHIFT = 5 label
168 var SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_MASK = 0x20 label
169 var SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_MASK = 0x40 label
170 var SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_SHIFT = 6 label
171 var SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_MASK = 0x80 label
172 var SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT = 7 label
173 var SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_MASK = 0x100 label
174 var SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_SHIFT = 8 label
175 var SQ_WAVE_EXCP_FLAG_PRIV_WAVE_END_MASK = 0x200 label
176 var SQ_WAVE_EXCP_FLAG_PRIV_TRAP_AFTER_INST_MASK = 0x800 label
177 var SQ_WAVE_TRAP_CTRL_ADDR_WATCH_MASK = 0x80 label
178 var SQ_WAVE_TRAP_CTRL_TRAP_AFTER_INST_MASK = 0x200 label
180 var S_TRAPSTS_HWREG = HW_REG_WAVE_EXCP_FLAG_PRIV label
181 var S_TRAPSTS_SAVE_CONTEXT_MASK = SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_MASK label
182 var S_TRAPSTS_SAVE_CONTEXT_SHIFT = SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_SHIFT label
188 SQ_WAVE_EXCP_FLAG_PRIV_TRAP_AFTER_INST_MASK
189 var S_TRAPSTS_RESTORE_PART_1_SIZE = SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_SHIFT label
190 var S_TRAPSTS_RESTORE_PART_2_SHIFT = SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_SHIFT label
191 var S_TRAPSTS_RESTORE_PART_2_SIZE = SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT - SQ_WAVE_EXCP_FLAG_PRI… label
192 var S_TRAPSTS_RESTORE_PART_3_SHIFT = SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_SHIFT label
193 var S_TRAPSTS_RESTORE_PART_3_SIZE = 32 - S_TRAPSTS_RESTORE_PART_3_SHIFT label
194 var BARRIER_STATE_SIGNAL_OFFSET = 16 label
195 var BARRIER_STATE_VALID_OFFSET = 0 label
199 var TTMP11_SAVE_REPLAY_W64H_SHIFT = 31 label
200 var TTMP11_SAVE_REPLAY_W64H_MASK = 0x80000000 label
201 var TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT = 24 label
202 var TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK = 0x7F000000 label
203 var TTMP11_DEBUG_TRAP_ENABLED_SHIFT = 23 label
204 var TTMP11_DEBUG_TRAP_ENABLED_MASK = 0x800000 label
208 var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 label
209 var S_SAVE_BUF_RSRC_WORD3_MISC = 0x10807FAC label
210 var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 label
211 var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 label
213 var S_SAVE_PC_HI_FIRST_WAVE_MASK = 0x80000000 label
214 var S_SAVE_PC_HI_FIRST_WAVE_SHIFT = 31 label
216 var s_sgpr_save_num = 108 label
218 var s_save_spi_init_lo = exec_lo label
219 var s_save_spi_init_hi = exec_hi label
220 var s_save_pc_lo = ttmp0 label
221 var s_save_pc_hi = ttmp1 label
222 var s_save_exec_lo = ttmp2 label
223 var s_save_exec_hi = ttmp3 label
224 var s_save_status = ttmp12 label
225 var s_save_trapsts = ttmp15 label
226 var s_save_xnack_mask = s_save_trapsts label
227 var s_wave_size = ttmp7 label
228 var s_save_buf_rsrc0 = ttmp8 label
229 var s_save_buf_rsrc1 = ttmp9 label
230 var s_save_buf_rsrc2 = ttmp10 label
231 var s_save_buf_rsrc3 = ttmp11 label
232 var s_save_mem_offset = ttmp4 label
233 var s_save_alloc_size = s_save_trapsts label
234 var s_save_tmp = ttmp14 label
235 var s_save_m0 = ttmp5 label
236 var s_save_ttmps_lo = s_save_tmp label
237 var s_save_ttmps_hi = s_save_trapsts label
239 var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE label
240 var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC label
242 var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 label
243 var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26 label
244 var S_WAVE_SIZE = 25 label
246 var s_restore_spi_init_lo = exec_lo label
247 var s_restore_spi_init_hi = exec_hi label
248 var s_restore_mem_offset = ttmp12 label
249 var s_restore_alloc_size = ttmp3 label
250 var s_restore_tmp = ttmp2 label
251 var s_restore_mem_offset_save = s_restore_tmp label
252 var s_restore_m0 = s_restore_alloc_size label
253 var s_restore_mode = ttmp7 label
254 var s_restore_flat_scratch = s_restore_tmp label
255 var s_restore_pc_lo = ttmp0 label
256 var s_restore_pc_hi = ttmp1 label
257 var s_restore_exec_lo = ttmp4 label
258 var s_restore_exec_hi = ttmp5 label
259 var s_restore_status = ttmp14 label
260 var s_restore_trapsts = ttmp15 label
261 var s_restore_xnack_mask = ttmp13 label
262 var s_restore_buf_rsrc0 = ttmp8 label
263 var s_restore_buf_rsrc1 = ttmp9 label
264 var s_restore_buf_rsrc2 = ttmp10 label
265 var s_restore_buf_rsrc3 = ttmp11 label
266 var s_restore_size = ttmp6 label
267 var s_restore_ttmps_lo = s_restore_tmp label
268 var s_restore_ttmps_hi = s_restore_alloc_size label
269 var s_restore_spi_init_hi_save = s_restore_exec_hi label