68 	base = vpe->ring.adev->reg_offset[VPE_HWIP][inst][0];  in vpe_v6_1_get_reg_offset()
73 static void vpe_v6_1_halt(struct amdgpu_vpe *vpe, bool halt)  in vpe_v6_1_halt()  argument
75 	struct amdgpu_device *adev = vpe->ring.adev;  in vpe_v6_1_halt()
78 	for (i = 0; i < vpe->num_instances; i++) {  in vpe_v6_1_halt()
80 		f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, halt ? 1 : 0);  in vpe_v6_1_halt()
81 		f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, halt ? 1 : 0);  in vpe_v6_1_halt()
93 				&adev->vpe.trap_irq);  in vpe_v6_1_irq_init()
102 	struct amdgpu_device *adev = vpe->ring.adev;  in vpe_v6_1_set_collaborate_mode()
105 	if (!vpe->collaborate_mode)  in vpe_v6_1_set_collaborate_mode()
108 	for (i = 0; i < vpe->num_instances; i++) {  in vpe_v6_1_set_collaborate_mode()
125 	struct amdgpu_device *adev = vpe->ring.adev;  in vpe_v6_1_load_microcode()
133 	for (j = 0; j < vpe->num_instances; j++) {  in vpe_v6_1_load_microcode()
152 		dev_warn(adev->dev, "VPE failed to enable DPM\n");  in vpe_v6_1_load_microcode()
158 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {  in vpe_v6_1_load_microcode()
163 		f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0);  in vpe_v6_1_load_microcode()
166 		adev->vpe.cmdbuf_cpu_addr[0] = f32_offset;  in vpe_v6_1_load_microcode()
167 		adev->vpe.cmdbuf_cpu_addr[1] = f32_cntl;  in vpe_v6_1_load_microcode()
172 	vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data;  in vpe_v6_1_load_microcode()
175 	ucode_offset[0] = le32_to_cpu(vpe_hdr->header.ucode_array_offset_bytes);  in vpe_v6_1_load_microcode()
176 	ucode_size[0] = le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes);  in vpe_v6_1_load_microcode()
178 	ucode_offset[1] = le32_to_cpu(vpe_hdr->ctl_ucode_offset);  in vpe_v6_1_load_microcode()
179 	ucode_size[1] = le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes);  in vpe_v6_1_load_microcode()
183 	for (j = 0; j < vpe->num_instances; j++) {  in vpe_v6_1_load_microcode()
190 			data = (const __le32 *)(adev->vpe.fw->data + ucode_offset[i]);  in vpe_v6_1_load_microcode()
193 			while (size_dw--) {  in vpe_v6_1_load_microcode()
208 	struct amdgpu_ring *ring = &vpe->ring;  in vpe_v6_1_ring_start()
209 	struct amdgpu_device *adev = ring->adev;  in vpe_v6_1_ring_start()
215 	for (i = 0; i < vpe->num_instances; i++) {  in vpe_v6_1_ring_start()
217 		rb_bufsz = order_base_2(ring->ring_size / 4);  in vpe_v6_1_ring_start()
232 			lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);  in vpe_v6_1_ring_start()
234 			upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);  in vpe_v6_1_ring_start()
238 		WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_BASE), ring->gpu_addr >> 8);  in vpe_v6_1_ring_start()
239 		WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);  in vpe_v6_1_ring_start()
241 		ring->wptr = 0;  in vpe_v6_1_ring_start()
245 		WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);  in vpe_v6_1_ring_start()
246 		WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);  in vpe_v6_1_ring_start()
251 …doorbell_offset = REG_SET_FIELD(doorbell_offset, VPEC_QUEUE0_DOORBELL_OFFSET, OFFSET, ring->doorbe…  in vpe_v6_1_ring_start()
255 		doorbell = REG_SET_FIELD(doorbell, VPEC_QUEUE0_DOORBELL, ENABLE, ring->use_doorbell ? 1 : 0);  in vpe_v6_1_ring_start()
258 		adev->nbio.funcs->vpe_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index + i*4, 4);  in vpe_v6_1_ring_start()
278 	struct amdgpu_device *adev = vpe->ring.adev;  in vpe_v_6_1_ring_stop()
282 	for (i = 0; i < vpe->num_instances; i++) {  in vpe_v_6_1_ring_stop()
301 			dev_err(adev->dev, "VPE queue reset failed\n");  in vpe_v_6_1_ring_stop()
304 	vpe->ring.sched.ready = false;  in vpe_v_6_1_ring_stop()
314 	struct amdgpu_vpe *vpe = &adev->vpe;  in vpe_v6_1_set_trap_irq_state()
338 	dev_dbg(adev->dev, "IH: VPE trap\n");  in vpe_v6_1_process_trap_irq()
340 	switch (entry->client_id) {  in vpe_v6_1_process_trap_irq()
342 		amdgpu_fence_process(&adev->vpe.ring);  in vpe_v6_1_process_trap_irq()
355 	vpe->regs.queue0_rb_rptr_lo = regVPEC_QUEUE0_RB_RPTR;  in vpe_v6_1_set_regs()
356 	vpe->regs.queue0_rb_rptr_hi = regVPEC_QUEUE0_RB_RPTR_HI;  in vpe_v6_1_set_regs()
357 	vpe->regs.queue0_rb_wptr_lo = regVPEC_QUEUE0_RB_WPTR;  in vpe_v6_1_set_regs()
358 	vpe->regs.queue0_rb_wptr_hi = regVPEC_QUEUE0_RB_WPTR_HI;  in vpe_v6_1_set_regs()
359 	vpe->regs.queue0_preempt = regVPEC_QUEUE0_PREEMPT;  in vpe_v6_1_set_regs()
362 		vpe->regs.dpm_enable = regVPEC_PUB_DUMMY2_6_1_1;  in vpe_v6_1_set_regs()
364 		vpe->regs.dpm_enable = regVPEC_PUB_DUMMY2;  in vpe_v6_1_set_regs()
366 	vpe->regs.dpm_pratio = regVPEC_QUEUE6_DUMMY4;  in vpe_v6_1_set_regs()
367 	vpe->regs.dpm_request_interval = regVPEC_QUEUE5_DUMMY3;  in vpe_v6_1_set_regs()
368 	vpe->regs.dpm_decision_threshold = regVPEC_QUEUE5_DUMMY4;  in vpe_v6_1_set_regs()
369 	vpe->regs.dpm_busy_clamp_threshold = regVPEC_QUEUE7_DUMMY2;  in vpe_v6_1_set_regs()
370 	vpe->regs.dpm_idle_clamp_threshold = regVPEC_QUEUE7_DUMMY3;  in vpe_v6_1_set_regs()
371 	vpe->regs.dpm_request_lv = regVPEC_QUEUE7_DUMMY1;  in vpe_v6_1_set_regs()
372 	vpe->regs.context_indicator = regVPEC_QUEUE6_DUMMY3;  in vpe_v6_1_set_regs()
396 	vpe->funcs = &vpe_v6_1_funcs;  in vpe_v6_1_set_funcs()
397 	vpe->trap_irq.funcs = &vpe_v6_1_trap_irq_funcs;  in vpe_v6_1_set_funcs()