Lines Matching refs:IH_RB_CNTL
114 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); in vega20_ih_toggle_ring_interrupts()
115 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1); in vega20_ih_toggle_ring_interrupts()
119 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); in vega20_ih_toggle_ring_interrupts()
171 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega20_ih_rb_cntl()
173 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega20_ih_rb_cntl()
175 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega20_ih_rb_cntl()
177 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in vega20_ih_rb_cntl()
181 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega20_ih_rb_cntl()
183 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); in vega20_ih_rb_cntl()
184 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); in vega20_ih_rb_cntl()
185 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); in vega20_ih_rb_cntl()
232 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); in vega20_ih_enable_ring()
234 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); in vega20_ih_enable_ring()
425 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in vega20_ih_get_wptr()
431 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); in vega20_ih_get_wptr()