Lines Matching +full:0 +full:x0007ffff
26 #define SDMA_OP_NOP 0
42 #define SDMA_SUBOP_TIMESTAMP_SET 0
45 #define SDMA_SUBOP_COPY_LINEAR 0
53 #define SDMA_SUBOP_WRITE_LINEAR 0
55 #define SDMA_SUBOP_PTEPDE_GEN 0
65 #define SDMA_OP_AQL_COPY 0
66 #define SDMA_OP_AQL_BARRIER_OR 0
69 #define SDMA_PKT_HEADER_op_offset 0
70 #define SDMA_PKT_HEADER_op_mask 0x000000FF
71 #define SDMA_PKT_HEADER_op_shift 0
75 #define SDMA_PKT_HEADER_sub_op_offset 0
76 #define SDMA_PKT_HEADER_sub_op_mask 0x000000FF
87 #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0
88 #define SDMA_PKT_COPY_LINEAR_HEADER_op_mask 0x000000FF
89 #define SDMA_PKT_COPY_LINEAR_HEADER_op_shift 0
93 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0
94 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask 0x000000FF
99 #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset 0
100 #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask 0x00000001
105 #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset 0
106 #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask 0x00000001
111 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0
112 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask 0x00000001
119 #define SDMA_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF
120 #define SDMA_PKT_COPY_LINEAR_COUNT_count_shift 0
126 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003
132 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003
139 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF
140 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0
146 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF
147 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0
153 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
154 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0
160 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
161 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0
171 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset 0
172 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask 0x000000FF
173 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift 0
177 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset 0
178 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask 0x000000FF
183 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset 0
184 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask 0x00000001
189 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset 0
190 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask 0x00000001
197 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask 0x003FFFFF
198 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift 0
204 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask 0x00000003
210 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask 0x00000001
216 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask 0x00000001
222 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask 0x00000001
228 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask 0x00000001
234 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask 0x00000003
240 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask 0x00000001
246 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask 0x00000001
252 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask 0x00000001
259 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF
260 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift 0
266 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF
267 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift 0
273 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
274 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift 0
280 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
281 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift 0
291 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset 0
292 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask 0x000000FF
293 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift 0
297 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset 0
298 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask 0x000000FF
303 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset 0
304 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask 0x00000001
311 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask 0x003FFFFF
312 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift 0
318 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask 0x00000003
324 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask 0x00000001
330 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask 0x00000001
336 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask 0x00000001
342 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask 0x00000001
348 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask 0x00000001
354 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask 0x00000003
360 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask 0x00000001
366 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask 0x00000001
372 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask 0x00000001
378 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask 0x00000001
385 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF
386 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0
392 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF
393 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0
399 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
400 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0
406 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
407 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0
417 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0
418 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask 0x000000FF
419 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift 0
423 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0
424 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask 0x000000FF
429 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset 0
430 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask 0x00000001
435 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset 0
436 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask 0x00000001
441 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0
442 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask 0x00000001
449 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask 0x003FFFFF
450 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift 0
456 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask 0x00000003
462 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask 0x00000003
468 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask 0x00000003
475 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF
476 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0
482 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF
483 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0
489 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask 0xFFFFFFFF
490 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift 0
496 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask 0xFFFFFFFF
497 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift 0
503 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask 0xFFFFFFFF
504 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift 0
510 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask 0xFFFFFFFF
511 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift 0
521 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0
522 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask 0x000000FF
523 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift 0
527 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0
528 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask 0x000000FF
533 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset 0
534 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask 0x00000001
539 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0
540 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask 0x00000007
547 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF
548 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift 0
554 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF
555 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift 0
561 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask 0x00003FFF
562 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift 0
567 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask 0x00003FFF
574 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask 0x000007FF
575 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift 0
580 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask 0x0007FFFF
587 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask 0x0FFFFFFF
588 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift 0
594 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
595 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift 0
601 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
602 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift 0
608 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask 0x00003FFF
609 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift 0
614 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask 0x00003FFF
621 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask 0x000007FF
622 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift 0
627 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask 0x0007FFFF
634 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask 0x0FFFFFFF
635 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift 0
641 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask 0x00003FFF
642 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift 0
647 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask 0x00003FFF
654 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask 0x000007FF
655 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift 0
660 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask 0x00000003
666 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask 0x00000003
677 #define SDMA_PKT_COPY_TILED_HEADER_op_offset 0
678 #define SDMA_PKT_COPY_TILED_HEADER_op_mask 0x000000FF
679 #define SDMA_PKT_COPY_TILED_HEADER_op_shift 0
683 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0
684 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask 0x000000FF
689 #define SDMA_PKT_COPY_TILED_HEADER_encrypt_offset 0
690 #define SDMA_PKT_COPY_TILED_HEADER_encrypt_mask 0x00000001
695 #define SDMA_PKT_COPY_TILED_HEADER_tmz_offset 0
696 #define SDMA_PKT_COPY_TILED_HEADER_tmz_mask 0x00000001
701 #define SDMA_PKT_COPY_TILED_HEADER_mip_max_offset 0
702 #define SDMA_PKT_COPY_TILED_HEADER_mip_max_mask 0x0000000F
707 #define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0
708 #define SDMA_PKT_COPY_TILED_HEADER_detile_mask 0x00000001
715 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF
716 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift 0
722 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF
723 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift 0
729 #define SDMA_PKT_COPY_TILED_DW_3_width_mask 0x00003FFF
730 #define SDMA_PKT_COPY_TILED_DW_3_width_shift 0
736 #define SDMA_PKT_COPY_TILED_DW_4_height_mask 0x00003FFF
737 #define SDMA_PKT_COPY_TILED_DW_4_height_shift 0
742 #define SDMA_PKT_COPY_TILED_DW_4_depth_mask 0x000007FF
749 #define SDMA_PKT_COPY_TILED_DW_5_element_size_mask 0x00000007
750 #define SDMA_PKT_COPY_TILED_DW_5_element_size_shift 0
755 #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask 0x0000001F
761 #define SDMA_PKT_COPY_TILED_DW_5_dimension_mask 0x00000003
767 #define SDMA_PKT_COPY_TILED_DW_5_epitch_mask 0x0000FFFF
774 #define SDMA_PKT_COPY_TILED_DW_6_x_mask 0x00003FFF
775 #define SDMA_PKT_COPY_TILED_DW_6_x_shift 0
780 #define SDMA_PKT_COPY_TILED_DW_6_y_mask 0x00003FFF
787 #define SDMA_PKT_COPY_TILED_DW_7_z_mask 0x000007FF
788 #define SDMA_PKT_COPY_TILED_DW_7_z_shift 0
793 #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask 0x00000003
799 #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask 0x00000003
806 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF
807 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift 0
813 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF
814 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift 0
820 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF
821 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift 0
827 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF
828 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0
834 #define SDMA_PKT_COPY_TILED_COUNT_count_mask 0x000FFFFF
835 #define SDMA_PKT_COPY_TILED_COUNT_count_shift 0
845 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0
846 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask 0x000000FF
847 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift 0
851 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0
852 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask 0x000000FF
857 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset 0
858 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask 0x00000001
863 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset 0
864 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask 0x00000001
869 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_offset 0
870 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask 0x0000000F
875 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0
876 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask 0x00000001
881 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0
882 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask 0x00000001
889 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask 0xFFFFFFFF
890 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift 0
896 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask 0xFFFFFFFF
897 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift 0
903 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask 0xFFFFFFFF
904 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift 0
910 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask 0xFFFFFFFF
911 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift 0
917 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask 0x00003FFF
918 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift 0
924 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask 0x00003FFF
925 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift 0
930 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask 0x000007FF
937 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask 0x00000007
938 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift 0
943 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask 0x0000001F
949 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask 0x00000003
955 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask 0x0000FFFF
962 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask 0x00003FFF
963 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift 0
968 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask 0x00003FFF
975 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask 0x000007FF
976 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift 0
982 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask 0x00000003
988 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask 0x00000003
994 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask 0x00000003
1001 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF
1002 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift 0
1008 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF
1009 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift 0
1015 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF
1016 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift 0
1022 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF
1023 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0
1029 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask 0x000FFFFF
1030 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift 0
1040 #define SDMA_PKT_COPY_T2T_HEADER_op_offset 0
1041 #define SDMA_PKT_COPY_T2T_HEADER_op_mask 0x000000FF
1042 #define SDMA_PKT_COPY_T2T_HEADER_op_shift 0
1046 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0
1047 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask 0x000000FF
1052 #define SDMA_PKT_COPY_T2T_HEADER_tmz_offset 0
1053 #define SDMA_PKT_COPY_T2T_HEADER_tmz_mask 0x00000001
1058 #define SDMA_PKT_COPY_T2T_HEADER_mip_max_offset 0
1059 #define SDMA_PKT_COPY_T2T_HEADER_mip_max_mask 0x0000000F
1066 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF
1067 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift 0
1073 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF
1074 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift 0
1080 #define SDMA_PKT_COPY_T2T_DW_3_src_x_mask 0x00003FFF
1081 #define SDMA_PKT_COPY_T2T_DW_3_src_x_shift 0
1086 #define SDMA_PKT_COPY_T2T_DW_3_src_y_mask 0x00003FFF
1093 #define SDMA_PKT_COPY_T2T_DW_4_src_z_mask 0x000007FF
1094 #define SDMA_PKT_COPY_T2T_DW_4_src_z_shift 0
1099 #define SDMA_PKT_COPY_T2T_DW_4_src_width_mask 0x00003FFF
1106 #define SDMA_PKT_COPY_T2T_DW_5_src_height_mask 0x00003FFF
1107 #define SDMA_PKT_COPY_T2T_DW_5_src_height_shift 0
1112 #define SDMA_PKT_COPY_T2T_DW_5_src_depth_mask 0x000007FF
1119 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask 0x00000007
1120 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift 0
1125 #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask 0x0000001F
1131 #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask 0x00000003
1137 #define SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask 0x0000FFFF
1144 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
1145 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift 0
1151 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
1152 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift 0
1158 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask 0x00003FFF
1159 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift 0
1164 #define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask 0x00003FFF
1171 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask 0x000007FF
1172 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift 0
1177 #define SDMA_PKT_COPY_T2T_DW_10_dst_width_mask 0x00003FFF
1184 #define SDMA_PKT_COPY_T2T_DW_11_dst_height_mask 0x00003FFF
1185 #define SDMA_PKT_COPY_T2T_DW_11_dst_height_shift 0
1190 #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask 0x000007FF
1197 #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask 0x00000007
1198 #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift 0
1203 #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask 0x0000001F
1209 #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask 0x00000003
1215 #define SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask 0x0000FFFF
1222 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask 0x00003FFF
1223 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift 0
1228 #define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask 0x00003FFF
1235 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask 0x000007FF
1236 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift 0
1241 #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask 0x00000003
1247 #define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask 0x00000003
1258 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0
1259 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask 0x000000FF
1260 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift 0
1264 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0
1265 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask 0x000000FF
1270 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset 0
1271 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask 0x00000001
1276 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_offset 0
1277 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask 0x0000000F
1282 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_offset 0
1283 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask 0x0000000F
1288 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0
1289 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask 0x00000001
1296 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF
1297 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift 0
1303 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF
1304 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift 0
1310 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask 0x00003FFF
1311 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift 0
1316 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask 0x00003FFF
1323 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask 0x000007FF
1324 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift 0
1329 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask 0x00003FFF
1336 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask 0x00003FFF
1337 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift 0
1342 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask 0x000007FF
1349 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask 0x00000007
1350 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift 0
1355 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask 0x0000001F
1361 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask 0x00000003
1367 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask 0x0000FFFF
1374 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF
1375 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift 0
1381 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF
1382 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift 0
1388 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask 0x00003FFF
1389 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift 0
1394 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask 0x00003FFF
1401 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask 0x000007FF
1402 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift 0
1407 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask 0x00003FFF
1414 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask 0x0FFFFFFF
1415 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift 0
1421 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask 0x00003FFF
1422 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift 0
1427 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask 0x00003FFF
1434 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask 0x000007FF
1435 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift 0
1440 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask 0x00000003
1446 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask 0x00000003
1457 #define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0
1458 #define SDMA_PKT_COPY_STRUCT_HEADER_op_mask 0x000000FF
1459 #define SDMA_PKT_COPY_STRUCT_HEADER_op_shift 0
1463 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0
1464 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask 0x000000FF
1469 #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset 0
1470 #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask 0x00000001
1475 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0
1476 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask 0x00000001
1483 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask 0xFFFFFFFF
1484 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift 0
1490 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask 0xFFFFFFFF
1491 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift 0
1497 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask 0xFFFFFFFF
1498 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift 0
1504 #define SDMA_PKT_COPY_STRUCT_COUNT_count_mask 0xFFFFFFFF
1505 #define SDMA_PKT_COPY_STRUCT_COUNT_count_shift 0
1511 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask 0x000007FF
1512 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift 0
1517 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask 0x00000003
1523 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask 0x00000003
1530 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF
1531 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift 0
1537 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF
1538 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift 0
1548 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0
1549 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask 0x000000FF
1550 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift 0
1554 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0
1555 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask 0x000000FF
1560 #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset 0
1561 #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask 0x00000001
1566 #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset 0
1567 #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask 0x00000001
1574 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
1575 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift 0
1581 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
1582 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift 0
1588 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask 0x000FFFFF
1589 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift 0
1594 #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask 0x00000003
1601 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask 0xFFFFFFFF
1602 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift 0
1612 #define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0
1613 #define SDMA_PKT_WRITE_TILED_HEADER_op_mask 0x000000FF
1614 #define SDMA_PKT_WRITE_TILED_HEADER_op_shift 0
1618 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0
1619 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask 0x000000FF
1624 #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset 0
1625 #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask 0x00000001
1630 #define SDMA_PKT_WRITE_TILED_HEADER_tmz_offset 0
1631 #define SDMA_PKT_WRITE_TILED_HEADER_tmz_mask 0x00000001
1636 #define SDMA_PKT_WRITE_TILED_HEADER_mip_max_offset 0
1637 #define SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask 0x0000000F
1644 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
1645 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift 0
1651 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
1652 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift 0
1658 #define SDMA_PKT_WRITE_TILED_DW_3_width_mask 0x00003FFF
1659 #define SDMA_PKT_WRITE_TILED_DW_3_width_shift 0
1665 #define SDMA_PKT_WRITE_TILED_DW_4_height_mask 0x00003FFF
1666 #define SDMA_PKT_WRITE_TILED_DW_4_height_shift 0
1671 #define SDMA_PKT_WRITE_TILED_DW_4_depth_mask 0x000007FF
1678 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask 0x00000007
1679 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift 0
1684 #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask 0x0000001F
1690 #define SDMA_PKT_WRITE_TILED_DW_5_dimension_mask 0x00000003
1696 #define SDMA_PKT_WRITE_TILED_DW_5_epitch_mask 0x0000FFFF
1703 #define SDMA_PKT_WRITE_TILED_DW_6_x_mask 0x00003FFF
1704 #define SDMA_PKT_WRITE_TILED_DW_6_x_shift 0
1709 #define SDMA_PKT_WRITE_TILED_DW_6_y_mask 0x00003FFF
1716 #define SDMA_PKT_WRITE_TILED_DW_7_z_mask 0x000007FF
1717 #define SDMA_PKT_WRITE_TILED_DW_7_z_shift 0
1722 #define SDMA_PKT_WRITE_TILED_DW_7_sw_mask 0x00000003
1729 #define SDMA_PKT_WRITE_TILED_COUNT_count_mask 0x000FFFFF
1730 #define SDMA_PKT_WRITE_TILED_COUNT_count_shift 0
1736 #define SDMA_PKT_WRITE_TILED_DATA0_data0_mask 0xFFFFFFFF
1737 #define SDMA_PKT_WRITE_TILED_DATA0_data0_shift 0
1747 #define SDMA_PKT_PTEPDE_COPY_HEADER_op_offset 0
1748 #define SDMA_PKT_PTEPDE_COPY_HEADER_op_mask 0x000000FF
1749 #define SDMA_PKT_PTEPDE_COPY_HEADER_op_shift 0
1753 #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset 0
1754 #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask 0x000000FF
1759 #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset 0
1760 #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask 0x00000001
1767 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF
1768 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift 0
1774 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF
1775 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift 0
1781 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
1782 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift 0
1788 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
1789 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift 0
1795 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask 0xFFFFFFFF
1796 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift 0
1802 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask 0xFFFFFFFF
1803 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift 0
1809 #define SDMA_PKT_PTEPDE_COPY_COUNT_count_mask 0x0007FFFF
1810 #define SDMA_PKT_PTEPDE_COPY_COUNT_count_shift 0
1820 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset 0
1821 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask 0x000000FF
1822 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift 0
1826 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset 0
1827 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask 0x000000FF
1832 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset 0
1833 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask 0x00000003
1838 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset 0
1839 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask 0x00000001
1844 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset 0
1845 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask 0x00000001
1852 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF
1853 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift 0
1859 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF
1860 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift 0
1866 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
1867 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift 0
1873 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
1874 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift 0
1880 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask 0x000000FF
1881 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift 0
1886 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask 0x000000FF
1893 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask 0x0001FFFF
1894 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift 0
1904 #define SDMA_PKT_PTEPDE_RMW_HEADER_op_offset 0
1905 #define SDMA_PKT_PTEPDE_RMW_HEADER_op_mask 0x000000FF
1906 #define SDMA_PKT_PTEPDE_RMW_HEADER_op_shift 0
1910 #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset 0
1911 #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask 0x000000FF
1916 #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset 0
1917 #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask 0x00000001
1922 #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset 0
1923 #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask 0x00000001
1928 #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset 0
1929 #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask 0x00000001
1934 #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset 0
1935 #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask 0x00000001
1942 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask 0xFFFFFFFF
1943 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift 0
1949 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask 0xFFFFFFFF
1950 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift 0
1956 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask 0xFFFFFFFF
1957 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift 0
1963 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask 0xFFFFFFFF
1964 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift 0
1970 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask 0xFFFFFFFF
1971 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift 0
1977 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask 0xFFFFFFFF
1978 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift 0
1988 #define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0
1989 #define SDMA_PKT_WRITE_INCR_HEADER_op_mask 0x000000FF
1990 #define SDMA_PKT_WRITE_INCR_HEADER_op_shift 0
1994 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0
1995 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask 0x000000FF
2002 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
2003 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift 0
2009 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
2010 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift 0
2016 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask 0xFFFFFFFF
2017 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift 0
2023 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask 0xFFFFFFFF
2024 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift 0
2030 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask 0xFFFFFFFF
2031 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift 0
2037 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask 0xFFFFFFFF
2038 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift 0
2044 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask 0xFFFFFFFF
2045 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift 0
2051 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask 0xFFFFFFFF
2052 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift 0
2058 #define SDMA_PKT_WRITE_INCR_COUNT_count_mask 0x0007FFFF
2059 #define SDMA_PKT_WRITE_INCR_COUNT_count_shift 0
2069 #define SDMA_PKT_INDIRECT_HEADER_op_offset 0
2070 #define SDMA_PKT_INDIRECT_HEADER_op_mask 0x000000FF
2071 #define SDMA_PKT_INDIRECT_HEADER_op_shift 0
2075 #define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0
2076 #define SDMA_PKT_INDIRECT_HEADER_sub_op_mask 0x000000FF
2081 #define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0
2082 #define SDMA_PKT_INDIRECT_HEADER_vmid_mask 0x0000000F
2089 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask 0xFFFFFFFF
2090 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift 0
2096 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask 0xFFFFFFFF
2097 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift 0
2103 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask 0x000FFFFF
2104 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift 0
2110 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask 0xFFFFFFFF
2111 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift 0
2117 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask 0xFFFFFFFF
2118 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift 0
2128 #define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0
2129 #define SDMA_PKT_SEMAPHORE_HEADER_op_mask 0x000000FF
2130 #define SDMA_PKT_SEMAPHORE_HEADER_op_shift 0
2134 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0
2135 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask 0x000000FF
2140 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0
2141 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask 0x00000001
2146 #define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0
2147 #define SDMA_PKT_SEMAPHORE_HEADER_signal_mask 0x00000001
2152 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0
2153 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask 0x00000001
2160 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF
2161 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift 0
2167 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF
2168 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift 0
2178 #define SDMA_PKT_FENCE_HEADER_op_offset 0
2179 #define SDMA_PKT_FENCE_HEADER_op_mask 0x000000FF
2180 #define SDMA_PKT_FENCE_HEADER_op_shift 0
2184 #define SDMA_PKT_FENCE_HEADER_sub_op_offset 0
2185 #define SDMA_PKT_FENCE_HEADER_sub_op_mask 0x000000FF
2192 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF
2193 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift 0
2199 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF
2200 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift 0
2206 #define SDMA_PKT_FENCE_DATA_data_mask 0xFFFFFFFF
2207 #define SDMA_PKT_FENCE_DATA_data_shift 0
2217 #define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0
2218 #define SDMA_PKT_SRBM_WRITE_HEADER_op_mask 0x000000FF
2219 #define SDMA_PKT_SRBM_WRITE_HEADER_op_shift 0
2223 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0
2224 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask 0x000000FF
2229 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0
2230 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask 0x0000000F
2237 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask 0x0003FFFF
2238 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift 0
2244 #define SDMA_PKT_SRBM_WRITE_DATA_data_mask 0xFFFFFFFF
2245 #define SDMA_PKT_SRBM_WRITE_DATA_data_shift 0
2255 #define SDMA_PKT_PRE_EXE_HEADER_op_offset 0
2256 #define SDMA_PKT_PRE_EXE_HEADER_op_mask 0x000000FF
2257 #define SDMA_PKT_PRE_EXE_HEADER_op_shift 0
2261 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0
2262 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask 0x000000FF
2267 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0
2268 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask 0x000000FF
2275 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF
2276 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift 0
2286 #define SDMA_PKT_COND_EXE_HEADER_op_offset 0
2287 #define SDMA_PKT_COND_EXE_HEADER_op_mask 0x000000FF
2288 #define SDMA_PKT_COND_EXE_HEADER_op_shift 0
2292 #define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0
2293 #define SDMA_PKT_COND_EXE_HEADER_sub_op_mask 0x000000FF
2300 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF
2301 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift 0
2307 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF
2308 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift 0
2314 #define SDMA_PKT_COND_EXE_REFERENCE_reference_mask 0xFFFFFFFF
2315 #define SDMA_PKT_COND_EXE_REFERENCE_reference_shift 0
2321 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF
2322 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift 0
2332 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0
2333 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask 0x000000FF
2334 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift 0
2338 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0
2339 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask 0x000000FF
2344 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0
2345 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask 0x00000003
2350 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0
2351 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask 0x00000003
2358 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
2359 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift 0
2365 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
2366 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift 0
2372 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask 0xFFFFFFFF
2373 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift 0
2379 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask 0x003FFFFF
2380 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift 0
2390 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset 0
2391 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask 0x000000FF
2392 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift 0
2396 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset 0
2397 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask 0x000000FF
2402 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset 0
2403 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask 0x00000001
2410 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask 0xFFFFFFFF
2411 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift 0
2417 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask 0xFFFFFFFF
2418 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift 0
2424 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
2425 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift 0
2431 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
2432 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift 0
2438 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask 0x03FFFFFF
2439 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift 0
2449 #define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0
2450 #define SDMA_PKT_POLL_REGMEM_HEADER_op_mask 0x000000FF
2451 #define SDMA_PKT_POLL_REGMEM_HEADER_op_shift 0
2455 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0
2456 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask 0x000000FF
2461 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0
2462 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask 0x00000001
2467 #define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0
2468 #define SDMA_PKT_POLL_REGMEM_HEADER_func_mask 0x00000007
2473 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0
2474 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask 0x00000001
2481 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask 0xFFFFFFFF
2482 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift 0
2488 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask 0xFFFFFFFF
2489 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift 0
2495 #define SDMA_PKT_POLL_REGMEM_VALUE_value_mask 0xFFFFFFFF
2496 #define SDMA_PKT_POLL_REGMEM_VALUE_value_shift 0
2502 #define SDMA_PKT_POLL_REGMEM_MASK_mask_mask 0xFFFFFFFF
2503 #define SDMA_PKT_POLL_REGMEM_MASK_mask_shift 0
2509 #define SDMA_PKT_POLL_REGMEM_DW5_interval_mask 0x0000FFFF
2510 #define SDMA_PKT_POLL_REGMEM_DW5_interval_shift 0
2515 #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask 0x00000FFF
2526 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset 0
2527 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask 0x000000FF
2528 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift 0
2532 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset 0
2533 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask 0x000000FF
2540 #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask 0x3FFFFFFF
2547 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF
2548 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0
2554 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF
2555 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0
2565 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset 0
2566 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask 0x000000FF
2567 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift 0
2571 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset 0
2572 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask 0x000000FF
2577 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset 0
2578 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask 0x00000003
2585 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF
2586 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0
2592 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF
2593 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0
2599 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask 0x0FFFFFFF
2606 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask 0xFFFFFFFF
2607 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift 0
2617 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset 0
2618 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask 0x000000FF
2619 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift 0
2623 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset 0
2624 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask 0x000000FF
2629 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset 0
2630 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask 0x00000001
2637 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask 0xFFFFFFFF
2638 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift 0
2644 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask 0xFFFFFFFF
2645 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift 0
2651 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask 0xFFFFFFFF
2652 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift 0
2658 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF
2659 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift 0
2665 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF
2666 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift 0
2672 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask 0xFFFFFFFF
2673 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift 0
2679 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask 0xFFFFFFFF
2680 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift 0
2686 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF
2687 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift 0
2693 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF
2694 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift 0
2700 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask 0xFFFFFFFF
2701 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift 0
2707 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask 0xFFFFFFFF
2708 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift 0
2714 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask 0xFFFFFFFF
2715 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift 0
2725 #define SDMA_PKT_ATOMIC_HEADER_op_offset 0
2726 #define SDMA_PKT_ATOMIC_HEADER_op_mask 0x000000FF
2727 #define SDMA_PKT_ATOMIC_HEADER_op_shift 0
2731 #define SDMA_PKT_ATOMIC_HEADER_loop_offset 0
2732 #define SDMA_PKT_ATOMIC_HEADER_loop_mask 0x00000001
2737 #define SDMA_PKT_ATOMIC_HEADER_tmz_offset 0
2738 #define SDMA_PKT_ATOMIC_HEADER_tmz_mask 0x00000001
2743 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 0
2744 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask 0x0000007F
2751 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask 0xFFFFFFFF
2752 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift 0
2758 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask 0xFFFFFFFF
2759 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift 0
2765 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask 0xFFFFFFFF
2766 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift 0
2772 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask 0xFFFFFFFF
2773 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift 0
2779 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask 0xFFFFFFFF
2780 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift 0
2786 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask 0xFFFFFFFF
2787 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift 0
2793 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask 0x00001FFF
2794 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift 0
2804 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0
2805 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask 0x000000FF
2806 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift 0
2810 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0
2811 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask 0x000000FF
2818 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask 0xFFFFFFFF
2819 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift 0
2825 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask 0xFFFFFFFF
2826 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift 0
2836 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0
2837 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask 0x000000FF
2838 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift 0
2842 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0
2843 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask 0x000000FF
2850 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF
2857 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF
2858 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift 0
2868 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0
2869 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask 0x000000FF
2870 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift 0
2874 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0
2875 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask 0x000000FF
2882 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF
2889 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF
2890 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift 0
2900 #define SDMA_PKT_TRAP_HEADER_op_offset 0
2901 #define SDMA_PKT_TRAP_HEADER_op_mask 0x000000FF
2902 #define SDMA_PKT_TRAP_HEADER_op_shift 0
2906 #define SDMA_PKT_TRAP_HEADER_sub_op_offset 0
2907 #define SDMA_PKT_TRAP_HEADER_sub_op_mask 0x000000FF
2914 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF
2915 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift 0
2925 #define SDMA_PKT_DUMMY_TRAP_HEADER_op_offset 0
2926 #define SDMA_PKT_DUMMY_TRAP_HEADER_op_mask 0x000000FF
2927 #define SDMA_PKT_DUMMY_TRAP_HEADER_op_shift 0
2931 #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset 0
2932 #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask 0x000000FF
2939 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF
2940 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift 0
2950 #define SDMA_PKT_NOP_HEADER_op_offset 0
2951 #define SDMA_PKT_NOP_HEADER_op_mask 0x000000FF
2952 #define SDMA_PKT_NOP_HEADER_op_shift 0
2956 #define SDMA_PKT_NOP_HEADER_sub_op_offset 0
2957 #define SDMA_PKT_NOP_HEADER_sub_op_mask 0x000000FF
2962 #define SDMA_PKT_NOP_HEADER_count_offset 0
2963 #define SDMA_PKT_NOP_HEADER_count_mask 0x00003FFF
2970 #define SDMA_PKT_NOP_DATA0_data0_mask 0xFFFFFFFF
2971 #define SDMA_PKT_NOP_DATA0_data0_shift 0
2981 #define SDMA_AQL_PKT_HEADER_HEADER_format_offset 0
2982 #define SDMA_AQL_PKT_HEADER_HEADER_format_mask 0x000000FF
2983 #define SDMA_AQL_PKT_HEADER_HEADER_format_shift 0
2987 #define SDMA_AQL_PKT_HEADER_HEADER_barrier_offset 0
2988 #define SDMA_AQL_PKT_HEADER_HEADER_barrier_mask 0x00000001
2993 #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset 0
2994 #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask 0x00000003
2999 #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset 0
3000 #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask 0x00000003
3005 #define SDMA_AQL_PKT_HEADER_HEADER_reserved_offset 0
3006 #define SDMA_AQL_PKT_HEADER_HEADER_reserved_mask 0x00000007
3011 #define SDMA_AQL_PKT_HEADER_HEADER_op_offset 0
3012 #define SDMA_AQL_PKT_HEADER_HEADER_op_mask 0x0000000F
3017 #define SDMA_AQL_PKT_HEADER_HEADER_subop_offset 0
3018 #define SDMA_AQL_PKT_HEADER_HEADER_subop_mask 0x00000007
3029 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset 0
3030 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask 0x000000FF
3031 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift 0
3035 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset 0
3036 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask 0x00000001
3041 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset 0
3042 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask 0x00000003
3047 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset 0
3048 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask 0x00000003
3053 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset 0
3054 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask 0x00000007
3059 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset 0
3060 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask 0x0000000F
3065 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset 0
3066 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask 0x00000007
3073 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF
3074 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift 0
3080 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask 0xFFFFFFFF
3081 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift 0
3087 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask 0xFFFFFFFF
3088 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift 0
3094 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF
3095 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift 0
3101 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003
3107 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003
3114 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF
3115 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0
3121 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF
3122 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0
3128 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
3129 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0
3135 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
3136 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0
3142 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask 0xFFFFFFFF
3143 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift 0
3149 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask 0xFFFFFFFF
3150 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift 0
3156 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF
3157 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift 0
3163 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF
3164 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift 0
3170 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF
3171 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0
3177 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF
3178 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0
3188 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset 0
3189 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask 0x000000FF
3190 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift 0
3194 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset 0
3195 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask 0x00000001
3200 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset 0
3201 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask 0x00000003
3206 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset 0
3207 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask 0x00000003
3212 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset 0
3213 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask 0x00000007
3218 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset 0
3219 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask 0x0000000F
3224 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset 0
3225 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask 0x00000007
3232 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF
3233 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift 0
3239 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask 0xFFFFFFFF
3240 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift 0
3246 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask 0xFFFFFFFF
3247 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift 0
3253 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask 0xFFFFFFFF
3254 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift 0
3260 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask 0xFFFFFFFF
3261 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift 0
3267 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask 0xFFFFFFFF
3268 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift 0
3274 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask 0xFFFFFFFF
3275 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift 0
3281 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask 0xFFFFFFFF
3282 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift 0
3288 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask 0xFFFFFFFF
3289 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift 0
3295 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask 0xFFFFFFFF
3296 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift 0
3302 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask 0xFFFFFFFF
3303 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift 0
3309 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF
3310 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift 0
3316 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF
3317 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift 0
3323 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF
3324 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0
3330 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF
3331 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0