amd/amdgpu/uvd_v7_0.c

75 	return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);  in uvd_v7_0_ring_get_rptr()
89 	if (ring == &adev->uvd.inst[ring->me].ring_enc[0])  in uvd_v7_0_enc_ring_get_rptr()
90 		return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR);  in uvd_v7_0_enc_ring_get_rptr()
92 		return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2);  in uvd_v7_0_enc_ring_get_rptr()
106 	return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);  in uvd_v7_0_ring_get_wptr()
123 	if (ring == &adev->uvd.inst[ring->me].ring_enc[0])  in uvd_v7_0_enc_ring_get_wptr()
124 		return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR);  in uvd_v7_0_enc_ring_get_wptr()
126 		return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2);  in uvd_v7_0_enc_ring_get_wptr()
140 	WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));  in uvd_v7_0_ring_set_wptr()
161 	if (ring == &adev->uvd.inst[ring->me].ring_enc[0])  in uvd_v7_0_enc_ring_set_wptr()
162 		WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR,  in uvd_v7_0_enc_ring_set_wptr()
165 		WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2,  in uvd_v7_0_enc_ring_set_wptr()
448 			sprintf(ring->name, "uvd_%d", ring->me);  in uvd_v7_0_sw_init()
459 			sprintf(ring->name, "uvd_enc_%d.%d", ring->me, i);  in uvd_v7_0_sw_init()
1188 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));  in uvd_v7_0_ring_emit_fence()
1191 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));  in uvd_v7_0_ring_emit_fence()
1194 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));  in uvd_v7_0_ring_emit_fence()
1197 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));  in uvd_v7_0_ring_emit_fence()
1201 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));  in uvd_v7_0_ring_emit_fence()
1204 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));  in uvd_v7_0_ring_emit_fence()
1207 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));  in uvd_v7_0_ring_emit_fence()
1258 	WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD);  in uvd_v7_0_ring_test_ring()
1264 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));  in uvd_v7_0_ring_test_ring()
1268 		tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID);  in uvd_v7_0_ring_test_ring()
1296 	if (!ring->me)  in uvd_v7_0_ring_patch_cs_in_place()
1329 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0));  in uvd_v7_0_ring_emit_ib()
1333 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));  in uvd_v7_0_ring_emit_ib()
1336 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));  in uvd_v7_0_ring_emit_ib()
1339 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0));  in uvd_v7_0_ring_emit_ib()
1373 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));  in uvd_v7_0_ring_emit_wreg()
1376 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));  in uvd_v7_0_ring_emit_wreg()
1379 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));  in uvd_v7_0_ring_emit_wreg()
1389 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));  in uvd_v7_0_ring_emit_reg_wait()
1392 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));  in uvd_v7_0_ring_emit_reg_wait()
1395 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0));  in uvd_v7_0_ring_emit_reg_wait()
1398 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));  in uvd_v7_0_ring_emit_reg_wait()
1425 		amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0));  in uvd_v7_0_ring_insert_nop()
1495 	    (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) &
1501 		adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset;
1504 		adev->uvd.inst[ring->me].srbm_soft_reset = 0;
1513 	if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1525 	if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1527 	srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset;
1555 	if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1618 	data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL);
1619 	data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1620 	data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL);
1664 	WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);
1665 	WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0);
1666 	WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1667 	WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2);
1674 	data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE);
1675 	data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1707 	WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data);
1708 	WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1767 	WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1877 		adev->uvd.inst[i].ring.me = i;  in uvd_v7_0_set_ring_funcs()
1891 			adev->uvd.inst[j].ring_enc[i].me = j;  in uvd_v7_0_set_enc_ring_funcs()