Lines Matching +full:0 +full:x000007ff
26 #define SDMA_OP_NOP 0
41 #define SDMA_SUBOP_TIMESTAMP_SET 0
44 #define SDMA_SUBOP_COPY_LINEAR 0
50 #define SDMA_SUBOP_WRITE_LINEAR 0
54 #define SDMA_PKT_HEADER_op_offset 0
55 #define SDMA_PKT_HEADER_op_mask 0x000000FF
56 #define SDMA_PKT_HEADER_op_shift 0
60 #define SDMA_PKT_HEADER_sub_op_offset 0
61 #define SDMA_PKT_HEADER_sub_op_mask 0x000000FF
71 #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0
72 #define SDMA_PKT_COPY_LINEAR_HEADER_op_mask 0x000000FF
73 #define SDMA_PKT_COPY_LINEAR_HEADER_op_shift 0
77 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0
78 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask 0x000000FF
83 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0
84 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask 0x00000001
91 #define SDMA_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF
92 #define SDMA_PKT_COPY_LINEAR_COUNT_count_shift 0
98 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003
104 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_mask 0x00000001
110 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003
116 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_mask 0x00000001
123 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF
124 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0
130 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF
131 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0
137 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
138 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0
144 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
145 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0
155 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0
156 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask 0x000000FF
157 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift 0
161 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0
162 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask 0x000000FF
167 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0
168 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask 0x00000001
175 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask 0x003FFFFF
176 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift 0
182 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask 0x00000003
188 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_mask 0x00000001
194 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask 0x00000003
200 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_mask 0x00000001
206 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask 0x00000003
212 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_mask 0x00000001
219 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF
220 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0
226 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF
227 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0
233 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask 0xFFFFFFFF
234 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift 0
240 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask 0xFFFFFFFF
241 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift 0
247 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask 0xFFFFFFFF
248 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift 0
254 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask 0xFFFFFFFF
255 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift 0
265 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0
266 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask 0x000000FF
267 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift 0
271 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0
272 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask 0x000000FF
277 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0
278 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask 0x00000007
285 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF
286 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift 0
292 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF
293 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift 0
299 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask 0x00003FFF
300 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift 0
305 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask 0x00003FFF
312 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask 0x000007FF
313 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift 0
318 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask 0x00003FFF
325 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask 0x0FFFFFFF
326 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift 0
332 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
333 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift 0
339 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
340 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift 0
346 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask 0x00003FFF
347 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift 0
352 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask 0x00003FFF
359 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask 0x000007FF
360 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift 0
365 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask 0x00003FFF
372 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask 0x0FFFFFFF
373 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift 0
379 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask 0x00003FFF
380 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift 0
385 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask 0x00003FFF
392 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask 0x000007FF
393 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift 0
398 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask 0x00000003
404 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_mask 0x00000001
410 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask 0x00000003
416 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_mask 0x00000001
427 #define SDMA_PKT_COPY_TILED_HEADER_op_offset 0
428 #define SDMA_PKT_COPY_TILED_HEADER_op_mask 0x000000FF
429 #define SDMA_PKT_COPY_TILED_HEADER_op_shift 0
433 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0
434 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask 0x000000FF
439 #define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0
440 #define SDMA_PKT_COPY_TILED_HEADER_detile_mask 0x00000001
447 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF
448 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift 0
454 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF
455 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift 0
461 #define SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_mask 0x000007FF
462 #define SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_shift 0
467 #define SDMA_PKT_COPY_TILED_DW_3_height_mask 0x00003FFF
474 #define SDMA_PKT_COPY_TILED_DW_4_slice_pitch_mask 0x003FFFFF
475 #define SDMA_PKT_COPY_TILED_DW_4_slice_pitch_shift 0
481 #define SDMA_PKT_COPY_TILED_DW_5_element_size_mask 0x00000007
482 #define SDMA_PKT_COPY_TILED_DW_5_element_size_shift 0
487 #define SDMA_PKT_COPY_TILED_DW_5_array_mode_mask 0x0000000F
493 #define SDMA_PKT_COPY_TILED_DW_5_mit_mode_mask 0x00000007
499 #define SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_mask 0x00000007
505 #define SDMA_PKT_COPY_TILED_DW_5_bank_w_mask 0x00000003
511 #define SDMA_PKT_COPY_TILED_DW_5_bank_h_mask 0x00000003
517 #define SDMA_PKT_COPY_TILED_DW_5_num_bank_mask 0x00000003
523 #define SDMA_PKT_COPY_TILED_DW_5_mat_aspt_mask 0x00000003
529 #define SDMA_PKT_COPY_TILED_DW_5_pipe_config_mask 0x0000001F
536 #define SDMA_PKT_COPY_TILED_DW_6_x_mask 0x00003FFF
537 #define SDMA_PKT_COPY_TILED_DW_6_x_shift 0
542 #define SDMA_PKT_COPY_TILED_DW_6_y_mask 0x00003FFF
549 #define SDMA_PKT_COPY_TILED_DW_7_z_mask 0x00000FFF
550 #define SDMA_PKT_COPY_TILED_DW_7_z_shift 0
555 #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask 0x00000003
561 #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask 0x00000003
568 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF
569 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift 0
575 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF
576 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift 0
582 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF
583 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift 0
589 #define SDMA_PKT_COPY_TILED_COUNT_count_mask 0x000FFFFF
590 #define SDMA_PKT_COPY_TILED_COUNT_count_shift 0
600 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0
601 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask 0x000000FF
602 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift 0
606 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0
607 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask 0x000000FF
612 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0
613 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask 0x00000001
618 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0
619 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask 0x00000001
626 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask 0xFFFFFFFF
627 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift 0
633 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask 0xFFFFFFFF
634 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift 0
640 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask 0xFFFFFFFF
641 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift 0
647 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask 0xFFFFFFFF
648 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift 0
654 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_mask 0x000007FF
655 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_shift 0
660 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_mask 0x00003FFF
667 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_mask 0x003FFFFF
668 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_shift 0
674 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask 0x00000007
675 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift 0
680 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_mask 0x0000000F
686 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_mask 0x00000007
692 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_mask 0x00000007
698 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_mask 0x00000003
704 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_mask 0x00000003
710 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_mask 0x00000003
716 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_mask 0x00000003
722 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_mask 0x0000001F
729 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask 0x00003FFF
730 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift 0
735 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask 0x00003FFF
742 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask 0x00000FFF
743 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift 0
749 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask 0x00000003
755 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_mask 0x00000001
761 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask 0x00000003
767 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask 0x00000003
774 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF
775 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift 0
781 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF
782 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift 0
788 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF
789 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift 0
795 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask 0x000FFFFF
796 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift 0
806 #define SDMA_PKT_COPY_T2T_HEADER_op_offset 0
807 #define SDMA_PKT_COPY_T2T_HEADER_op_mask 0x000000FF
808 #define SDMA_PKT_COPY_T2T_HEADER_op_shift 0
812 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0
813 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask 0x000000FF
820 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF
821 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift 0
827 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF
828 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift 0
834 #define SDMA_PKT_COPY_T2T_DW_3_src_x_mask 0x00003FFF
835 #define SDMA_PKT_COPY_T2T_DW_3_src_x_shift 0
840 #define SDMA_PKT_COPY_T2T_DW_3_src_y_mask 0x00003FFF
847 #define SDMA_PKT_COPY_T2T_DW_4_src_z_mask 0x000007FF
848 #define SDMA_PKT_COPY_T2T_DW_4_src_z_shift 0
853 #define SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_mask 0x00000FFF
860 #define SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_mask 0x003FFFFF
861 #define SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_shift 0
867 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask 0x00000007
868 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift 0
873 #define SDMA_PKT_COPY_T2T_DW_6_src_array_mode_mask 0x0000000F
879 #define SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_mask 0x00000007
885 #define SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_mask 0x00000007
891 #define SDMA_PKT_COPY_T2T_DW_6_src_bank_w_mask 0x00000003
897 #define SDMA_PKT_COPY_T2T_DW_6_src_bank_h_mask 0x00000003
903 #define SDMA_PKT_COPY_T2T_DW_6_src_num_bank_mask 0x00000003
909 #define SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_mask 0x00000003
915 #define SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_mask 0x0000001F
922 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
923 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift 0
929 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
930 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift 0
936 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask 0x00003FFF
937 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift 0
942 #define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask 0x00003FFF
949 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask 0x000007FF
950 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift 0
955 #define SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_mask 0x00000FFF
962 #define SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_mask 0x003FFFFF
963 #define SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_shift 0
969 #define SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_mask 0x0000000F
975 #define SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_mask 0x00000007
981 #define SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_mask 0x00000007
987 #define SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_mask 0x00000003
993 #define SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_mask 0x00000003
999 #define SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_mask 0x00000003
1005 #define SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_mask 0x00000003
1011 #define SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_mask 0x0000001F
1018 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask 0x00003FFF
1019 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift 0
1024 #define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask 0x00003FFF
1031 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask 0x000007FF
1032 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift 0
1037 #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask 0x00000003
1043 #define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask 0x00000003
1054 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0
1055 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask 0x000000FF
1056 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift 0
1060 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0
1061 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask 0x000000FF
1066 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0
1067 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask 0x00000001
1074 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF
1075 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift 0
1081 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF
1082 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift 0
1088 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask 0x00003FFF
1089 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift 0
1094 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask 0x00003FFF
1101 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask 0x000007FF
1102 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift 0
1107 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_mask 0x00000FFF
1114 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_mask 0x003FFFFF
1115 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_shift 0
1121 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask 0x00000007
1122 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift 0
1127 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_mask 0x0000000F
1133 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_mask 0x00000007
1139 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_mask 0x00000007
1145 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_mask 0x00000003
1151 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_mask 0x00000003
1157 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_mask 0x00000003
1163 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_mask 0x00000003
1169 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_mask 0x0000001F
1176 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF
1177 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift 0
1183 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF
1184 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift 0
1190 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask 0x00003FFF
1191 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift 0
1196 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask 0x00003FFF
1203 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask 0x000007FF
1204 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift 0
1209 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask 0x00003FFF
1216 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask 0x0FFFFFFF
1217 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift 0
1223 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask 0x00003FFF
1224 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift 0
1229 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask 0x00003FFF
1236 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask 0x000007FF
1237 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift 0
1242 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask 0x00000003
1248 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask 0x00000003
1259 #define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0
1260 #define SDMA_PKT_COPY_STRUCT_HEADER_op_mask 0x000000FF
1261 #define SDMA_PKT_COPY_STRUCT_HEADER_op_shift 0
1265 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0
1266 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask 0x000000FF
1271 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0
1272 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask 0x00000001
1279 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask 0xFFFFFFFF
1280 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift 0
1286 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask 0xFFFFFFFF
1287 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift 0
1293 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask 0xFFFFFFFF
1294 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift 0
1300 #define SDMA_PKT_COPY_STRUCT_COUNT_count_mask 0xFFFFFFFF
1301 #define SDMA_PKT_COPY_STRUCT_COUNT_count_shift 0
1307 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask 0x000007FF
1308 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift 0
1313 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask 0x00000003
1319 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_mask 0x00000001
1325 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask 0x00000003
1331 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_mask 0x00000001
1338 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF
1339 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift 0
1345 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF
1346 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift 0
1356 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0
1357 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask 0x000000FF
1358 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift 0
1362 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0
1363 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask 0x000000FF
1370 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
1371 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift 0
1377 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
1378 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift 0
1384 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask 0x003FFFFF
1385 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift 0
1390 #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask 0x00000003
1397 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask 0xFFFFFFFF
1398 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift 0
1408 #define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0
1409 #define SDMA_PKT_WRITE_TILED_HEADER_op_mask 0x000000FF
1410 #define SDMA_PKT_WRITE_TILED_HEADER_op_shift 0
1414 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0
1415 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask 0x000000FF
1422 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
1423 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift 0
1429 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
1430 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift 0
1436 #define SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_mask 0x000007FF
1437 #define SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_shift 0
1442 #define SDMA_PKT_WRITE_TILED_DW_3_height_mask 0x00003FFF
1449 #define SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_mask 0x003FFFFF
1450 #define SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_shift 0
1456 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask 0x00000007
1457 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift 0
1462 #define SDMA_PKT_WRITE_TILED_DW_5_array_mode_mask 0x0000000F
1468 #define SDMA_PKT_WRITE_TILED_DW_5_mit_mode_mask 0x00000007
1474 #define SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_mask 0x00000007
1480 #define SDMA_PKT_WRITE_TILED_DW_5_bank_w_mask 0x00000003
1486 #define SDMA_PKT_WRITE_TILED_DW_5_bank_h_mask 0x00000003
1492 #define SDMA_PKT_WRITE_TILED_DW_5_num_bank_mask 0x00000003
1498 #define SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_mask 0x00000003
1504 #define SDMA_PKT_WRITE_TILED_DW_5_pipe_config_mask 0x0000001F
1511 #define SDMA_PKT_WRITE_TILED_DW_6_x_mask 0x00003FFF
1512 #define SDMA_PKT_WRITE_TILED_DW_6_x_shift 0
1517 #define SDMA_PKT_WRITE_TILED_DW_6_y_mask 0x00003FFF
1524 #define SDMA_PKT_WRITE_TILED_DW_7_z_mask 0x00000FFF
1525 #define SDMA_PKT_WRITE_TILED_DW_7_z_shift 0
1530 #define SDMA_PKT_WRITE_TILED_DW_7_sw_mask 0x00000003
1537 #define SDMA_PKT_WRITE_TILED_COUNT_count_mask 0x003FFFFF
1538 #define SDMA_PKT_WRITE_TILED_COUNT_count_shift 0
1544 #define SDMA_PKT_WRITE_TILED_DATA0_data0_mask 0xFFFFFFFF
1545 #define SDMA_PKT_WRITE_TILED_DATA0_data0_shift 0
1555 #define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0
1556 #define SDMA_PKT_WRITE_INCR_HEADER_op_mask 0x000000FF
1557 #define SDMA_PKT_WRITE_INCR_HEADER_op_shift 0
1561 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0
1562 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask 0x000000FF
1569 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
1570 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift 0
1576 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
1577 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift 0
1583 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask 0xFFFFFFFF
1584 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift 0
1590 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask 0xFFFFFFFF
1591 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift 0
1597 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask 0xFFFFFFFF
1598 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift 0
1604 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask 0xFFFFFFFF
1605 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift 0
1611 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask 0xFFFFFFFF
1612 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift 0
1618 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask 0xFFFFFFFF
1619 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift 0
1625 #define SDMA_PKT_WRITE_INCR_COUNT_count_mask 0x0007FFFF
1626 #define SDMA_PKT_WRITE_INCR_COUNT_count_shift 0
1636 #define SDMA_PKT_INDIRECT_HEADER_op_offset 0
1637 #define SDMA_PKT_INDIRECT_HEADER_op_mask 0x000000FF
1638 #define SDMA_PKT_INDIRECT_HEADER_op_shift 0
1642 #define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0
1643 #define SDMA_PKT_INDIRECT_HEADER_sub_op_mask 0x000000FF
1648 #define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0
1649 #define SDMA_PKT_INDIRECT_HEADER_vmid_mask 0x0000000F
1656 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask 0xFFFFFFFF
1657 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift 0
1663 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask 0xFFFFFFFF
1664 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift 0
1670 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask 0x000FFFFF
1671 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift 0
1677 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask 0xFFFFFFFF
1678 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift 0
1684 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask 0xFFFFFFFF
1685 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift 0
1695 #define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0
1696 #define SDMA_PKT_SEMAPHORE_HEADER_op_mask 0x000000FF
1697 #define SDMA_PKT_SEMAPHORE_HEADER_op_shift 0
1701 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0
1702 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask 0x000000FF
1707 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0
1708 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask 0x00000001
1713 #define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0
1714 #define SDMA_PKT_SEMAPHORE_HEADER_signal_mask 0x00000001
1719 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0
1720 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask 0x00000001
1727 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF
1728 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift 0
1734 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF
1735 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift 0
1745 #define SDMA_PKT_FENCE_HEADER_op_offset 0
1746 #define SDMA_PKT_FENCE_HEADER_op_mask 0x000000FF
1747 #define SDMA_PKT_FENCE_HEADER_op_shift 0
1751 #define SDMA_PKT_FENCE_HEADER_sub_op_offset 0
1752 #define SDMA_PKT_FENCE_HEADER_sub_op_mask 0x000000FF
1759 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF
1760 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift 0
1766 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF
1767 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift 0
1773 #define SDMA_PKT_FENCE_DATA_data_mask 0xFFFFFFFF
1774 #define SDMA_PKT_FENCE_DATA_data_shift 0
1784 #define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0
1785 #define SDMA_PKT_SRBM_WRITE_HEADER_op_mask 0x000000FF
1786 #define SDMA_PKT_SRBM_WRITE_HEADER_op_shift 0
1790 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0
1791 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask 0x000000FF
1796 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0
1797 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask 0x0000000F
1804 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask 0x0000FFFF
1805 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift 0
1811 #define SDMA_PKT_SRBM_WRITE_DATA_data_mask 0xFFFFFFFF
1812 #define SDMA_PKT_SRBM_WRITE_DATA_data_shift 0
1822 #define SDMA_PKT_PRE_EXE_HEADER_op_offset 0
1823 #define SDMA_PKT_PRE_EXE_HEADER_op_mask 0x000000FF
1824 #define SDMA_PKT_PRE_EXE_HEADER_op_shift 0
1828 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0
1829 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask 0x000000FF
1834 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0
1835 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask 0x000000FF
1842 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF
1843 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift 0
1853 #define SDMA_PKT_COND_EXE_HEADER_op_offset 0
1854 #define SDMA_PKT_COND_EXE_HEADER_op_mask 0x000000FF
1855 #define SDMA_PKT_COND_EXE_HEADER_op_shift 0
1859 #define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0
1860 #define SDMA_PKT_COND_EXE_HEADER_sub_op_mask 0x000000FF
1867 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF
1868 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift 0
1874 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF
1875 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift 0
1881 #define SDMA_PKT_COND_EXE_REFERENCE_reference_mask 0xFFFFFFFF
1882 #define SDMA_PKT_COND_EXE_REFERENCE_reference_shift 0
1888 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF
1889 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift 0
1899 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0
1900 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask 0x000000FF
1901 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift 0
1905 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0
1906 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask 0x000000FF
1911 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0
1912 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask 0x00000003
1917 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0
1918 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask 0x00000003
1925 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF
1926 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift 0
1932 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF
1933 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift 0
1939 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask 0xFFFFFFFF
1940 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift 0
1946 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask 0x003FFFFF
1947 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift 0
1957 #define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0
1958 #define SDMA_PKT_POLL_REGMEM_HEADER_op_mask 0x000000FF
1959 #define SDMA_PKT_POLL_REGMEM_HEADER_op_shift 0
1963 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0
1964 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask 0x000000FF
1969 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0
1970 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask 0x00000001
1975 #define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0
1976 #define SDMA_PKT_POLL_REGMEM_HEADER_func_mask 0x00000007
1981 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0
1982 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask 0x00000001
1989 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask 0xFFFFFFFF
1990 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift 0
1996 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask 0xFFFFFFFF
1997 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift 0
2003 #define SDMA_PKT_POLL_REGMEM_VALUE_value_mask 0xFFFFFFFF
2004 #define SDMA_PKT_POLL_REGMEM_VALUE_value_shift 0
2010 #define SDMA_PKT_POLL_REGMEM_MASK_mask_mask 0xFFFFFFFF
2011 #define SDMA_PKT_POLL_REGMEM_MASK_mask_shift 0
2017 #define SDMA_PKT_POLL_REGMEM_DW5_interval_mask 0x0000FFFF
2018 #define SDMA_PKT_POLL_REGMEM_DW5_interval_shift 0
2023 #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask 0x00000FFF
2034 #define SDMA_PKT_ATOMIC_HEADER_op_offset 0
2035 #define SDMA_PKT_ATOMIC_HEADER_op_mask 0x000000FF
2036 #define SDMA_PKT_ATOMIC_HEADER_op_shift 0
2040 #define SDMA_PKT_ATOMIC_HEADER_loop_offset 0
2041 #define SDMA_PKT_ATOMIC_HEADER_loop_mask 0x00000001
2046 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 0
2047 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask 0x0000007F
2054 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask 0xFFFFFFFF
2055 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift 0
2061 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask 0xFFFFFFFF
2062 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift 0
2068 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask 0xFFFFFFFF
2069 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift 0
2075 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask 0xFFFFFFFF
2076 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift 0
2082 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask 0xFFFFFFFF
2083 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift 0
2089 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask 0xFFFFFFFF
2090 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift 0
2096 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask 0x00001FFF
2097 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift 0
2107 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0
2108 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask 0x000000FF
2109 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift 0
2113 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0
2114 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask 0x000000FF
2121 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask 0xFFFFFFFF
2122 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift 0
2128 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask 0xFFFFFFFF
2129 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift 0
2139 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0
2140 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask 0x000000FF
2141 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift 0
2145 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0
2146 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask 0x000000FF
2153 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF
2160 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF
2161 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift 0
2171 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0
2172 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask 0x000000FF
2173 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift 0
2177 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0
2178 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask 0x000000FF
2185 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF
2192 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF
2193 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift 0
2203 #define SDMA_PKT_TRAP_HEADER_op_offset 0
2204 #define SDMA_PKT_TRAP_HEADER_op_mask 0x000000FF
2205 #define SDMA_PKT_TRAP_HEADER_op_shift 0
2209 #define SDMA_PKT_TRAP_HEADER_sub_op_offset 0
2210 #define SDMA_PKT_TRAP_HEADER_sub_op_mask 0x000000FF
2217 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF
2218 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift 0
2228 #define SDMA_PKT_NOP_HEADER_op_offset 0
2229 #define SDMA_PKT_NOP_HEADER_op_mask 0x000000FF
2230 #define SDMA_PKT_NOP_HEADER_op_shift 0
2234 #define SDMA_PKT_NOP_HEADER_sub_op_offset 0
2235 #define SDMA_PKT_NOP_HEADER_sub_op_mask 0x000000FF
2240 #define SDMA_PKT_NOP_HEADER_count_offset 0
2241 #define SDMA_PKT_NOP_HEADER_count_mask 0x00003FFF