Lines Matching +full:3 +full:- +full:31
35 #define PACKET_TYPE3 3
37 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
59 #define PACKETJ_CONDITION_CHECK3 3
68 #define PACKETJ_TYPE3 3
85 /* Packet 3 types */
89 #define CE_PARTITION_BASE 3
117 /* 0 - register
118 * 1 - memory (sync - via GRBM)
119 * 2 - gl2
120 * 3 - gds
121 * 4 - reserved
122 * 5 - memory (async - direct)
127 /* 0 - LRU
128 * 1 - Stream
131 /* 0 - me
132 * 1 - pfp
133 * 2 - ce
143 /* 0 - always
144 * 1 - <
145 * 2 - <=
146 * 3 - ==
147 * 4 - !=
148 * 5 - >=
149 * 6 - >
152 /* 0 - reg
153 * 1 - mem
156 /* 0 - wait_reg_mem
157 * 1 - wr_wait_wr_reg
160 /* 0 - me
161 * 1 - pfp
166 /* 0 - LRU
167 * 1 - Stream
168 * 2 - Bypass
178 /* 0 - any non-TS event
179 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
180 * 2 - SAMPLE_PIPELINESTAT
181 * 3 - SAMPLE_STREAMOUTSTAT*
182 * 4 - *S_PARTIAL_FLUSH
197 /* 0 - discard
198 * 1 - send low 32bit data
199 * 2 - send 64bit data
200 * 3 - send 64bit GPU counter value
201 * 4 - send 64bit sys counter value
204 /* 0 - none
205 * 1 - interrupt only (DATA_SEL = 0)
206 * 2 - interrupt when data write is confirmed
209 /* 0 - MC
210 * 1 - TC/L2
217 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
221 * 3. SRC_ADDR_LO or DATA [31:0]
222 * 4. SRC_ADDR_HI [31:0]
223 * 5. DST_ADDR_LO [31:0]
229 /* 0 - ME
230 * 1 - PFP
233 /* 0 - LRU
234 * 1 - Stream
237 /* 0 - DST_ADDR using DAS
238 * 1 - GDS
239 * 3 - DST_ADDR using L2
242 /* 0 - LRU
243 * 1 - Stream
246 /* 0 - SRC_ADDR using SAS
247 * 1 - GDS
248 * 2 - DATA
249 * 3 - SRC_ADDR using L2
251 # define PACKET3_DMA_DATA_CP_SYNC (1 << 31)
254 /* 0 - memory
255 * 1 - register
258 /* 0 - memory
259 * 1 - register
267 * 2.1 ENGINE_SEL [31:31]
268 * 3. COHER_SIZE [31:0]
270 * 5. COHER_BASE_LO [31:0]
275 #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_NC_ACTION_ENA(x) ((x) << 3)
335 * 3. QUEUE_MASK_LO [31:0]
336 * 4. QUEUE_MASK_HI [31:0]
337 * 5. GWS_MASK_LO [31:0]
338 * 6. GWS_MASK_HI [31:0]
348 * 3. CONTROL2
349 * 4. MQD_ADDR_LO [31:0]
350 * 5. MQD_ADDR_HI [31:0]
351 * 6. WPTR_ADDR_LO [31:0]
352 * 7. WPTR_ADDR_HI [31:0]
370 * 3. CONTROL2
377 /* 0 - PREEMPT_QUEUES
378 * 1 - RESET_QUEUES
379 * 2 - DISABLE_PROCESS_QUEUES
380 * 3 - PREEMPT_QUEUES_NO_UNMAP
400 * 3. CONTROL2
401 * 4. ADDR_LO [31:0]
402 * 5. ADDR_HI [31:0]
403 * 6. DATA_LO [31:0]
404 * 7. DATA_HI [31:0]
418 * 2. RESERVED [31:0]